Index: llvm/include/llvm/IR/IRBuilder.h =================================================================== --- llvm/include/llvm/IR/IRBuilder.h +++ llvm/include/llvm/IR/IRBuilder.h @@ -1138,16 +1138,6 @@ // Instruction creation methods: Binary Operators //===--------------------------------------------------------------------===// private: - BinaryOperator *CreateInsertNUWNSWBinOp(BinaryOperator::BinaryOps Opc, - Value *LHS, Value *RHS, - const Twine &Name, - bool HasNUW, bool HasNSW) { - BinaryOperator *BO = Insert(BinaryOperator::Create(Opc, LHS, RHS), Name); - if (HasNUW) BO->setHasNoUnsignedWrap(); - if (HasNSW) BO->setHasNoSignedWrap(); - return BO; - } - Instruction *setFPAttrs(Instruction *I, MDNode *FPMD, FastMathFlags FMF) const { if (!FPMD) @@ -1199,11 +1189,7 @@ public: Value *CreateAdd(Value *LHS, Value *RHS, const Twine &Name = "", bool HasNUW = false, bool HasNSW = false) { - if (Value *V = - Folder.FoldNoWrapBinOp(Instruction::Add, LHS, RHS, HasNUW, HasNSW)) - return V; - return CreateInsertNUWNSWBinOp(Instruction::Add, LHS, RHS, Name, HasNUW, - HasNSW); + return CreateNoWrapBinOp(Instruction::Add, LHS, RHS, HasNUW, HasNSW, Name); } Value *CreateNSWAdd(Value *LHS, Value *RHS, const Twine &Name = "") { @@ -1216,11 +1202,7 @@ Value *CreateSub(Value *LHS, Value *RHS, const Twine &Name = "", bool HasNUW = false, bool HasNSW = false) { - if (Value *V = - Folder.FoldNoWrapBinOp(Instruction::Sub, LHS, RHS, HasNUW, HasNSW)) - return V; - return CreateInsertNUWNSWBinOp(Instruction::Sub, LHS, RHS, Name, HasNUW, - HasNSW); + return CreateNoWrapBinOp(Instruction::Sub, LHS, RHS, HasNUW, HasNSW, Name); } Value *CreateNSWSub(Value *LHS, Value *RHS, const Twine &Name = "") { @@ -1233,11 +1215,7 @@ Value *CreateMul(Value *LHS, Value *RHS, const Twine &Name = "", bool HasNUW = false, bool HasNSW = false) { - if (Value *V = - Folder.FoldNoWrapBinOp(Instruction::Mul, LHS, RHS, HasNUW, HasNSW)) - return V; - return CreateInsertNUWNSWBinOp(Instruction::Mul, LHS, RHS, Name, HasNUW, - HasNSW); + return CreateNoWrapBinOp(Instruction::Mul, LHS, RHS, HasNUW, HasNSW, Name); } Value *CreateNSWMul(Value *LHS, Value *RHS, const Twine &Name = "") { @@ -1288,11 +1266,7 @@ Value *CreateShl(Value *LHS, Value *RHS, const Twine &Name = "", bool HasNUW = false, bool HasNSW = false) { - if (Value *V = - Folder.FoldNoWrapBinOp(Instruction::Shl, LHS, RHS, HasNUW, HasNSW)) - return V; - return CreateInsertNUWNSWBinOp(Instruction::Shl, LHS, RHS, Name, - HasNUW, HasNSW); + return CreateNoWrapBinOp(Instruction::Shl, LHS, RHS, HasNUW, HasNSW, Name); } Value *CreateShl(Value *LHS, const APInt &RHS, const Twine &Name = "", @@ -1545,6 +1519,19 @@ return Insert(BinOp, Name); } + Value *CreateNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, + bool HasNUW, bool HasNSW, const Twine &Name = "") { + if (Value *V = Folder.FoldNoWrapBinOp(Opc, LHS, RHS, HasNUW, HasNSW)) + return V; + + BinaryOperator *BO = Insert(BinaryOperator::Create(Opc, LHS, RHS), Name); + if (HasNUW) + BO->setHasNoUnsignedWrap(); + if (HasNSW) + BO->setHasNoSignedWrap(); + return BO; + } + Value *CreateLogicalAnd(Value *Cond1, Value *Cond2, const Twine &Name = "") { assert(Cond2->getType()->isIntOrIntVectorTy(1)); return CreateSelect(Cond1, Cond2, Index: llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp =================================================================== --- llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp +++ llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp @@ -273,15 +273,10 @@ } // If we haven't found this binop, insert it. - // TODO: Use the Builder, which will make CreateBinOp below fold with - // InstSimplifyFolder. - Instruction *BO = Builder.Insert(BinaryOperator::Create(Opcode, LHS, RHS)); - BO->setDebugLoc(Loc); - if (Flags & SCEV::FlagNUW) - BO->setHasNoUnsignedWrap(); - if (Flags & SCEV::FlagNSW) - BO->setHasNoSignedWrap(); - + Value *BO = Builder.CreateNoWrapBinOp(Opcode, LHS, RHS, Flags & SCEV::FlagNUW, + Flags & SCEV::FlagNSW); + if (auto *I = dyn_cast(BO)) + I->setDebugLoc(Loc); return BO; } Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-le-simple.ll =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-le-simple.ll +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-le-simple.ll @@ -96,17 +96,18 @@ define void @cbz_exit_minsize(i32* %in, i32* %res) #0 { ; CHECK-LABEL: cbz_exit_minsize: ; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: .LBB3_1: @ %loop ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: ldr.w r3, [r0, r2, lsl #2] +; CHECK-NEXT: ldr.w r4, [r0, r2, lsl #2] +; CHECK-NEXT: mov r3, r2 ; CHECK-NEXT: adds r2, #1 -; CHECK-NEXT: cmp r3, #0 +; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: bne .LBB3_1 ; CHECK-NEXT: @ %bb.2: @ %exit -; CHECK-NEXT: subs r0, r2, #1 -; CHECK-NEXT: str r0, [r1] -; CHECK-NEXT: bx lr +; CHECK-NEXT: str r3, [r1] +; CHECK-NEXT: pop {r4, pc} entry: br label %loop @@ -126,17 +127,18 @@ define void @cbnz_exit_minsize(i32* %in, i32* %res) #0 { ; CHECK-LABEL: cbnz_exit_minsize: ; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: .LBB4_1: @ %loop ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: ldr.w r3, [r0, r2, lsl #2] +; CHECK-NEXT: ldr.w r4, [r0, r2, lsl #2] +; CHECK-NEXT: mov r3, r2 ; CHECK-NEXT: adds r2, #1 -; CHECK-NEXT: cmp r3, #0 +; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: beq .LBB4_1 ; CHECK-NEXT: @ %bb.2: @ %exit -; CHECK-NEXT: subs r0, r2, #1 -; CHECK-NEXT: str r0, [r1] -; CHECK-NEXT: bx lr +; CHECK-NEXT: str r3, [r1] +; CHECK-NEXT: pop {r4, pc} entry: br label %loop Index: llvm/test/CodeGen/X86/break-false-dep.ll =================================================================== --- llvm/test/CodeGen/X86/break-false-dep.ll +++ llvm/test/CodeGen/X86/break-false-dep.ll @@ -1287,33 +1287,33 @@ ; SSE-LINUX-NEXT: #APP ; SSE-LINUX-NEXT: #NO_APP ; SSE-LINUX-NEXT: movl $1, %r8d -; SSE-LINUX-NEXT: xorl %ecx, %ecx +; SSE-LINUX-NEXT: xorl %r9d, %r9d ; SSE-LINUX-NEXT: .p2align 4, 0x90 ; SSE-LINUX-NEXT: .LBB13_1: # %inner_loop ; SSE-LINUX-NEXT: # =>This Inner Loop Header: Depth=1 -; SSE-LINUX-NEXT: movq %rcx, %rax -; SSE-LINUX-NEXT: shrq $6, %rcx -; SSE-LINUX-NEXT: movq (%rsi,%rcx,8), %rcx -; SSE-LINUX-NEXT: btq %rax, %rcx -; SSE-LINUX-NEXT: leaq 1(%rax), %rcx +; SSE-LINUX-NEXT: movq %r9, %rcx +; SSE-LINUX-NEXT: movq %r9, %rax +; SSE-LINUX-NEXT: shrq $6, %rax +; SSE-LINUX-NEXT: movq (%rsi,%rax,8), %rax +; SSE-LINUX-NEXT: incq %r9 +; SSE-LINUX-NEXT: btq %rcx, %rax ; SSE-LINUX-NEXT: jae .LBB13_1 ; SSE-LINUX-NEXT: # %bb.2: # %loop_end ; SSE-LINUX-NEXT: # in Loop: Header=BB13_1 Depth=1 -; SSE-LINUX-NEXT: leaq 1(%r8), %r9 +; SSE-LINUX-NEXT: leaq 1(%r8), %rax ; SSE-LINUX-NEXT: xorps %xmm4, %xmm4 -; SSE-LINUX-NEXT: cvtsi2sd %r9, %xmm4 +; SSE-LINUX-NEXT: cvtsi2sd %rax, %xmm4 ; SSE-LINUX-NEXT: movapd %xmm0, %xmm5 ; SSE-LINUX-NEXT: subsd %xmm4, %xmm5 ; SSE-LINUX-NEXT: mulsd %xmm1, %xmm5 -; SSE-LINUX-NEXT: leaq -1(%rcx), %rax ; SSE-LINUX-NEXT: xorps %xmm4, %xmm4 -; SSE-LINUX-NEXT: cvtsi2sd %rax, %xmm4 +; SSE-LINUX-NEXT: cvtsi2sd %rcx, %xmm4 ; SSE-LINUX-NEXT: mulsd %xmm2, %xmm4 ; SSE-LINUX-NEXT: addsd %xmm5, %xmm4 ; SSE-LINUX-NEXT: divsd %xmm3, %xmm4 ; SSE-LINUX-NEXT: movsd %xmm4, -8(%rdi,%r8,8) -; SSE-LINUX-NEXT: movq %r9, %r8 -; SSE-LINUX-NEXT: cmpq %r9, %rdx +; SSE-LINUX-NEXT: movq %rax, %r8 +; SSE-LINUX-NEXT: cmpq %rax, %rdx ; SSE-LINUX-NEXT: jge .LBB13_1 ; SSE-LINUX-NEXT: # %bb.3: # %loopdone ; SSE-LINUX-NEXT: retq @@ -1359,34 +1359,33 @@ ; SSE-WIN-NEXT: #APP ; SSE-WIN-NEXT: #NO_APP ; SSE-WIN-NEXT: movl $1, %r9d -; SSE-WIN-NEXT: xorl %r11d, %r11d +; SSE-WIN-NEXT: xorl %r10d, %r10d ; SSE-WIN-NEXT: .p2align 4, 0x90 ; SSE-WIN-NEXT: .LBB13_1: # %inner_loop ; SSE-WIN-NEXT: # =>This Inner Loop Header: Depth=1 -; SSE-WIN-NEXT: movq %r11, %r10 -; SSE-WIN-NEXT: movq %r11, %rax +; SSE-WIN-NEXT: movq %r10, %r11 +; SSE-WIN-NEXT: movq %r10, %rax ; SSE-WIN-NEXT: shrq $6, %rax ; SSE-WIN-NEXT: movq (%rdx,%rax,8), %rax +; SSE-WIN-NEXT: incq %r10 ; SSE-WIN-NEXT: btq %r11, %rax -; SSE-WIN-NEXT: leaq 1(%r11), %r11 ; SSE-WIN-NEXT: jae .LBB13_1 ; SSE-WIN-NEXT: # %bb.2: # %loop_end ; SSE-WIN-NEXT: # in Loop: Header=BB13_1 Depth=1 -; SSE-WIN-NEXT: leaq 1(%r9), %r10 +; SSE-WIN-NEXT: leaq 1(%r9), %rax ; SSE-WIN-NEXT: xorps %xmm4, %xmm4 -; SSE-WIN-NEXT: cvtsi2sd %r10, %xmm4 +; SSE-WIN-NEXT: cvtsi2sd %rax, %xmm4 ; SSE-WIN-NEXT: movapd %xmm2, %xmm5 ; SSE-WIN-NEXT: subsd %xmm4, %xmm5 ; SSE-WIN-NEXT: mulsd %xmm3, %xmm5 -; SSE-WIN-NEXT: leaq -1(%r11), %rax ; SSE-WIN-NEXT: xorps %xmm4, %xmm4 -; SSE-WIN-NEXT: cvtsi2sd %rax, %xmm4 +; SSE-WIN-NEXT: cvtsi2sd %r11, %xmm4 ; SSE-WIN-NEXT: mulsd %xmm1, %xmm4 ; SSE-WIN-NEXT: addsd %xmm5, %xmm4 ; SSE-WIN-NEXT: divsd %xmm0, %xmm4 ; SSE-WIN-NEXT: movsd %xmm4, -8(%rcx,%r9,8) -; SSE-WIN-NEXT: movq %r10, %r9 -; SSE-WIN-NEXT: cmpq %r10, %r8 +; SSE-WIN-NEXT: movq %rax, %r9 +; SSE-WIN-NEXT: cmpq %rax, %r8 ; SSE-WIN-NEXT: jge .LBB13_1 ; SSE-WIN-NEXT: # %bb.3: # %loopdone ; SSE-WIN-NEXT: movaps (%rsp), %xmm7 # 16-byte Reload @@ -1443,31 +1442,30 @@ ; AVX1-NEXT: #APP ; AVX1-NEXT: #NO_APP ; AVX1-NEXT: movl $1, %r9d -; AVX1-NEXT: xorl %r11d, %r11d +; AVX1-NEXT: xorl %r10d, %r10d ; AVX1-NEXT: .p2align 4, 0x90 ; AVX1-NEXT: .LBB13_1: # %inner_loop ; AVX1-NEXT: # =>This Inner Loop Header: Depth=1 -; AVX1-NEXT: movq %r11, %r10 -; AVX1-NEXT: movq %r11, %rax +; AVX1-NEXT: movq %r10, %r11 +; AVX1-NEXT: movq %r10, %rax ; AVX1-NEXT: shrq $6, %rax ; AVX1-NEXT: movq (%rdx,%rax,8), %rax +; AVX1-NEXT: incq %r10 ; AVX1-NEXT: btq %r11, %rax -; AVX1-NEXT: leaq 1(%r11), %r11 ; AVX1-NEXT: jae .LBB13_1 ; AVX1-NEXT: # %bb.2: # %loop_end ; AVX1-NEXT: # in Loop: Header=BB13_1 Depth=1 -; AVX1-NEXT: leaq 1(%r9), %r10 -; AVX1-NEXT: vcvtsi2sd %r10, %xmm6, %xmm4 +; AVX1-NEXT: leaq 1(%r9), %rax +; AVX1-NEXT: vcvtsi2sd %rax, %xmm6, %xmm4 ; AVX1-NEXT: vsubsd %xmm4, %xmm2, %xmm4 ; AVX1-NEXT: vmulsd %xmm3, %xmm4, %xmm4 -; AVX1-NEXT: leaq -1(%r11), %rax -; AVX1-NEXT: vcvtsi2sd %rax, %xmm6, %xmm5 +; AVX1-NEXT: vcvtsi2sd %r11, %xmm6, %xmm5 ; AVX1-NEXT: vmulsd %xmm1, %xmm5, %xmm5 ; AVX1-NEXT: vaddsd %xmm5, %xmm4, %xmm4 ; AVX1-NEXT: vdivsd %xmm0, %xmm4, %xmm4 ; AVX1-NEXT: vmovsd %xmm4, -8(%rcx,%r9,8) -; AVX1-NEXT: movq %r10, %r9 -; AVX1-NEXT: cmpq %r10, %r8 +; AVX1-NEXT: movq %rax, %r9 +; AVX1-NEXT: cmpq %rax, %r8 ; AVX1-NEXT: jge .LBB13_1 ; AVX1-NEXT: # %bb.3: # %loopdone ; AVX1-NEXT: vmovaps (%rsp), %xmm7 # 16-byte Reload @@ -1524,31 +1522,30 @@ ; AVX512VL-NEXT: #APP ; AVX512VL-NEXT: #NO_APP ; AVX512VL-NEXT: movl $1, %r9d -; AVX512VL-NEXT: xorl %r11d, %r11d +; AVX512VL-NEXT: xorl %r10d, %r10d ; AVX512VL-NEXT: .p2align 4, 0x90 ; AVX512VL-NEXT: .LBB13_1: # %inner_loop ; AVX512VL-NEXT: # =>This Inner Loop Header: Depth=1 -; AVX512VL-NEXT: movq %r11, %r10 -; AVX512VL-NEXT: movq %r11, %rax +; AVX512VL-NEXT: movq %r10, %r11 +; AVX512VL-NEXT: movq %r10, %rax ; AVX512VL-NEXT: shrq $6, %rax ; AVX512VL-NEXT: movq (%rdx,%rax,8), %rax +; AVX512VL-NEXT: incq %r10 ; AVX512VL-NEXT: btq %r11, %rax -; AVX512VL-NEXT: leaq 1(%r11), %r11 ; AVX512VL-NEXT: jae .LBB13_1 ; AVX512VL-NEXT: # %bb.2: # %loop_end ; AVX512VL-NEXT: # in Loop: Header=BB13_1 Depth=1 -; AVX512VL-NEXT: leaq 1(%r9), %r10 -; AVX512VL-NEXT: vcvtsi2sd %r10, %xmm6, %xmm4 +; AVX512VL-NEXT: leaq 1(%r9), %rax +; AVX512VL-NEXT: vcvtsi2sd %rax, %xmm6, %xmm4 ; AVX512VL-NEXT: vsubsd %xmm4, %xmm2, %xmm4 ; AVX512VL-NEXT: vmulsd %xmm3, %xmm4, %xmm4 -; AVX512VL-NEXT: leaq -1(%r11), %rax -; AVX512VL-NEXT: vcvtsi2sd %rax, %xmm6, %xmm5 +; AVX512VL-NEXT: vcvtsi2sd %r11, %xmm6, %xmm5 ; AVX512VL-NEXT: vmulsd %xmm1, %xmm5, %xmm5 ; AVX512VL-NEXT: vaddsd %xmm5, %xmm4, %xmm4 ; AVX512VL-NEXT: vdivsd %xmm0, %xmm4, %xmm4 ; AVX512VL-NEXT: vmovsd %xmm4, -8(%rcx,%r9,8) -; AVX512VL-NEXT: movq %r10, %r9 -; AVX512VL-NEXT: cmpq %r10, %r8 +; AVX512VL-NEXT: movq %rax, %r9 +; AVX512VL-NEXT: cmpq %rax, %r8 ; AVX512VL-NEXT: jge .LBB13_1 ; AVX512VL-NEXT: # %bb.3: # %loopdone ; AVX512VL-NEXT: vmovaps (%rsp), %xmm7 # 16-byte Reload Index: llvm/test/Transforms/LoopDeletion/pr53969.ll =================================================================== --- llvm/test/Transforms/LoopDeletion/pr53969.ll +++ llvm/test/Transforms/LoopDeletion/pr53969.ll @@ -26,13 +26,12 @@ ; CHECK-NEXT: [[TMP2_LCSSA12:%.*]] = phi i32 [ 11, [[BB34]] ] ; CHECK-NEXT: br label [[BB33_LOOPEXIT:%.*]] ; CHECK: bb12: -; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[TMP40:%.*]], 0 ; CHECK-NEXT: br label [[BB14:%.*]] ; CHECK: bb14: ; CHECK-NEXT: br i1 true, label [[BB32:%.*]], label [[BB22:%.*]] ; CHECK: bb22: -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 4 to i32 -; CHECK-NEXT: [[TMP23:%.*]] = or i32 [[TMP1]], undef +; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 4 to i32 +; CHECK-NEXT: [[TMP23:%.*]] = or i32 [[TMP0]], undef ; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP23]], undef ; CHECK-NEXT: br i1 false, label [[BB42:%.*]], label [[BB25:%.*]] ; CHECK: bb25: @@ -55,11 +54,11 @@ ; CHECK-NEXT: [[TMP36:%.*]] = xor i32 0, [[TMP8]] ; CHECK-NEXT: [[TMP38:%.*]] = add i32 [[TMP36]], undef ; CHECK-NEXT: [[TMP39:%.*]] = add i32 [[TMP38]], undef -; CHECK-NEXT: [[TMP40]] = sext i32 [[TMP39]] to i64 +; CHECK-NEXT: [[TMP40:%.*]] = sext i32 [[TMP39]] to i64 ; CHECK-NEXT: br i1 false, label [[BB11]], label [[BB12:%.*]] ; CHECK: bb42: ; CHECK-NEXT: [[TMP24_LCSSA:%.*]] = phi i32 [ [[TMP24]], [[BB22]] ] -; CHECK-NEXT: [[TMP18_LCSSA4:%.*]] = phi i64 [ [[TMP0]], [[BB22]] ] +; CHECK-NEXT: [[TMP18_LCSSA4:%.*]] = phi i64 [ [[TMP40]], [[BB22]] ] ; CHECK-NEXT: store atomic i64 [[TMP18_LCSSA4]], i64 addrspace(1)* undef unordered, align 8 ; CHECK-NEXT: call void @use(i32 [[TMP24_LCSSA]]) ; CHECK-NEXT: ret void Index: llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll =================================================================== --- llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll +++ llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll @@ -20,17 +20,16 @@ ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_1: # %bb1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: movq %rbx, %rcx ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB0_4 +; CHECK-NEXT: je .LBB0_3 ; CHECK-NEXT: # %bb.2: # %bb4 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: incq %rbx +; CHECK-NEXT: leaq 1(%rcx), %rbx ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.3: # %bb8split -; CHECK-NEXT: decq %rbx -; CHECK-NEXT: .LBB0_4: # %bb8 -; CHECK-NEXT: movq %rbx, %rax +; CHECK-NEXT: .LBB0_3: # %bb8 +; CHECK-NEXT: movq %rcx, %rax ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: retq bb: Index: llvm/test/Transforms/LoopStrengthReduce/X86/pr46943.ll =================================================================== --- llvm/test/Transforms/LoopStrengthReduce/X86/pr46943.ll +++ llvm/test/Transforms/LoopStrengthReduce/X86/pr46943.ll @@ -19,8 +19,7 @@ ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[IV_NEXT]], 0 ; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: -; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[IV_NEXT]], -1 -; CHECK-NEXT: ret i8 [[TMP0]] +; CHECK-NEXT: ret i8 [[IV]] ; entry: br label %loop @@ -49,8 +48,7 @@ ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[IV_NEXT]], 127 ; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: -; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[IV_NEXT]], 1 -; CHECK-NEXT: ret i8 [[TMP0]] +; CHECK-NEXT: ret i8 [[IV]] ; entry: br label %loop @@ -79,8 +77,7 @@ ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[IV_NEXT]], -1 ; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]] ; CHECK: exit: -; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[IV_NEXT]], -1 -; CHECK-NEXT: ret i8 [[TMP0]] +; CHECK-NEXT: ret i8 [[IV]] ; entry: br label %loop Index: llvm/test/Transforms/LoopStrengthReduce/depth-limit-overrun.ll =================================================================== --- llvm/test/Transforms/LoopStrengthReduce/depth-limit-overrun.ll +++ llvm/test/Transforms/LoopStrengthReduce/depth-limit-overrun.ll @@ -22,17 +22,16 @@ ; DEFAULT: preheader: ; DEFAULT-NEXT: [[I15:%.*]] = shl i32 [[B]], 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = mul i32 [[PHI2]], -1 -; DEFAULT-NEXT: [[TMP2:%.*]] = mul i32 [[TMP1]], -1 -; DEFAULT-NEXT: [[TMP3:%.*]] = sub i32 [[PHI4]], [[TMP2]] -; DEFAULT-NEXT: [[TMP4:%.*]] = add i32 [[B]], [[PHI4]] -; DEFAULT-NEXT: [[TMP5:%.*]] = sub i32 [[TMP4]], [[TMP2]] -; DEFAULT-NEXT: [[TMP6:%.*]] = sub i32 14, [[TMP5]] -; DEFAULT-NEXT: [[TMP7:%.*]] = add i32 [[TMP0]], [[PHI2]] +; DEFAULT-NEXT: [[TMP2:%.*]] = sub i32 [[PHI4]], [[PHI2]] +; DEFAULT-NEXT: [[TMP3:%.*]] = add i32 [[B]], [[PHI4]] +; DEFAULT-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], [[PHI2]] +; DEFAULT-NEXT: [[TMP5:%.*]] = sub i32 14, [[TMP4]] +; DEFAULT-NEXT: [[TMP6:%.*]] = add i32 [[TMP0]], [[PHI2]] ; DEFAULT-NEXT: br label [[INNER_LOOP:%.*]] ; DEFAULT: inner_loop: -; DEFAULT-NEXT: [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[INNER_LOOP]] ], [ [[TMP6]], [[PREHEADER]] ] -; DEFAULT-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[INNER_LOOP]] ], [ [[TMP5]], [[PREHEADER]] ] -; DEFAULT-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[INNER_LOOP]] ], [ [[TMP3]], [[PREHEADER]] ] +; DEFAULT-NEXT: [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[INNER_LOOP]] ], [ [[TMP5]], [[PREHEADER]] ] +; DEFAULT-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[INNER_LOOP]] ], [ [[TMP4]], [[PREHEADER]] ] +; DEFAULT-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[INNER_LOOP]] ], [ [[TMP2]], [[PREHEADER]] ] ; DEFAULT-NEXT: [[PHI5:%.*]] = phi i32 [ [[PHI3]], [[PREHEADER]] ], [ [[I30:%.*]], [[INNER_LOOP]] ] ; DEFAULT-NEXT: [[PHI6:%.*]] = phi i32 [ [[PHI2]], [[PREHEADER]] ], [ [[I33:%.*]], [[INNER_LOOP]] ] ; DEFAULT-NEXT: [[ITER:%.*]] = phi i32 [ [[C]], [[PREHEADER]] ], [ [[ITER_SUB:%.*]], [[INNER_LOOP]] ] @@ -40,20 +39,20 @@ ; DEFAULT-NEXT: [[I18:%.*]] = sub i32 14, [[PHI5]] ; DEFAULT-NEXT: [[I19:%.*]] = mul i32 [[I18]], [[C]] ; DEFAULT-NEXT: [[FACTOR_PROL:%.*]] = shl i32 [[PHI5]], 1 -; DEFAULT-NEXT: [[TMP8:%.*]] = add i32 [[LSR_IV1]], [[I19]] -; DEFAULT-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], [[FACTOR_PROL]] -; DEFAULT-NEXT: [[TMP10:%.*]] = shl i32 [[TMP9]], 1 -; DEFAULT-NEXT: [[TMP11:%.*]] = add i32 [[LSR_IV]], [[TMP10]] -; DEFAULT-NEXT: [[TMP12:%.*]] = sub i32 [[LSR_IV3]], [[I19]] -; DEFAULT-NEXT: [[TMP13:%.*]] = sub i32 [[TMP12]], [[FACTOR_PROL]] -; DEFAULT-NEXT: [[TMP14:%.*]] = mul i32 [[C]], [[TMP13]] -; DEFAULT-NEXT: [[TMP15:%.*]] = add i32 [[LSR_IV1]], [[I19]] -; DEFAULT-NEXT: [[TMP16:%.*]] = add i32 [[TMP15]], [[FACTOR_PROL]] -; DEFAULT-NEXT: [[TMP17:%.*]] = shl i32 [[TMP16]], 1 -; DEFAULT-NEXT: [[TMP18:%.*]] = add i32 [[TMP14]], [[TMP17]] -; DEFAULT-NEXT: [[TMP19:%.*]] = add i32 [[LSR_IV]], [[TMP18]] -; DEFAULT-NEXT: [[I29:%.*]] = mul i32 [[TMP11]], [[C]] -; DEFAULT-NEXT: [[FACTOR_2_PROL:%.*]] = shl i32 [[TMP19]], 1 +; DEFAULT-NEXT: [[TMP7:%.*]] = add i32 [[LSR_IV1]], [[I19]] +; DEFAULT-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[FACTOR_PROL]] +; DEFAULT-NEXT: [[TMP9:%.*]] = shl i32 [[TMP8]], 1 +; DEFAULT-NEXT: [[TMP10:%.*]] = add i32 [[LSR_IV]], [[TMP9]] +; DEFAULT-NEXT: [[TMP11:%.*]] = sub i32 [[LSR_IV3]], [[I19]] +; DEFAULT-NEXT: [[TMP12:%.*]] = sub i32 [[TMP11]], [[FACTOR_PROL]] +; DEFAULT-NEXT: [[TMP13:%.*]] = mul i32 [[C]], [[TMP12]] +; DEFAULT-NEXT: [[TMP14:%.*]] = add i32 [[LSR_IV1]], [[I19]] +; DEFAULT-NEXT: [[TMP15:%.*]] = add i32 [[TMP14]], [[FACTOR_PROL]] +; DEFAULT-NEXT: [[TMP16:%.*]] = shl i32 [[TMP15]], 1 +; DEFAULT-NEXT: [[TMP17:%.*]] = add i32 [[TMP13]], [[TMP16]] +; DEFAULT-NEXT: [[TMP18:%.*]] = add i32 [[LSR_IV]], [[TMP17]] +; DEFAULT-NEXT: [[I29:%.*]] = mul i32 [[TMP10]], [[C]] +; DEFAULT-NEXT: [[FACTOR_2_PROL:%.*]] = shl i32 [[TMP18]], 1 ; DEFAULT-NEXT: [[I30]] = add i32 [[I17]], [[FACTOR_2_PROL]] ; DEFAULT-NEXT: [[I33]] = add i32 [[PHI6]], -3 ; DEFAULT-NEXT: [[ITER_SUB]] = add i32 [[ITER]], -1 @@ -65,7 +64,7 @@ ; DEFAULT: outer_tail.loopexit: ; DEFAULT-NEXT: br label [[OUTER_TAIL]] ; DEFAULT: outer_tail: -; DEFAULT-NEXT: [[PHI7:%.*]] = phi i32 [ [[PHI2]], [[GUARD]] ], [ [[TMP7]], [[OUTER_TAIL_LOOPEXIT]] ] +; DEFAULT-NEXT: [[PHI7:%.*]] = phi i32 [ [[PHI2]], [[GUARD]] ], [ [[TMP6]], [[OUTER_TAIL_LOOPEXIT]] ] ; DEFAULT-NEXT: [[I35]] = sub i32 [[A]], [[PHI7]] ; DEFAULT-NEXT: [[CMP:%.*]] = icmp sgt i32 [[I35]], 9876 ; DEFAULT-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[OUTER_LOOP]] @@ -86,16 +85,15 @@ ; LIMIT: preheader: ; LIMIT-NEXT: [[I15:%.*]] = shl i32 [[B]], 1 ; LIMIT-NEXT: [[TMP0:%.*]] = mul i32 [[PHI2]], -1 -; LIMIT-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], -1 -; LIMIT-NEXT: [[TMP2:%.*]] = sub i32 [[PHI4]], [[TMP1]] -; LIMIT-NEXT: [[TMP3:%.*]] = add i32 [[B]], [[PHI4]] -; LIMIT-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], [[TMP1]] -; LIMIT-NEXT: [[TMP5:%.*]] = sub i32 14, [[TMP4]] +; LIMIT-NEXT: [[TMP1:%.*]] = sub i32 [[PHI4]], [[PHI2]] +; LIMIT-NEXT: [[TMP2:%.*]] = add i32 [[B]], [[PHI4]] +; LIMIT-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[PHI2]] +; LIMIT-NEXT: [[TMP4:%.*]] = sub i32 14, [[TMP3]] ; LIMIT-NEXT: br label [[INNER_LOOP:%.*]] ; LIMIT: inner_loop: -; LIMIT-NEXT: [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[INNER_LOOP]] ], [ [[TMP5]], [[PREHEADER]] ] -; LIMIT-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[INNER_LOOP]] ], [ [[TMP4]], [[PREHEADER]] ] -; LIMIT-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[INNER_LOOP]] ], [ [[TMP2]], [[PREHEADER]] ] +; LIMIT-NEXT: [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[INNER_LOOP]] ], [ [[TMP4]], [[PREHEADER]] ] +; LIMIT-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[INNER_LOOP]] ], [ [[TMP3]], [[PREHEADER]] ] +; LIMIT-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[INNER_LOOP]] ], [ [[TMP1]], [[PREHEADER]] ] ; LIMIT-NEXT: [[PHI5:%.*]] = phi i32 [ [[PHI3]], [[PREHEADER]] ], [ [[I30:%.*]], [[INNER_LOOP]] ] ; LIMIT-NEXT: [[PHI6:%.*]] = phi i32 [ [[PHI2]], [[PREHEADER]] ], [ [[I33:%.*]], [[INNER_LOOP]] ] ; LIMIT-NEXT: [[ITER:%.*]] = phi i32 [ [[C]], [[PREHEADER]] ], [ [[ITER_SUB:%.*]], [[INNER_LOOP]] ] @@ -103,20 +101,20 @@ ; LIMIT-NEXT: [[I18:%.*]] = sub i32 14, [[PHI5]] ; LIMIT-NEXT: [[I19:%.*]] = mul i32 [[I18]], [[C]] ; LIMIT-NEXT: [[FACTOR_PROL:%.*]] = shl i32 [[PHI5]], 1 -; LIMIT-NEXT: [[TMP6:%.*]] = add i32 [[LSR_IV1]], [[I19]] -; LIMIT-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[FACTOR_PROL]] -; LIMIT-NEXT: [[TMP8:%.*]] = shl i32 [[TMP7]], 1 -; LIMIT-NEXT: [[TMP9:%.*]] = add i32 [[LSR_IV]], [[TMP8]] -; LIMIT-NEXT: [[TMP10:%.*]] = sub i32 [[LSR_IV3]], [[I19]] -; LIMIT-NEXT: [[TMP11:%.*]] = sub i32 [[TMP10]], [[FACTOR_PROL]] -; LIMIT-NEXT: [[TMP12:%.*]] = mul i32 [[C]], [[TMP11]] -; LIMIT-NEXT: [[TMP13:%.*]] = add i32 [[LSR_IV1]], [[I19]] -; LIMIT-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[FACTOR_PROL]] -; LIMIT-NEXT: [[TMP15:%.*]] = shl i32 [[TMP14]], 1 -; LIMIT-NEXT: [[TMP16:%.*]] = add i32 [[TMP12]], [[TMP15]] -; LIMIT-NEXT: [[TMP17:%.*]] = add i32 [[LSR_IV]], [[TMP16]] -; LIMIT-NEXT: [[I29:%.*]] = mul i32 [[TMP9]], [[C]] -; LIMIT-NEXT: [[FACTOR_2_PROL:%.*]] = shl i32 [[TMP17]], 1 +; LIMIT-NEXT: [[TMP5:%.*]] = add i32 [[LSR_IV1]], [[I19]] +; LIMIT-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], [[FACTOR_PROL]] +; LIMIT-NEXT: [[TMP7:%.*]] = shl i32 [[TMP6]], 1 +; LIMIT-NEXT: [[TMP8:%.*]] = add i32 [[LSR_IV]], [[TMP7]] +; LIMIT-NEXT: [[TMP9:%.*]] = sub i32 [[LSR_IV3]], [[I19]] +; LIMIT-NEXT: [[TMP10:%.*]] = sub i32 [[TMP9]], [[FACTOR_PROL]] +; LIMIT-NEXT: [[TMP11:%.*]] = mul i32 [[C]], [[TMP10]] +; LIMIT-NEXT: [[TMP12:%.*]] = add i32 [[LSR_IV1]], [[I19]] +; LIMIT-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], [[FACTOR_PROL]] +; LIMIT-NEXT: [[TMP14:%.*]] = shl i32 [[TMP13]], 1 +; LIMIT-NEXT: [[TMP15:%.*]] = add i32 [[TMP11]], [[TMP14]] +; LIMIT-NEXT: [[TMP16:%.*]] = add i32 [[LSR_IV]], [[TMP15]] +; LIMIT-NEXT: [[I29:%.*]] = mul i32 [[TMP8]], [[C]] +; LIMIT-NEXT: [[FACTOR_2_PROL:%.*]] = shl i32 [[TMP16]], 1 ; LIMIT-NEXT: [[I30]] = add i32 [[I17]], [[FACTOR_2_PROL]] ; LIMIT-NEXT: [[I33]] = add i32 [[PHI6]], -3 ; LIMIT-NEXT: [[ITER_SUB]] = add i32 [[ITER]], -1 Index: llvm/test/Transforms/LoopStrengthReduce/wrong-hoisting-iv.ll =================================================================== --- llvm/test/Transforms/LoopStrengthReduce/wrong-hoisting-iv.ll +++ llvm/test/Transforms/LoopStrengthReduce/wrong-hoisting-iv.ll @@ -17,17 +17,15 @@ ; CHECK-NEXT: [[VAL5:%.*]] = ashr i32 undef, undef ; CHECK-NEXT: [[VAL6:%.*]] = sub i32 [[VAL4]], [[VAL5]] ; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[VAL]], 7 -; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[VAL3]], 7 +; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[VAL5]], 7 ; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP0]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[VAL5]], 7 -; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = shl i32 [[VAL6]], 3 +; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[VAL6]], 3 ; CHECK-NEXT: br label [[BB7:%.*]] ; CHECK: bb7: ; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB32:%.*]] ], [ 0, [[BB:%.*]] ] ; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BB32]] ], [ -8, [[BB]] ] ; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 8 -; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nuw nsw i32 [[LSR_IV1]], [[TMP5]] +; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nuw nsw i32 [[LSR_IV1]], [[TMP3]] ; CHECK-NEXT: [[VAL10:%.*]] = icmp ult i64 [[LSR_IV_NEXT]], 65536 ; CHECK-NEXT: br i1 [[VAL10]], label [[BB12:%.*]], label [[BB11:%.*]] ; CHECK: bb11: @@ -38,70 +36,66 @@ ; CHECK: bb15splitsplitsplitsplitsplitsplit: ; CHECK-NEXT: br label [[BB15SPLITSPLITSPLITSPLITSPLIT:%.*]] ; CHECK: bb12.bb15splitsplitsplitsplitsplit_crit_edge: -; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[VAL6]], [[LSR_IV1]] +; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[VAL6]], [[LSR_IV1]] ; CHECK-NEXT: br label [[BB15SPLITSPLITSPLITSPLITSPLIT]] ; CHECK: bb15splitsplitsplitsplitsplit: -; CHECK-NEXT: [[VAL16_PH_PH_PH_PH_PH:%.*]] = phi i32 [ [[TMP6]], [[BB12_BB15SPLITSPLITSPLITSPLITSPLIT_CRIT_EDGE]] ], [ [[VAL35:%.*]], [[BB15SPLITSPLITSPLITSPLITSPLITSPLIT:%.*]] ] +; CHECK-NEXT: [[VAL16_PH_PH_PH_PH_PH:%.*]] = phi i32 [ [[TMP4]], [[BB12_BB15SPLITSPLITSPLITSPLITSPLIT_CRIT_EDGE]] ], [ [[VAL35:%.*]], [[BB15SPLITSPLITSPLITSPLITSPLITSPLIT:%.*]] ] ; CHECK-NEXT: br label [[BB15SPLITSPLITSPLITSPLIT:%.*]] ; CHECK: bb17.bb15splitsplitsplitsplit_crit_edge: -; CHECK-NEXT: [[TMP7:%.*]] = shl i32 [[VAL]], 1 -; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[VAL1]], [[VAL2]] -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP8]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[TMP7]], [[TMP9]] -; CHECK-NEXT: [[TMP11:%.*]] = shl i32 [[VAL5]], 1 -; CHECK-NEXT: [[TMP12:%.*]] = sub i32 [[TMP10]], [[TMP11]] -; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], [[LSR_IV1]] +; CHECK-NEXT: [[TMP5:%.*]] = shl i32 [[VAL]], 1 +; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: [[TMP7:%.*]] = shl i32 [[TMP6]], 1 +; CHECK-NEXT: [[TMP8:%.*]] = sub i32 [[TMP5]], [[TMP7]] +; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[VAL5]], 1 +; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[TMP8]], [[TMP9]] +; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[LSR_IV1]] ; CHECK-NEXT: br label [[BB15SPLITSPLITSPLITSPLIT]] ; CHECK: bb15splitsplitsplitsplit: -; CHECK-NEXT: [[VAL16_PH_PH_PH_PH:%.*]] = phi i32 [ [[TMP13]], [[BB17_BB15SPLITSPLITSPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH_PH_PH]], [[BB15SPLITSPLITSPLITSPLITSPLIT]] ] +; CHECK-NEXT: [[VAL16_PH_PH_PH_PH:%.*]] = phi i32 [ [[TMP11]], [[BB17_BB15SPLITSPLITSPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH_PH_PH]], [[BB15SPLITSPLITSPLITSPLITSPLIT]] ] ; CHECK-NEXT: br label [[BB15SPLITSPLITSPLIT:%.*]] ; CHECK: bb20.bb15splitsplitsplit_crit_edge: -; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[VAL]], 3 -; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[VAL1]], [[VAL2]] -; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], 3 -; CHECK-NEXT: [[TMP17:%.*]] = sub i32 [[TMP14]], [[TMP16]] -; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[VAL5]], 3 -; CHECK-NEXT: [[TMP19:%.*]] = sub i32 [[TMP17]], [[TMP18]] -; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP19]], [[LSR_IV1]] +; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[VAL]], 3 +; CHECK-NEXT: [[TMP13:%.*]] = mul i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[VAL5]], 3 +; CHECK-NEXT: [[TMP15:%.*]] = sub i32 [[TMP12]], [[TMP14]] +; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP15]], [[LSR_IV1]] ; CHECK-NEXT: br label [[BB15SPLITSPLITSPLIT]] ; CHECK: bb15splitsplitsplit: -; CHECK-NEXT: [[VAL16_PH_PH_PH:%.*]] = phi i32 [ [[TMP20]], [[BB20_BB15SPLITSPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH_PH]], [[BB15SPLITSPLITSPLITSPLIT]] ] +; CHECK-NEXT: [[VAL16_PH_PH_PH:%.*]] = phi i32 [ [[TMP16]], [[BB20_BB15SPLITSPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH_PH]], [[BB15SPLITSPLITSPLITSPLIT]] ] ; CHECK-NEXT: br label [[BB15SPLITSPLIT:%.*]] ; CHECK: bb23.bb15splitsplit_crit_edge: -; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[VAL]], 2 -; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[VAL1]], [[VAL2]] -; CHECK-NEXT: [[TMP23:%.*]] = shl i32 [[TMP22]], 2 -; CHECK-NEXT: [[TMP24:%.*]] = sub i32 [[TMP21]], [[TMP23]] -; CHECK-NEXT: [[TMP25:%.*]] = shl i32 [[VAL5]], 2 -; CHECK-NEXT: [[TMP26:%.*]] = sub i32 [[TMP24]], [[TMP25]] -; CHECK-NEXT: [[TMP27:%.*]] = add i32 [[TMP26]], [[LSR_IV1]] +; CHECK-NEXT: [[TMP17:%.*]] = shl i32 [[VAL]], 2 +; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: [[TMP19:%.*]] = shl i32 [[TMP18]], 2 +; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[TMP17]], [[TMP19]] +; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[VAL5]], 2 +; CHECK-NEXT: [[TMP22:%.*]] = sub i32 [[TMP20]], [[TMP21]] +; CHECK-NEXT: [[TMP23:%.*]] = add i32 [[TMP22]], [[LSR_IV1]] ; CHECK-NEXT: br label [[BB15SPLITSPLIT]] ; CHECK: bb15splitsplit: -; CHECK-NEXT: [[VAL16_PH_PH:%.*]] = phi i32 [ [[TMP27]], [[BB23_BB15SPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH]], [[BB15SPLITSPLITSPLIT]] ] +; CHECK-NEXT: [[VAL16_PH_PH:%.*]] = phi i32 [ [[TMP23]], [[BB23_BB15SPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH]], [[BB15SPLITSPLITSPLIT]] ] ; CHECK-NEXT: br label [[BB15SPLIT:%.*]] ; CHECK: bb26.bb15split_crit_edge: -; CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[VAL]], 5 -; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[VAL1]], [[VAL2]] -; CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[TMP29]], 5 -; CHECK-NEXT: [[TMP31:%.*]] = sub i32 [[TMP28]], [[TMP30]] -; CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[VAL5]], 5 -; CHECK-NEXT: [[TMP33:%.*]] = sub i32 [[TMP31]], [[TMP32]] -; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[TMP33]], [[LSR_IV1]] +; CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[VAL]], 5 +; CHECK-NEXT: [[TMP25:%.*]] = mul i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: [[TMP26:%.*]] = mul i32 [[VAL5]], 5 +; CHECK-NEXT: [[TMP27:%.*]] = sub i32 [[TMP24]], [[TMP26]] +; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[TMP27]], [[LSR_IV1]] ; CHECK-NEXT: br label [[BB15SPLIT]] ; CHECK: bb15split: -; CHECK-NEXT: [[VAL16_PH:%.*]] = phi i32 [ [[TMP34]], [[BB26_BB15SPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH]], [[BB15SPLITSPLIT]] ] +; CHECK-NEXT: [[VAL16_PH:%.*]] = phi i32 [ [[TMP28]], [[BB26_BB15SPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH]], [[BB15SPLITSPLIT]] ] ; CHECK-NEXT: br label [[BB15:%.*]] ; CHECK: bb29.bb15_crit_edge: -; CHECK-NEXT: [[TMP35:%.*]] = mul i32 [[VAL]], 6 -; CHECK-NEXT: [[TMP36:%.*]] = mul i32 [[VAL1]], [[VAL2]] -; CHECK-NEXT: [[TMP37:%.*]] = mul i32 [[TMP36]], 6 -; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP35]], [[TMP37]] -; CHECK-NEXT: [[TMP39:%.*]] = mul i32 [[VAL5]], 6 -; CHECK-NEXT: [[TMP40:%.*]] = sub i32 [[TMP38]], [[TMP39]] -; CHECK-NEXT: [[TMP41:%.*]] = add i32 [[TMP40]], [[LSR_IV1]] +; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[VAL]], 6 +; CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[VAL1]], [[VAL2]] +; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], 6 +; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP29]], [[TMP31]] +; CHECK-NEXT: [[TMP33:%.*]] = mul i32 [[VAL5]], 6 +; CHECK-NEXT: [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP33]] +; CHECK-NEXT: [[TMP35:%.*]] = add i32 [[TMP34]], [[LSR_IV1]] ; CHECK-NEXT: br label [[BB15]] ; CHECK: bb15: -; CHECK-NEXT: [[VAL16:%.*]] = phi i32 [ [[TMP41]], [[BB29_BB15_CRIT_EDGE:%.*]] ], [ [[VAL16_PH]], [[BB15SPLIT]] ] +; CHECK-NEXT: [[VAL16:%.*]] = phi i32 [ [[TMP35]], [[BB29_BB15_CRIT_EDGE:%.*]] ], [ [[VAL16_PH]], [[BB15SPLIT]] ] ; CHECK-NEXT: call void @widget() [ "deopt"(i32 [[VAL16]], i32 3, i32 [[VAL]]) ] ; CHECK-NEXT: unreachable ; CHECK: bb17: @@ -120,8 +114,8 @@ ; CHECK-NEXT: [[VAL31:%.*]] = icmp slt i32 undef, undef ; CHECK-NEXT: br i1 [[VAL31]], label [[BB32]], label [[BB29_BB15_CRIT_EDGE]] ; CHECK: bb32: -; CHECK-NEXT: [[TMP42:%.*]] = add i32 [[TMP4]], [[LSR_IV1]] -; CHECK-NEXT: [[VAL35]] = add i32 [[TMP42]], [[VAL6]] +; CHECK-NEXT: [[TMP36:%.*]] = add i32 [[TMP2]], [[LSR_IV1]] +; CHECK-NEXT: [[VAL35]] = add i32 [[TMP36]], [[VAL6]] ; CHECK-NEXT: br i1 false, label [[BB7]], label [[BB15SPLITSPLITSPLITSPLITSPLITSPLIT]] ; bb: