diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h --- a/clang/include/clang/Basic/LangOptions.h +++ b/clang/include/clang/Basic/LangOptions.h @@ -530,6 +530,13 @@ return ConvergentFunctions; } + /// Return true if uninitialized function arguments are allowed. + bool allowUninitializedFunctionArgs() const { + /// CUDA/HIP etc. cross-lane APIs are convergent functions + /// and accept uninitialised variables as arguments. + return ConvergentFunctions; + } + /// Return the OpenCL C or C++ version as a VersionTuple. VersionTuple getOpenCLVersionTuple() const; diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -2306,11 +2306,22 @@ getLangOpts().Sanitize.has(SanitizerKind::Memory) || getLangOpts().Sanitize.has(SanitizerKind::Return); + // Enable noundef attribute based on codegen options. + // Also skip adding the attribute for languages like HIP, CUDA etc. + // which allow uninitialized function arguments. In these languages, + // some functions have multi-threaded semantics and it is enough + // for only one or some threads to provide defined arguments. + // Depending on semantics, undef arguments in some threads + // don't produce undefined results in the function call. + bool EnableNoundefAttrs = CodeGenOpts.EnableNoundefAttrs && + (!getLangOpts().allowUninitializedFunctionArgs()); + // Determine if the return type could be partially undef - if (CodeGenOpts.EnableNoundefAttrs && HasStrictReturn) { + if (EnableNoundefAttrs && HasStrictReturn) { if (!RetTy->isVoidType() && RetAI.getKind() != ABIArgInfo::Indirect && - DetermineNoUndef(RetTy, getTypes(), DL, RetAI)) - RetAttrs.addAttribute(llvm::Attribute::NoUndef); + DetermineNoUndef(RetTy, getTypes(), DL, RetAI)) { + RetAttrs.addAttribute(llvm::Attribute::NoUndef); + } } switch (RetAI.getKind()) { @@ -2441,9 +2452,8 @@ } // Decide whether the argument we're handling could be partially undef - if (CodeGenOpts.EnableNoundefAttrs && - DetermineNoUndef(ParamType, getTypes(), DL, AI)) { - Attrs.addAttribute(llvm::Attribute::NoUndef); + if (EnableNoundefAttrs && DetermineNoUndef(ParamType, getTypes(), DL, AI)) { + Attrs.addAttribute(llvm::Attribute::NoUndef); } // 'restrict' -> 'noalias' is done in EmitFunctionProlog when we diff --git a/clang/test/CodeGen/PowerPC/ppc64le-varargs-f128.c b/clang/test/CodeGen/PowerPC/ppc64le-varargs-f128.c --- a/clang/test/CodeGen/PowerPC/ppc64le-varargs-f128.c +++ b/clang/test/CodeGen/PowerPC/ppc64le-varargs-f128.c @@ -29,7 +29,7 @@ // OMP-TARGET: %[[CUR:[0-9a-zA-Z_.]+]] = load i8*, i8** // OMP-TARGET: %[[V2:[0-9a-zA-Z_.]+]] = bitcast i8* %[[CUR]] to ppc_fp128* // OMP-TARGET: %[[V3:[0-9a-zA-Z_.]+]] = load ppc_fp128, ppc_fp128* %[[V2]], align 8 -// OMP-TARGET: call void @foo_ld(ppc_fp128 noundef %[[V3]]) +// OMP-TARGET: call void @foo_ld(ppc_fp128 %[[V3]]) // OMP-HOST-LABEL: define{{.*}} void @omp( // OMP-HOST: %[[AP1:[0-9a-zA-Z_.]+]] = bitcast i8** %[[AP:[0-9a-zA-Z_.]+]] to i8* diff --git a/clang/test/CodeGenCUDA/address-spaces.cu b/clang/test/CodeGenCUDA/address-spaces.cu --- a/clang/test/CodeGenCUDA/address-spaces.cu +++ b/clang/test/CodeGenCUDA/address-spaces.cu @@ -60,7 +60,7 @@ callee(&a); // implicit cast from parameters } // CHECK: define{{.*}} void @_Z5func1v() -// CHECK: call void @_Z6calleePf(float* noundef addrspacecast (float addrspace(3)* @_ZZ5func1vE1a to float*)) +// CHECK: call void @_Z6calleePf(float* addrspacecast (float addrspace(3)* @_ZZ5func1vE1a to float*)) __device__ void func2() { __shared__ float a[256]; diff --git a/clang/test/CodeGenCUDA/builtins-amdgcn.cu b/clang/test/CodeGenCUDA/builtins-amdgcn.cu --- a/clang/test/CodeGenCUDA/builtins-amdgcn.cu +++ b/clang/test/CodeGenCUDA/builtins-amdgcn.cu @@ -195,7 +195,7 @@ // CHECK-NEXT: [[TMP4:%.*]] = call contract float @llvm.amdgcn.ds.fmin.f32(float addrspace(3)* [[TMP2]], float [[TMP3]], i32 0, i32 0, i1 false) // CHECK-NEXT: store volatile float [[TMP4]], float* [[X_ASCAST]], align 4 // CHECK-NEXT: [[TMP5:%.*]] = load float*, float** [[SHARED_ADDR_ASCAST]], align 8 -// CHECK-NEXT: call void @_Z4funcPf(float* noundef [[TMP5]]) #[[ATTR8:[0-9]+]] +// CHECK-NEXT: call void @_Z4funcPf(float* [[TMP5]]) #[[ATTR8:[0-9]+]] // CHECK-NEXT: ret void // __global__ void test_ds_fmin_func(float src, float *__restrict shared) { diff --git a/clang/test/CodeGenCUDA/cuda-builtin-vars.cu b/clang/test/CodeGenCUDA/cuda-builtin-vars.cu --- a/clang/test/CodeGenCUDA/cuda-builtin-vars.cu +++ b/clang/test/CodeGenCUDA/cuda-builtin-vars.cu @@ -2,7 +2,7 @@ #include "__clang_cuda_builtin_vars.h" -// CHECK: define{{.*}} void @_Z6kernelPi(i32* noundef %out) +// CHECK: define{{.*}} void @_Z6kernelPi(i32* %out) __attribute__((global)) void kernel(int *out) { int i = 0; diff --git a/clang/test/CodeGenCUDA/kernel-args-alignment.cu b/clang/test/CodeGenCUDA/kernel-args-alignment.cu --- a/clang/test/CodeGenCUDA/kernel-args-alignment.cu +++ b/clang/test/CodeGenCUDA/kernel-args-alignment.cu @@ -36,5 +36,5 @@ // HOST-OLD: call i32 @cudaSetupArgument({{[^,]*}}, i64 8, i64 24) // DEVICE-LABEL: @_Z6kernelc1SPi -// DEVICE-SAME: i8{{[^,]*}}, %struct.S* noundef byval(%struct.S) align 8{{[^,]*}}, i32* +// DEVICE-SAME: i8{{[^,]*}}, %struct.S* byval(%struct.S) align 8{{[^,]*}}, i32* __global__ void kernel(char a, S s, int *b) {} diff --git a/clang/test/CodeGenCUDA/kernel-args.cu b/clang/test/CodeGenCUDA/kernel-args.cu --- a/clang/test/CodeGenCUDA/kernel-args.cu +++ b/clang/test/CodeGenCUDA/kernel-args.cu @@ -10,14 +10,14 @@ }; // AMDGCN: define{{.*}} amdgpu_kernel void @_Z6kernel1A(%struct.A addrspace(4)* byref(%struct.A) align 8 %{{.+}}) -// NVPTX: define{{.*}} void @_Z6kernel1A(%struct.A* noundef byval(%struct.A) align 8 %x) +// NVPTX: define{{.*}} void @_Z6kernel1A(%struct.A* byval(%struct.A) align 8 %x) __global__ void kernel(A x) { } class Kernel { public: // AMDGCN: define{{.*}} amdgpu_kernel void @_ZN6Kernel12memberKernelE1A(%struct.A addrspace(4)* byref(%struct.A) align 8 %{{.+}}) - // NVPTX: define{{.*}} void @_ZN6Kernel12memberKernelE1A(%struct.A* noundef byval(%struct.A) align 8 %x) + // NVPTX: define{{.*}} void @_ZN6Kernel12memberKernelE1A(%struct.A* byval(%struct.A) align 8 %x) static __global__ void memberKernel(A x){} template static __global__ void templateMemberKernel(T x) {} }; @@ -31,10 +31,10 @@ void test() { Kernel K; // AMDGCN: define{{.*}} amdgpu_kernel void @_Z14templateKernelI1AEvT_(%struct.A addrspace(4)* byref(%struct.A) align 8 %{{.+}} - // NVPTX: define{{.*}} void @_Z14templateKernelI1AEvT_(%struct.A* noundef byval(%struct.A) align 8 %x) + // NVPTX: define{{.*}} void @_Z14templateKernelI1AEvT_(%struct.A* byval(%struct.A) align 8 %x) launch((void*)templateKernel); // AMDGCN: define{{.*}} amdgpu_kernel void @_ZN6Kernel20templateMemberKernelI1AEEvT_(%struct.A addrspace(4)* byref(%struct.A) align 8 %{{.+}} - // NVPTX: define{{.*}} void @_ZN6Kernel20templateMemberKernelI1AEEvT_(%struct.A* noundef byval(%struct.A) align 8 %x) + // NVPTX: define{{.*}} void @_ZN6Kernel20templateMemberKernelI1AEEvT_(%struct.A* byval(%struct.A) align 8 %x) launch((void*)Kernel::templateMemberKernel); } diff --git a/clang/test/CodeGenCUDA/lambda.cu b/clang/test/CodeGenCUDA/lambda.cu --- a/clang/test/CodeGenCUDA/lambda.cu +++ b/clang/test/CodeGenCUDA/lambda.cu @@ -51,8 +51,8 @@ // DEV-LABEL: define{{.*}} amdgpu_kernel void @_Z1gIZ12test_resolvevEUlvE_EvT_ // DEV: call void @_ZZ12test_resolvevENKUlvE_clEv // DEV-LABEL: define internal void @_ZZ12test_resolvevENKUlvE_clEv -// DEV: call noundef i32 @_Z10overloadedIiET_v -// DEV-LABEL: define linkonce_odr noundef i32 @_Z10overloadedIiET_v +// DEV: call i32 @_Z10overloadedIiET_v +// DEV-LABEL: define linkonce_odr i32 @_Z10overloadedIiET_v // DEV: ret i32 1 __device__ int a; diff --git a/clang/test/CodeGenCUDA/redux-builtins.cu b/clang/test/CodeGenCUDA/redux-builtins.cu --- a/clang/test/CodeGenCUDA/redux-builtins.cu +++ b/clang/test/CodeGenCUDA/redux-builtins.cu @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -no-opaque-pointers "-triple" "nvptx-nvidia-cuda" "-target-feature" "+ptx70" "-target-cpu" "sm_80" -emit-llvm -fcuda-is-device -o - %s | FileCheck %s // RUN: %clang_cc1 -no-opaque-pointers "-triple" "nvptx64-nvidia-cuda" "-target-feature" "+ptx70" "-target-cpu" "sm_80" -emit-llvm -fcuda-is-device -o - %s | FileCheck %s -// CHECK: define{{.*}} void @_Z6kernelPi(i32* noundef %out) +// CHECK: define{{.*}} void @_Z6kernelPi(i32* %out) __attribute__((global)) void kernel(int *out) { int a = 1; unsigned int b = 5; diff --git a/clang/test/CodeGenCUDA/surface.cu b/clang/test/CodeGenCUDA/surface.cu --- a/clang/test/CodeGenCUDA/surface.cu +++ b/clang/test/CodeGenCUDA/surface.cu @@ -27,9 +27,9 @@ __attribute__((device)) int suld_2d_zero(surface, int, int) asm("llvm.nvvm.suld.2d.i32.zero"); -// DEVICE-LABEL: i32 @_Z3fooii(i32 noundef %x, i32 noundef %y) +// DEVICE-LABEL: i32 @_Z3fooii(i32 %x, i32 %y) // DEVICE: call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf) -// DEVICE: call noundef i32 @llvm.nvvm.suld.2d.i32.zero(i64 %{{.*}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}) +// DEVICE: call i32 @llvm.nvvm.suld.2d.i32.zero(i64 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) __attribute__((device)) int foo(int x, int y) { return suld_2d_zero(surf, x, y); } diff --git a/clang/test/CodeGenCUDA/unnamed-types.cu b/clang/test/CodeGenCUDA/unnamed-types.cu --- a/clang/test/CodeGenCUDA/unnamed-types.cu +++ b/clang/test/CodeGenCUDA/unnamed-types.cu @@ -19,16 +19,16 @@ } // DEVICE: amdgpu_kernel void @_Z2k0IZZ2f1PfENKUlS0_E_clES0_EUlfE_EvS0_T_( -// DEVICE: define internal noundef float @_ZZZ2f1PfENKUlS_E_clES_ENKUlfE_clEf( +// DEVICE: define internal float @_ZZZ2f1PfENKUlS_E_clES_ENKUlfE_clEf( template __global__ void k0(float *p, F f) { p[0] = f(p[0]) + d0(p[1]) + d1(p[2]); } // DEVICE: amdgpu_kernel void @_Z2k1IZ2f1PfEUlfE_Z2f1S0_EUlffE_Z2f1S0_EUlfE0_EvS0_T_T0_T1_( -// DEVICE: define internal noundef float @_ZZ2f1PfENKUlfE_clEf( -// DEVICE: define internal noundef float @_ZZ2f1PfENKUlffE_clEff( -// DEVICE: define internal noundef float @_ZZ2f1PfENKUlfE0_clEf( +// DEVICE: define internal float @_ZZ2f1PfENKUlfE_clEf( +// DEVICE: define internal float @_ZZ2f1PfENKUlffE_clEff( +// DEVICE: define internal float @_ZZ2f1PfENKUlfE0_clEf( template __global__ void k1(float *p, F0 f0, F1 f1, F2 f2) { p[0] = f0(p[0]) + f1(p[1], p[2]) + f2(p[3]); diff --git a/clang/test/CodeGenCUDA/usual-deallocators.cu b/clang/test/CodeGenCUDA/usual-deallocators.cu --- a/clang/test/CodeGenCUDA/usual-deallocators.cu +++ b/clang/test/CodeGenCUDA/usual-deallocators.cu @@ -83,7 +83,7 @@ // COMMON: call void @_ZN4H1D1dlEPv test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI4H1D2EvPv - // DEVICE: call void @_ZN4H1D2dlEPvj(i8* noundef {{.*}}, i32 noundef 1) + // DEVICE: call void @_ZN4H1D2dlEPvj(i8* {{.*}}, i32 1) // HOST: call void @_ZN4H1D2dlEPv(i8* noundef {{.*}}) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI4H2D1EvPv @@ -91,20 +91,24 @@ // HOST: call void @_ZN4H2D1dlEPvj(i8* noundef %3, i32 noundef 1) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI4H2D2EvPv - // COMMON: call void @_ZN4H2D2dlEPvj(i8* noundef {{.*}}, i32 noundef 1) + // DEVICE: call void @_ZN4H2D2dlEPvj(i8* {{.*}}, i32 1) + // HOST: call void @_ZN4H2D2dlEPvj(i8* noundef {{.*}}, i32 noundef 1) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI6H1D1D2EvPv - // COMMON: call void @_ZN6H1D1D2dlEPv(i8* noundef %3) + // DEVICE: call void @_ZN6H1D1D2dlEPv(i8* %3) + // HOST: call void @_ZN6H1D1D2dlEPv(i8* noundef %3) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI6H1H2D1EvPv - // COMMON: call void @_ZN6H1H2D1dlEPv(i8* {{.*}}) + // DEVICE: call void @_ZN6H1H2D1dlEPv(i8* {{.*}}) + // HOST: call void @_ZN6H1H2D1dlEPv(i8* noundef {{.*}}) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI6H1H2D2EvPv - // DEVICE: call void @_ZN6H1H2D2dlEPvj(i8* noundef {{.*}}, i32 noundef 1) + // DEVICE: call void @_ZN6H1H2D2dlEPvj(i8* {{.*}}, i32 1) // HOST: call void @_ZN6H1H2D2dlEPv(i8* noundef {{.*}}) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI8H1H2D1D2EvPv - // COMMON: call void @_ZN8H1H2D1D2dlEPv(i8* {{.*}}) + // DEVICE: call void @_ZN8H1H2D1D2dlEPv(i8* {{.*}}) + // HOST: call void @_ZN8H1H2D1D2dlEPv(i8* noundef {{.*}}) test_hd(t); } @@ -113,38 +117,41 @@ // Make sure we've picked deallocator for the correct side of compilation. -// COMMON-LABEL: define linkonce_odr void @_ZN4H1D1dlEPv(i8* noundef %0) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() -// DEVICE-LABEL: define linkonce_odr void @_ZN4H1D2dlEPvj(i8* noundef %0, i32 noundef %1) +// DEVICE-LABEL: define linkonce_odr void @_ZN4H1D2dlEPvj(i8* %0, i32 %1) // DEVICE: call void @dev_fn() // HOST-LABEL: define linkonce_odr void @_ZN4H1D2dlEPv(i8* noundef %0) // HOST: call void @host_fn() -// DEVICE-LABEL: define linkonce_odr void @_ZN4H2D1dlEPv(i8* noundef %0) +// DEVICE-LABEL: define linkonce_odr void @_ZN4H2D1dlEPv(i8* %0) // DEVICE: call void @dev_fn() // HOST-LABEL: define linkonce_odr void @_ZN4H2D1dlEPvj(i8* noundef %0, i32 noundef %1) // HOST: call void @host_fn() -// COMMON-LABEL: define linkonce_odr void @_ZN4H2D2dlEPvj(i8* noundef %0, i32 noundef %1) +// DEVICE-LABEL: define linkonce_odr void @_ZN4H2D2dlEPvj(i8* %0, i32 %1) +// HOST-LABEL: define linkonce_odr void @_ZN4H2D2dlEPvj(i8* noundef %0, i32 noundef %1) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() -// COMMON-LABEL: define linkonce_odr void @_ZN6H1D1D2dlEPv(i8* noundef %0) +// DEVICE-LABEL: define linkonce_odr void @_ZN6H1D1D2dlEPv(i8* %0) +// HOST-LABEL: define linkonce_odr void @_ZN6H1D1D2dlEPv(i8* noundef %0) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() -// COMMON-LABEL: define linkonce_odr void @_ZN6H1H2D1dlEPv(i8* noundef %0) +// DEVICE-LABEL: define linkonce_odr void @_ZN6H1H2D1dlEPv(i8* %0) +// HOST-LABEL: define linkonce_odr void @_ZN6H1H2D1dlEPv(i8* noundef %0) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() -// DEVICE-LABEL: define linkonce_odr void @_ZN6H1H2D2dlEPvj(i8* noundef %0, i32 noundef %1) +// DEVICE-LABEL: define linkonce_odr void @_ZN6H1H2D2dlEPvj(i8* %0, i32 %1) // DEVICE: call void @dev_fn() // HOST-LABEL: define linkonce_odr void @_ZN6H1H2D2dlEPv(i8* noundef %0) // HOST: call void @host_fn() -// COMMON-LABEL: define linkonce_odr void @_ZN8H1H2D1D2dlEPv(i8* noundef %0) +// DEVICE-LABEL: define linkonce_odr void @_ZN8H1H2D1D2dlEPv(i8* %0) +// HOST-LABEL: define linkonce_odr void @_ZN8H1H2D1D2dlEPv(i8* noundef %0) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() diff --git a/clang/test/CodeGenCUDA/vtbl.cu b/clang/test/CodeGenCUDA/vtbl.cu --- a/clang/test/CodeGenCUDA/vtbl.cu +++ b/clang/test/CodeGenCUDA/vtbl.cu @@ -3,7 +3,7 @@ #include "Inputs/cuda.h" -// CHECK-LABEL: define {{.*}}@_ZN1AC2Ev(%struct.A* noundef nonnull align 8 dereferenceable(8) %this) +// CHECK-LABEL: define {{.*}}@_ZN1AC2Ev(%struct.A* nonnull align 8 dereferenceable(8) %this) // CHECK: store %struct.A* %this, %struct.A** %this.addr.ascast // CHECK: %this1 = load %struct.A*, %struct.A** %this.addr.ascast // CHECK: %[[VTFIELD:.*]] = bitcast %struct.A* %this1 to i32 (...)* addrspace(1)** diff --git a/clang/test/CodeGenCUDASPIRV/kernel-argument.cu b/clang/test/CodeGenCUDASPIRV/kernel-argument.cu --- a/clang/test/CodeGenCUDASPIRV/kernel-argument.cu +++ b/clang/test/CodeGenCUDASPIRV/kernel-argument.cu @@ -1,5 +1,6 @@ // Tests CUDA kernel arguments get global address space when targetting SPIR-V. +// REQUIRES: clang-driver // RUN: %clang -Xclang -no-opaque-pointers -emit-llvm --cuda-device-only --offload=spirv32 \ // RUN: -nocudalib -nocudainc %s -o %t.bc -c 2>&1 @@ -12,6 +13,6 @@ // RUN: FileCheck %s --input-file=%t.ll // CHECK: define -// CHECK-SAME: spir_kernel void @_Z6kernelPi(i32 addrspace(1)* noundef +// CHECK-SAME: spir_kernel void @_Z6kernelPi(i32 addrspace(1)* __attribute__((global)) void kernel(int* output) { *output = 1; } diff --git a/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp b/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp --- a/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp +++ b/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp @@ -25,30 +25,30 @@ // Check literals are placed in address space 1 (CrossWorkGroup/__global). // CHECK: @.str ={{.*}} unnamed_addr addrspace(1) constant -// CHECK: define{{.*}} spir_func noundef i32 addrspace(4)* @_Z3barPi(i32 addrspace(4)* +// CHECK: define{{.*}} spir_func i32 addrspace(4)* @_Z3barPi(i32 addrspace(4)* __device__ int* bar(int *x) { return x; } -// CHECK: define{{.*}} spir_func noundef i32 addrspace(4)* @_Z5baz_dv() +// CHECK: define{{.*}} spir_func i32 addrspace(4)* @_Z5baz_dv() __device__ int* baz_d() { // CHECK: ret i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @d to i32 addrspace(4)* return &d; } -// CHECK: define{{.*}} spir_func noundef i32 addrspace(4)* @_Z5baz_cv() +// CHECK: define{{.*}} spir_func i32 addrspace(4)* @_Z5baz_cv() __device__ int* baz_c() { // CHECK: ret i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @c to i32 addrspace(4)* return &c; } -// CHECK: define{{.*}} spir_func noundef i32 addrspace(4)* @_Z5baz_sv() +// CHECK: define{{.*}} spir_func i32 addrspace(4)* @_Z5baz_sv() __device__ int* baz_s() { // CHECK: ret i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @s to i32 addrspace(4)* return &s; } -// CHECK: define{{.*}} spir_func noundef i8 addrspace(4)* @_Z3quzv() +// CHECK: define{{.*}} spir_func i8 addrspace(4)* @_Z3quzv() __device__ const char* quz() { return "abc"; } diff --git a/clang/test/CodeGenHIP/noundef-attribute-hip-device-verify.hip b/clang/test/CodeGenHIP/noundef-attribute-hip-device-verify.hip new file mode 100644 --- /dev/null +++ b/clang/test/CodeGenHIP/noundef-attribute-hip-device-verify.hip @@ -0,0 +1,38 @@ +// RUN: %clang_cc1 -no-opaque-pointers -triple amdgcn-amd-amdhsa -target-cpu gfx906 -x hip -fcuda-is-device -emit-llvm %s \ +// RUN: -o - | FileCheck %s + +#define __global__ __attribute__((global)) +#define __device__ __attribute__((device)) +#define WARP_SIZE 64 + +static constexpr int warpSize = __AMDGCN_WAVEFRONT_SIZE; + +__device__ static inline unsigned int __lane_id() { + return __builtin_amdgcn_mbcnt_hi( + -1, __builtin_amdgcn_mbcnt_lo(-1, 0)); +} + +__device__ +inline +int __shfl(int var, int src_lane, int width = warpSize) { + int self = __lane_id(); + int index = src_lane + (self & ~(width-1)); + return __builtin_amdgcn_ds_bpermute(index<<2, var); +} + +template +static __device__ +T __shfl_sync(unsigned mask, T val, int src_line, int width=WARP_SIZE) +{ + return __shfl(val, src_line, width); +} + +// CHECK-LABEL: @_Z13shufflekernelv( +// CHECK: call i32 @_ZL11__shfl_syncIiET_jS0_ii(i32 64, i32 %0, i32 0, i32 64) + +__global__ void +shufflekernel() +{ + int res, t; + res = __shfl_sync(WARP_SIZE, t, 0); +} diff --git a/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl b/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl --- a/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl +++ b/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl @@ -45,7 +45,7 @@ struct LargeStructOneMember g_s; #endif -// X86-LABEL: define{{.*}} void @foo(%struct.Mat4X4* noalias sret(%struct.Mat4X4) align 4 %agg.result, %struct.Mat3X3* noundef byval(%struct.Mat3X3) align 4 %in) +// X86-LABEL: define{{.*}} void @foo(%struct.Mat4X4* noalias sret(%struct.Mat4X4) align 4 %agg.result, %struct.Mat3X3* byval(%struct.Mat3X3) align 4 %in) // AMDGCN-LABEL: define{{.*}} %struct.Mat4X4 @foo([9 x i32] %in.coerce) Mat4X4 __attribute__((noinline)) foo(Mat3X3 in) { Mat4X4 out; @@ -65,8 +65,8 @@ out[0] = foo(in[1]); } -// X86-LABEL: define{{.*}} void @foo_large(%struct.Mat64X64* noalias sret(%struct.Mat64X64) align 4 %agg.result, %struct.Mat32X32* noundef byval(%struct.Mat32X32) align 4 %in) -// AMDGCN-LABEL: define{{.*}} void @foo_large(%struct.Mat64X64 addrspace(5)* noalias sret(%struct.Mat64X64) align 4 %agg.result, %struct.Mat32X32 addrspace(5)* noundef byval(%struct.Mat32X32) align 4 %in) +// X86-LABEL: define{{.*}} void @foo_large(%struct.Mat64X64* noalias sret(%struct.Mat64X64) align 4 %agg.result, %struct.Mat32X32* byval(%struct.Mat32X32) align 4 %in) +// AMDGCN-LABEL: define{{.*}} void @foo_large(%struct.Mat64X64 addrspace(5)* noalias sret(%struct.Mat64X64) align 4 %agg.result, %struct.Mat32X32 addrspace(5)* byval(%struct.Mat32X32) align 4 %in) Mat64X64 __attribute__((noinline)) foo_large(Mat32X32 in) { Mat64X64 out; return out; @@ -88,7 +88,7 @@ u.x = (int2)(0, 0); } -// AMDGCN-LABEL: define{{.*}} void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %u) +// AMDGCN-LABEL: define{{.*}} void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %u) // AMDGCN-NOT: addrspacecast // AMDGCN: store <2 x i32> %{{.*}}, <2 x i32> addrspace(5)* void FuncOneLargeMember(struct LargeStructOneMember u) { @@ -99,7 +99,7 @@ // AMDGCN20: %[[byval_temp:.*]] = alloca %struct.LargeStructOneMember, align 8, addrspace(5) // AMDGCN20: %[[r0:.*]] = bitcast %struct.LargeStructOneMember addrspace(5)* %[[byval_temp]] to i8 addrspace(5)* // AMDGCN20: call void @llvm.memcpy.p5i8.p1i8.i64(i8 addrspace(5)* align 8 %[[r0]], i8 addrspace(1)* align 8 bitcast (%struct.LargeStructOneMember addrspace(1)* @g_s to i8 addrspace(1)*), i64 800, i1 false) -// AMDGCN20: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %[[byval_temp]]) +// AMDGCN20: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %[[byval_temp]]) #if (__OPENCL_C_VERSION__ == 200) || (__OPENCL_C_VERSION__ >= 300 && defined(__opencl_c_program_scope_global_variables)) void test_indirect_arg_globl(void) { FuncOneLargeMember(g_s); @@ -110,7 +110,7 @@ // AMDGCN: %[[byval_temp:.*]] = alloca %struct.LargeStructOneMember, align 8, addrspace(5) // AMDGCN: %[[r0:.*]] = bitcast %struct.LargeStructOneMember addrspace(5)* %[[byval_temp]] to i8 addrspace(5)* // AMDGCN: call void @llvm.memcpy.p5i8.p3i8.i64(i8 addrspace(5)* align 8 %[[r0]], i8 addrspace(3)* align 8 bitcast (%struct.LargeStructOneMember addrspace(3)* @test_indirect_arg_local.l_s to i8 addrspace(3)*), i64 800, i1 false) -// AMDGCN: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %[[byval_temp]]) +// AMDGCN: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %[[byval_temp]]) kernel void test_indirect_arg_local(void) { local struct LargeStructOneMember l_s; FuncOneLargeMember(l_s); @@ -119,7 +119,7 @@ // AMDGCN-LABEL: define{{.*}} void @test_indirect_arg_private() // AMDGCN: %[[p_s:.*]] = alloca %struct.LargeStructOneMember, align 8, addrspace(5) // AMDGCN-NOT: @llvm.memcpy -// AMDGCN-NEXT: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %[[p_s]]) +// AMDGCN-NEXT: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %[[p_s]]) void test_indirect_arg_private(void) { struct LargeStructOneMember p_s; FuncOneLargeMember(p_s); @@ -144,7 +144,7 @@ // AMDGCN-LABEL: define{{.*}} amdgpu_kernel void @KernelLargeOneMember( // AMDGCN: %[[U:.*]] = alloca %struct.LargeStructOneMember, align 8, addrspace(5) // AMDGCN: store %struct.LargeStructOneMember %u.coerce, %struct.LargeStructOneMember addrspace(5)* %[[U]], align 8 -// AMDGCN: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %[[U]]) +// AMDGCN: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %[[U]]) kernel void KernelLargeOneMember(struct LargeStructOneMember u) { FuncOneLargeMember(u); } @@ -154,7 +154,7 @@ u.y = (int2)(0, 0); } -// AMDGCN-LABEL: define{{.*}} void @FuncLargeTwoMember(%struct.LargeStructTwoMember addrspace(5)* noundef byval(%struct.LargeStructTwoMember) align 8 %u) +// AMDGCN-LABEL: define{{.*}} void @FuncLargeTwoMember(%struct.LargeStructTwoMember addrspace(5)* byval(%struct.LargeStructTwoMember) align 8 %u) void FuncLargeTwoMember(struct LargeStructTwoMember u) { u.y[0] = (int2)(0, 0); } @@ -173,7 +173,7 @@ // AMDGCN-SAME: (%struct.LargeStructTwoMember %[[u_coerce:.*]]) // AMDGCN: %[[u:.*]] = alloca %struct.LargeStructTwoMember, align 8, addrspace(5) // AMDGCN: store %struct.LargeStructTwoMember %[[u_coerce]], %struct.LargeStructTwoMember addrspace(5)* %[[u]] -// AMDGCN: call void @FuncLargeTwoMember(%struct.LargeStructTwoMember addrspace(5)* noundef byval(%struct.LargeStructTwoMember) align 8 %[[u]]) +// AMDGCN: call void @FuncLargeTwoMember(%struct.LargeStructTwoMember addrspace(5)* byval(%struct.LargeStructTwoMember) align 8 %[[u]]) kernel void KernelLargeTwoMember(struct LargeStructTwoMember u) { FuncLargeTwoMember(u); } diff --git a/clang/test/CodeGenOpenCL/address-spaces.cl b/clang/test/CodeGenOpenCL/address-spaces.cl --- a/clang/test/CodeGenOpenCL/address-spaces.cl +++ b/clang/test/CodeGenOpenCL/address-spaces.cl @@ -72,10 +72,10 @@ // CL20AMDGCN-DAG: @ptr = {{(dso_local )?}}addrspace(1) global i32* null #endif -// SPIR: i32* noundef %arg -// AMDGCN: i32 addrspace(5)* noundef %arg -// CL20SPIR-DAG: i32 addrspace(4)* noundef %arg -// CL20AMDGCN-DAG: i32* noundef %arg +// SPIR: i32* %arg +// AMDGCN: i32 addrspace(5)* %arg +// CL20SPIR-DAG: i32 addrspace(4)* %arg +// CL20AMDGCN-DAG: i32* %arg void f(int *arg) { int i; @@ -92,7 +92,7 @@ typedef int int_td; typedef int *intp_td; -// SPIR: define {{(dso_local )?}}void @{{.*}}test_typedef{{.*}}(i32 addrspace(1)* noundef %x, i32 addrspace(2)* noundef %y, i32* noundef %z) +// SPIR: define {{(dso_local )?}}void @{{.*}}test_typedef{{.*}}(i32 addrspace(1)* %x, i32 addrspace(2)* %y, i32* %z) void test_typedef(global int_td *x, constant int_td *y, intp_td z) { *x = *y; *z = 0; diff --git a/clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl b/clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl --- a/clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl +++ b/clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl @@ -1,8 +1,8 @@ // RUN: %clang_cc1 -no-opaque-pointers -O0 -cl-std=CL1.2 -triple amdgcn---amdgizcl -emit-llvm %s -o - | FileCheck -check-prefixes=CHECK,CL12 %s // RUN: %clang_cc1 -no-opaque-pointers -O0 -cl-std=CL2.0 -triple amdgcn---amdgizcl -emit-llvm %s -o - | FileCheck -check-prefixes=CHECK,CL20 %s -// CL12-LABEL: define{{.*}} void @func1(i32 addrspace(5)* noundef %x) -// CL20-LABEL: define{{.*}} void @func1(i32* noundef %x) +// CL12-LABEL: define{{.*}} void @func1(i32 addrspace(5)* %x) +// CL20-LABEL: define{{.*}} void @func1(i32* %x) void func1(int *x) { // CL12: %[[x_addr:.*]] = alloca i32 addrspace(5)*{{.*}}addrspace(5) // CL12: store i32 addrspace(5)* %x, i32 addrspace(5)* addrspace(5)* %[[x_addr]] @@ -48,9 +48,9 @@ // CL20: store i32* %[[r1]], i32* addrspace(5)* %lp2, align 8 int *lp2 = la; - // CL12: call void @func1(i32 addrspace(5)* noundef %lv1) + // CL12: call void @func1(i32 addrspace(5)* %lv1) // CL20: %[[r2:.*]] = addrspacecast i32 addrspace(5)* %lv1 to i32* - // CL20: call void @func1(i32* noundef %[[r2]]) + // CL20: call void @func1(i32* %[[r2]]) func1(&lv1); // CHECK: store i32 4, i32 addrspace(5)* %lvc diff --git a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl --- a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl @@ -248,22 +248,22 @@ // CHECK: void @kernel_different_size_type_pair_arg(%struct.different_size_type_pair %arg1.coerce) __kernel void kernel_different_size_type_pair_arg(different_size_type_pair arg1) { } -// CHECK: define{{.*}} void @func_f32_arg(float noundef %arg) +// CHECK: define{{.*}} void @func_f32_arg(float %arg) void func_f32_arg(float arg) { } -// CHECK: define{{.*}} void @func_v2i16_arg(<2 x i16> noundef %arg) +// CHECK: define{{.*}} void @func_v2i16_arg(<2 x i16> %arg) void func_v2i16_arg(short2 arg) { } -// CHECK: define{{.*}} void @func_v3i32_arg(<3 x i32> noundef %arg) +// CHECK: define{{.*}} void @func_v3i32_arg(<3 x i32> %arg) void func_v3i32_arg(int3 arg) { } -// CHECK: define{{.*}} void @func_v4i32_arg(<4 x i32> noundef %arg) +// CHECK: define{{.*}} void @func_v4i32_arg(<4 x i32> %arg) void func_v4i32_arg(int4 arg) { } -// CHECK: define{{.*}} void @func_v16i32_arg(<16 x i32> noundef %arg) +// CHECK: define{{.*}} void @func_v16i32_arg(<16 x i32> %arg) void func_v16i32_arg(int16 arg) { } -// CHECK: define{{.*}} void @func_v32i32_arg(<32 x i32> noundef %arg) +// CHECK: define{{.*}} void @func_v32i32_arg(<32 x i32> %arg) void func_v32i32_arg(int32 arg) { } // CHECK: define{{.*}} void @func_empty_struct_arg() @@ -308,7 +308,7 @@ // CHECK: void @func_different_size_type_pair_arg(i64 %arg1.coerce0, i32 %arg1.coerce1) void func_different_size_type_pair_arg(different_size_type_pair arg1) { } -// CHECK: void @func_flexible_array_arg(%struct.flexible_array addrspace(5)* nocapture noundef byval(%struct.flexible_array) align 4 %arg) +// CHECK: void @func_flexible_array_arg(%struct.flexible_array addrspace(5)* nocapture byval(%struct.flexible_array) align 4 %arg) void func_flexible_array_arg(flexible_array arg) { } // CHECK: define{{.*}} float @func_f32_ret() @@ -446,20 +446,20 @@ return s; } -// CHECK: define{{.*}} void @func_reg_state_lo(<4 x i32> noundef %arg0, <4 x i32> noundef %arg1, <4 x i32> noundef %arg2, i32 noundef %arg3, i32 %s.coerce0, float %s.coerce1, i32 %s.coerce2) +// CHECK: define{{.*}} void @func_reg_state_lo(<4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, i32 %arg3, i32 %s.coerce0, float %s.coerce1, i32 %s.coerce2) void func_reg_state_lo(int4 arg0, int4 arg1, int4 arg2, int arg3, struct_arg_t s) { } -// CHECK: define{{.*}} void @func_reg_state_hi(<4 x i32> noundef %arg0, <4 x i32> noundef %arg1, <4 x i32> noundef %arg2, i32 noundef %arg3, i32 noundef %arg4, %struct.struct_arg addrspace(5)* nocapture noundef byval(%struct.struct_arg) align 4 %s) +// CHECK: define{{.*}} void @func_reg_state_hi(<4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, i32 %arg3, i32 %arg4, %struct.struct_arg addrspace(5)* nocapture byval(%struct.struct_arg) align 4 %s) void func_reg_state_hi(int4 arg0, int4 arg1, int4 arg2, int arg3, int arg4, struct_arg_t s) { } // XXX - Why don't the inner structs flatten? -// CHECK: define{{.*}} void @func_reg_state_num_regs_nested_struct(<4 x i32> noundef %arg0, i32 noundef %arg1, i32 %arg2.coerce0, %struct.nested %arg2.coerce1, i32 %arg3.coerce0, %struct.nested %arg3.coerce1, %struct.num_regs_nested_struct addrspace(5)* nocapture noundef byval(%struct.num_regs_nested_struct) align 8 %arg4) +// CHECK: define{{.*}} void @func_reg_state_num_regs_nested_struct(<4 x i32> %arg0, i32 %arg1, i32 %arg2.coerce0, %struct.nested %arg2.coerce1, i32 %arg3.coerce0, %struct.nested %arg3.coerce1, %struct.num_regs_nested_struct addrspace(5)* nocapture byval(%struct.num_regs_nested_struct) align 8 %arg4) void func_reg_state_num_regs_nested_struct(int4 arg0, int arg1, num_regs_nested_struct arg2, num_regs_nested_struct arg3, num_regs_nested_struct arg4) { } -// CHECK: define{{.*}} void @func_double_nested_struct_arg(<4 x i32> noundef %arg0, i32 noundef %arg1, i32 %arg2.coerce0, %struct.double_nested %arg2.coerce1, i16 %arg2.coerce2) +// CHECK: define{{.*}} void @func_double_nested_struct_arg(<4 x i32> %arg0, i32 %arg1, i32 %arg2.coerce0, %struct.double_nested %arg2.coerce1, i16 %arg2.coerce2) void func_double_nested_struct_arg(int4 arg0, int arg1, double_nested_struct arg2) { } -// CHECK: define{{.*}} %struct.double_nested_struct @func_double_nested_struct_ret(<4 x i32> noundef %arg0, i32 noundef %arg1) +// CHECK: define{{.*}} %struct.double_nested_struct @func_double_nested_struct_ret(<4 x i32> %arg0, i32 %arg1) double_nested_struct func_double_nested_struct_ret(int4 arg0, int arg1) { double_nested_struct s = { 0 }; return s; @@ -468,55 +468,55 @@ // CHECK: define{{.*}} void @func_large_struct_padding_arg_direct(i8 %arg.coerce0, i32 %arg.coerce1, i8 %arg.coerce2, i32 %arg.coerce3, i8 %arg.coerce4, i8 %arg.coerce5, i16 %arg.coerce6, i16 %arg.coerce7, [3 x i8] %arg.coerce8, i64 %arg.coerce9, i32 %arg.coerce10, i8 %arg.coerce11, i32 %arg.coerce12, i16 %arg.coerce13, i8 %arg.coerce14) void func_large_struct_padding_arg_direct(large_struct_padding arg) { } -// CHECK: define{{.*}} void @func_large_struct_padding_arg_store(%struct.large_struct_padding addrspace(1)* nocapture noundef writeonly %out, %struct.large_struct_padding addrspace(5)* nocapture noundef readonly byval(%struct.large_struct_padding) align 8 %arg) +// CHECK: define{{.*}} void @func_large_struct_padding_arg_store(%struct.large_struct_padding addrspace(1)* nocapture writeonly %out, %struct.large_struct_padding addrspace(5)* nocapture readonly byval(%struct.large_struct_padding) align 8 %arg) void func_large_struct_padding_arg_store(global large_struct_padding* out, large_struct_padding arg) { *out = arg; } -// CHECK: define{{.*}} void @v3i32_reg_count(<3 x i32> noundef %arg1, <3 x i32> noundef %arg2, <3 x i32> noundef %arg3, <3 x i32> noundef %arg4, i32 %arg5.coerce0, float %arg5.coerce1, i32 %arg5.coerce2) +// CHECK: define{{.*}} void @v3i32_reg_count(<3 x i32> %arg1, <3 x i32> %arg2, <3 x i32> %arg3, <3 x i32> %arg4, i32 %arg5.coerce0, float %arg5.coerce1, i32 %arg5.coerce2) void v3i32_reg_count(int3 arg1, int3 arg2, int3 arg3, int3 arg4, struct_arg_t arg5) { } // Function signature from blender, nothing should be passed byval. The v3i32 // should not count as 4 passed registers. -// CHECK: define{{.*}} void @v3i32_pair_reg_count(%struct.int3_pair addrspace(5)* nocapture noundef %arg0, <3 x i32> %arg1.coerce0, <3 x i32> %arg1.coerce1, <3 x i32> noundef %arg2, <3 x i32> %arg3.coerce0, <3 x i32> %arg3.coerce1, <3 x i32> noundef %arg4, float noundef %arg5) +// CHECK: define{{.*}} void @v3i32_pair_reg_count(%struct.int3_pair addrspace(5)* nocapture %arg0, <3 x i32> %arg1.coerce0, <3 x i32> %arg1.coerce1, <3 x i32> %arg2, <3 x i32> %arg3.coerce0, <3 x i32> %arg3.coerce1, <3 x i32> %arg4, float %arg5) void v3i32_pair_reg_count(int3_pair *arg0, int3_pair arg1, int3 arg2, int3_pair arg3, int3 arg4, float arg5) { } // Each short4 should fit pack into 2 registers. -// CHECK: define{{.*}} void @v4i16_reg_count(<4 x i16> noundef %arg0, <4 x i16> noundef %arg1, <4 x i16> noundef %arg2, <4 x i16> noundef %arg3, <4 x i16> noundef %arg4, <4 x i16> noundef %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) +// CHECK: define{{.*}} void @v4i16_reg_count(<4 x i16> %arg0, <4 x i16> %arg1, <4 x i16> %arg2, <4 x i16> %arg3, <4 x i16> %arg4, <4 x i16> %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) void v4i16_reg_count(short4 arg0, short4 arg1, short4 arg2, short4 arg3, short4 arg4, short4 arg5, struct_4regs arg6) { } -// CHECK: define{{.*}} void @v4i16_pair_reg_count_over(<4 x i16> noundef %arg0, <4 x i16> noundef %arg1, <4 x i16> noundef %arg2, <4 x i16> noundef %arg3, <4 x i16> noundef %arg4, <4 x i16> noundef %arg5, <4 x i16> noundef %arg6, %struct.struct_4regs addrspace(5)* nocapture noundef byval(%struct.struct_4regs) align 4 %arg7) +// CHECK: define{{.*}} void @v4i16_pair_reg_count_over(<4 x i16> %arg0, <4 x i16> %arg1, <4 x i16> %arg2, <4 x i16> %arg3, <4 x i16> %arg4, <4 x i16> %arg5, <4 x i16> %arg6, %struct.struct_4regs addrspace(5)* nocapture byval(%struct.struct_4regs) align 4 %arg7) void v4i16_pair_reg_count_over(short4 arg0, short4 arg1, short4 arg2, short4 arg3, short4 arg4, short4 arg5, short4 arg6, struct_4regs arg7) { } -// CHECK: define{{.*}} void @v3i16_reg_count(<3 x i16> noundef %arg0, <3 x i16> noundef %arg1, <3 x i16> noundef %arg2, <3 x i16> noundef %arg3, <3 x i16> noundef %arg4, <3 x i16> noundef %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) +// CHECK: define{{.*}} void @v3i16_reg_count(<3 x i16> %arg0, <3 x i16> %arg1, <3 x i16> %arg2, <3 x i16> %arg3, <3 x i16> %arg4, <3 x i16> %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) void v3i16_reg_count(short3 arg0, short3 arg1, short3 arg2, short3 arg3, short3 arg4, short3 arg5, struct_4regs arg6) { } -// CHECK: define{{.*}} void @v3i16_reg_count_over(<3 x i16> noundef %arg0, <3 x i16> noundef %arg1, <3 x i16> noundef %arg2, <3 x i16> noundef %arg3, <3 x i16> noundef %arg4, <3 x i16> noundef %arg5, <3 x i16> noundef %arg6, %struct.struct_4regs addrspace(5)* nocapture noundef byval(%struct.struct_4regs) align 4 %arg7) +// CHECK: define{{.*}} void @v3i16_reg_count_over(<3 x i16> %arg0, <3 x i16> %arg1, <3 x i16> %arg2, <3 x i16> %arg3, <3 x i16> %arg4, <3 x i16> %arg5, <3 x i16> %arg6, %struct.struct_4regs addrspace(5)* nocapture byval(%struct.struct_4regs) align 4 %arg7) void v3i16_reg_count_over(short3 arg0, short3 arg1, short3 arg2, short3 arg3, short3 arg4, short3 arg5, short3 arg6, struct_4regs arg7) { } -// CHECK: define{{.*}} void @v2i16_reg_count(<2 x i16> noundef %arg0, <2 x i16> noundef %arg1, <2 x i16> noundef %arg2, <2 x i16> noundef %arg3, <2 x i16> noundef %arg4, <2 x i16> noundef %arg5, <2 x i16> noundef %arg6, <2 x i16> noundef %arg7, <2 x i16> noundef %arg8, <2 x i16> noundef %arg9, <2 x i16> noundef %arg10, <2 x i16> noundef %arg11, i32 %arg13.coerce0, i32 %arg13.coerce1, i32 %arg13.coerce2, i32 %arg13.coerce3) +// CHECK: define{{.*}} void @v2i16_reg_count(<2 x i16> %arg0, <2 x i16> %arg1, <2 x i16> %arg2, <2 x i16> %arg3, <2 x i16> %arg4, <2 x i16> %arg5, <2 x i16> %arg6, <2 x i16> %arg7, <2 x i16> %arg8, <2 x i16> %arg9, <2 x i16> %arg10, <2 x i16> %arg11, i32 %arg13.coerce0, i32 %arg13.coerce1, i32 %arg13.coerce2, i32 %arg13.coerce3) void v2i16_reg_count(short2 arg0, short2 arg1, short2 arg2, short2 arg3, short2 arg4, short2 arg5, short2 arg6, short2 arg7, short2 arg8, short2 arg9, short2 arg10, short2 arg11, struct_4regs arg13) { } -// CHECK: define{{.*}} void @v2i16_reg_count_over(<2 x i16> noundef %arg0, <2 x i16> noundef %arg1, <2 x i16> noundef %arg2, <2 x i16> noundef %arg3, <2 x i16> noundef %arg4, <2 x i16> noundef %arg5, <2 x i16> noundef %arg6, <2 x i16> noundef %arg7, <2 x i16> noundef %arg8, <2 x i16> noundef %arg9, <2 x i16> noundef %arg10, <2 x i16> noundef %arg11, <2 x i16> noundef %arg12, %struct.struct_4regs addrspace(5)* nocapture noundef byval(%struct.struct_4regs) align 4 %arg13) +// CHECK: define{{.*}} void @v2i16_reg_count_over(<2 x i16> %arg0, <2 x i16> %arg1, <2 x i16> %arg2, <2 x i16> %arg3, <2 x i16> %arg4, <2 x i16> %arg5, <2 x i16> %arg6, <2 x i16> %arg7, <2 x i16> %arg8, <2 x i16> %arg9, <2 x i16> %arg10, <2 x i16> %arg11, <2 x i16> %arg12, %struct.struct_4regs addrspace(5)* nocapture byval(%struct.struct_4regs) align 4 %arg13) void v2i16_reg_count_over(short2 arg0, short2 arg1, short2 arg2, short2 arg3, short2 arg4, short2 arg5, short2 arg6, short2 arg7, short2 arg8, short2 arg9, short2 arg10, short2 arg11, short2 arg12, struct_4regs arg13) { } -// CHECK: define{{.*}} void @v2i8_reg_count(<2 x i8> noundef %arg0, <2 x i8> noundef %arg1, <2 x i8> noundef %arg2, <2 x i8> noundef %arg3, <2 x i8> noundef %arg4, <2 x i8> noundef %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) +// CHECK: define{{.*}} void @v2i8_reg_count(<2 x i8> %arg0, <2 x i8> %arg1, <2 x i8> %arg2, <2 x i8> %arg3, <2 x i8> %arg4, <2 x i8> %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) void v2i8_reg_count(char2 arg0, char2 arg1, char2 arg2, char2 arg3, char2 arg4, char2 arg5, struct_4regs arg6) { } -// CHECK: define{{.*}} void @v2i8_reg_count_over(<2 x i8> noundef %arg0, <2 x i8> noundef %arg1, <2 x i8> noundef %arg2, <2 x i8> noundef %arg3, <2 x i8> noundef %arg4, <2 x i8> noundef %arg5, i32 noundef %arg6, %struct.struct_4regs addrspace(5)* nocapture noundef byval(%struct.struct_4regs) align 4 %arg7) +// CHECK: define{{.*}} void @v2i8_reg_count_over(<2 x i8> %arg0, <2 x i8> %arg1, <2 x i8> %arg2, <2 x i8> %arg3, <2 x i8> %arg4, <2 x i8> %arg5, i32 %arg6, %struct.struct_4regs addrspace(5)* nocapture byval(%struct.struct_4regs) align 4 %arg7) void v2i8_reg_count_over(char2 arg0, char2 arg1, char2 arg2, char2 arg3, char2 arg4, char2 arg5, int arg6, struct_4regs arg7) { } -// CHECK: define{{.*}} void @num_regs_left_64bit_aggregate(<4 x i32> noundef %arg0, <4 x i32> noundef %arg1, <4 x i32> noundef %arg2, <3 x i32> noundef %arg3, [2 x i32] %arg4.coerce, i32 noundef %arg5) +// CHECK: define{{.*}} void @num_regs_left_64bit_aggregate(<4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, <3 x i32> %arg3, [2 x i32] %arg4.coerce, i32 %arg5) void num_regs_left_64bit_aggregate(int4 arg0, int4 arg1, int4 arg2, int3 arg3, struct_char_x8 arg4, int arg5) { } diff --git a/clang/test/CodeGenOpenCL/amdgpu-call-kernel.cl b/clang/test/CodeGenOpenCL/amdgpu-call-kernel.cl --- a/clang/test/CodeGenOpenCL/amdgpu-call-kernel.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-call-kernel.cl @@ -1,6 +1,6 @@ // REQUIRES: amdgpu-registered-target // RUN: %clang_cc1 -no-opaque-pointers -triple amdgcn-unknown-unknown -S -emit-llvm -o - %s | FileCheck %s -// CHECK: define{{.*}} amdgpu_kernel void @test_call_kernel(i32 addrspace(1)* nocapture noundef writeonly align 4 %out) +// CHECK: define{{.*}} amdgpu_kernel void @test_call_kernel(i32 addrspace(1)* nocapture writeonly align 4 %out) // CHECK: store i32 4, i32 addrspace(1)* %out, align 4 kernel void test_kernel(global int *out) diff --git a/clang/test/CodeGenOpenCL/amdgpu-printf.cl b/clang/test/CodeGenOpenCL/amdgpu-printf.cl --- a/clang/test/CodeGenOpenCL/amdgpu-printf.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-printf.cl @@ -5,7 +5,7 @@ // CHECK-LABEL: @test_printf_noargs( // CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8 addrspace(4)*, ...) @printf(i8 addrspace(4)* noundef getelementptr inbounds ([1 x i8], [1 x i8] addrspace(4)* @.str, i64 0, i64 0)) #[[ATTR4:[0-9]+]] +// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8 addrspace(4)*, ...) @printf(i8 addrspace(4)* getelementptr inbounds ([1 x i8], [1 x i8] addrspace(4)* @.str, i64 0, i64 0)) #[[ATTR4:[0-9]+]] // CHECK-NEXT: ret void // __kernel void test_printf_noargs() { @@ -17,7 +17,7 @@ // CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: store i32 [[I:%.*]], i32 addrspace(5)* [[I_ADDR]], align 4, !tbaa [[TBAA8:![0-9]+]] // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32 addrspace(5)* [[I_ADDR]], align 4, !tbaa [[TBAA8]] -// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8 addrspace(4)*, ...) @printf(i8 addrspace(4)* noundef getelementptr inbounds ([3 x i8], [3 x i8] addrspace(4)* @.str.1, i64 0, i64 0), i32 noundef [[TMP0]]) #[[ATTR4]] +// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8 addrspace(4)*, ...) @printf(i8 addrspace(4)* getelementptr inbounds ([3 x i8], [3 x i8] addrspace(4)* @.str.1, i64 0, i64 0), i32 [[TMP0]]) #[[ATTR4]] // CHECK-NEXT: ret void // __kernel void test_printf_int(int i) { @@ -35,7 +35,7 @@ // CHECK-NEXT: call void @llvm.memcpy.p5i8.p4i8.i64(i8 addrspace(5)* align 1 [[TMP1]], i8 addrspace(4)* align 1 getelementptr inbounds ([4 x i8], [4 x i8] addrspace(4)* @__const.test_printf_str_int.s, i32 0, i32 0), i64 4, i1 false) // CHECK-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], [4 x i8] addrspace(5)* [[S]], i64 0, i64 0 // CHECK-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(5)* [[I_ADDR]], align 4, !tbaa [[TBAA8]] -// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8 addrspace(4)*, ...) @printf(i8 addrspace(4)* noundef getelementptr inbounds ([6 x i8], [6 x i8] addrspace(4)* @.str.2, i64 0, i64 0), i8 addrspace(5)* noundef [[ARRAYDECAY]], i32 noundef [[TMP2]]) #[[ATTR4]] +// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8 addrspace(4)*, ...) @printf(i8 addrspace(4)* getelementptr inbounds ([6 x i8], [6 x i8] addrspace(4)* @.str.2, i64 0, i64 0), i8 addrspace(5)* [[ARRAYDECAY]], i32 [[TMP2]]) #[[ATTR4]] // CHECK-NEXT: [[TMP3:%.*]] = bitcast [4 x i8] addrspace(5)* [[S]] to i8 addrspace(5)* // CHECK-NEXT: call void @llvm.lifetime.end.p5i8(i64 4, i8 addrspace(5)* [[TMP3]]) #[[ATTR5]] // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenOpenCL/as_type.cl b/clang/test/CodeGenOpenCL/as_type.cl --- a/clang/test/CodeGenOpenCL/as_type.cl +++ b/clang/test/CodeGenOpenCL/as_type.cl @@ -5,21 +5,21 @@ typedef __attribute__(( ext_vector_type(16) )) char char16; typedef __attribute__(( ext_vector_type(3) )) int int3; -//CHECK: define{{.*}} spir_func <3 x i8> @f1(<4 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i8> @f1(<4 x i8> %[[x:.*]]) //CHECK: %[[astype:.*]] = shufflevector <4 x i8> %[[x]], <4 x i8> poison, <3 x i32> //CHECK: ret <3 x i8> %[[astype]] char3 f1(char4 x) { return __builtin_astype(x, char3); } -//CHECK: define{{.*}} spir_func <4 x i8> @f2(<3 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <4 x i8> @f2(<3 x i8> %[[x:.*]]) //CHECK: %[[astype:.*]] = shufflevector <3 x i8> %[[x]], <3 x i8> poison, <4 x i32> //CHECK: ret <4 x i8> %[[astype]] char4 f2(char3 x) { return __builtin_astype(x, char4); } -//CHECK: define{{.*}} spir_func <3 x i8> @f3(i32 noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i8> @f3(i32 %[[x:.*]]) //CHECK: %[[cast:.*]] = bitcast i32 %[[x]] to <4 x i8> //CHECK: %[[astype:.*]] = shufflevector <4 x i8> %[[cast]], <4 x i8> poison, <3 x i32> //CHECK: ret <3 x i8> %[[astype]] @@ -27,7 +27,7 @@ return __builtin_astype(x, char3); } -//CHECK: define{{.*}} spir_func <4 x i8> @f4(i32 noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <4 x i8> @f4(i32 %[[x:.*]]) //CHECK: %[[astype:.*]] = bitcast i32 %[[x]] to <4 x i8> //CHECK-NOT: shufflevector //CHECK: ret <4 x i8> %[[astype]] @@ -35,7 +35,7 @@ return __builtin_astype(x, char4); } -//CHECK: define{{.*}} spir_func i32 @f5(<3 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 @f5(<3 x i8> %[[x:.*]]) //CHECK: %[[shuffle:.*]] = shufflevector <3 x i8> %[[x]], <3 x i8> poison, <4 x i32> //CHECK: %[[astype:.*]] = bitcast <4 x i8> %[[shuffle]] to i32 //CHECK: ret i32 %[[astype]] @@ -43,7 +43,7 @@ return __builtin_astype(x, int); } -//CHECK: define{{.*}} spir_func i32 @f6(<4 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 @f6(<4 x i8> %[[x:.*]]) //CHECK: %[[astype:.*]] = bitcast <4 x i8> %[[x]] to i32 //CHECK-NOT: shufflevector //CHECK: ret i32 %[[astype]] @@ -51,7 +51,7 @@ return __builtin_astype(x, int); } -//CHECK: define{{.*}} spir_func <3 x i8> @f7(<3 x i8> noundef returned %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i8> @f7(<3 x i8> returned %[[x:.*]]) //CHECK-NOT: bitcast //CHECK-NOT: shufflevector //CHECK: ret <3 x i8> %[[x]] @@ -59,7 +59,7 @@ return __builtin_astype(x, char3); } -//CHECK: define{{.*}} spir_func <3 x i32> @f8(<16 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i32> @f8(<16 x i8> %[[x:.*]]) //CHECK: %[[cast:.*]] = bitcast <16 x i8> %[[x]] to <4 x i32> //CHECK: %[[astype:.*]] = shufflevector <4 x i32> %[[cast]], <4 x i32> poison, <3 x i32> //CHECK: ret <3 x i32> %[[astype]] @@ -67,28 +67,28 @@ return __builtin_astype(x, int3); } -//CHECK: define{{.*}} spir_func i32 addrspace(1)* @addr_cast(i32* noundef readnone %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 addrspace(1)* @addr_cast(i32* readnone %[[x:.*]]) //CHECK: %[[cast:.*]] ={{.*}} addrspacecast i32* %[[x]] to i32 addrspace(1)* //CHECK: ret i32 addrspace(1)* %[[cast]] global int* addr_cast(int *x) { return __builtin_astype(x, global int*); } -//CHECK: define{{.*}} spir_func i32 addrspace(1)* @int_to_ptr(i32 noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 addrspace(1)* @int_to_ptr(i32 %[[x:.*]]) //CHECK: %[[cast:.*]] = inttoptr i32 %[[x]] to i32 addrspace(1)* //CHECK: ret i32 addrspace(1)* %[[cast]] global int* int_to_ptr(int x) { return __builtin_astype(x, global int*); } -//CHECK: define{{.*}} spir_func i32 @ptr_to_int(i32* noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 @ptr_to_int(i32* %[[x:.*]]) //CHECK: %[[cast:.*]] = ptrtoint i32* %[[x]] to i32 //CHECK: ret i32 %[[cast]] int ptr_to_int(int *x) { return __builtin_astype(x, int); } -//CHECK: define{{.*}} spir_func <3 x i8> @ptr_to_char3(i32* noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i8> @ptr_to_char3(i32* %[[x:.*]]) //CHECK: %[[cast1:.*]] = ptrtoint i32* %[[x]] to i32 //CHECK: %[[cast2:.*]] = bitcast i32 %[[cast1]] to <4 x i8> //CHECK: %[[astype:.*]] = shufflevector <4 x i8> %[[cast2]], <4 x i8> poison, <3 x i32> @@ -97,7 +97,7 @@ return __builtin_astype(x, char3); } -//CHECK: define{{.*}} spir_func i32* @char3_to_ptr(<3 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32* @char3_to_ptr(<3 x i8> %[[x:.*]]) //CHECK: %[[astype:.*]] = shufflevector <3 x i8> %[[x]], <3 x i8> poison, <4 x i32> //CHECK: %[[cast1:.*]] = bitcast <4 x i8> %[[astype]] to i32 //CHECK: %[[cast2:.*]] = inttoptr i32 %[[cast1]] to i32* diff --git a/clang/test/CodeGenOpenCL/atomic-ops-libcall.cl b/clang/test/CodeGenOpenCL/atomic-ops-libcall.cl --- a/clang/test/CodeGenOpenCL/atomic-ops-libcall.cl +++ b/clang/test/CodeGenOpenCL/atomic-ops-libcall.cl @@ -20,63 +20,63 @@ void f(atomic_int *i, global atomic_int *gi, local atomic_int *li, private atomic_int *pi, atomic_uint *ui, int cmp, int order, int scope) { int x; - // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8* noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8 addrspace(4)* {{%[0-9]+}}, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8* {{%[0-9]+}}, i32 5, i32 1) x = __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_work_group); - // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: call void @__opencl_atomic_store_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) __opencl_atomic_store(i, 1, memory_order_seq_cst, memory_scope_work_group); // SPIR: %[[GP:[0-9]+]] = addrspacecast i8 addrspace(1)* {{%[0-9]+}} to i8 addrspace(4)* - // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef %[[GP]], i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: call void @__opencl_atomic_store_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* %[[GP]], i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) __opencl_atomic_store(gi, 1, memory_order_seq_cst, memory_scope_work_group); // SPIR: %[[GP:[0-9]+]] = addrspacecast i8 addrspace(3)* {{%[0-9]+}} to i8 addrspace(4)* - // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef %[[GP]], i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: call void @__opencl_atomic_store_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* %[[GP]], i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) __opencl_atomic_store(li, 1, memory_order_seq_cst, memory_scope_work_group); // SPIR: %[[GP:[0-9]+]] = addrspacecast i8* {{%[0-9]+}} to i8 addrspace(4)* - // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef %[[GP]], i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: call void @__opencl_atomic_store_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* %[[GP]], i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) __opencl_atomic_store(pi, 1, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) x = __opencl_atomic_fetch_add(i, 3, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) x = __opencl_atomic_fetch_min(i, 3, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) x = __opencl_atomic_fetch_min(ui, 3, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1) x = __opencl_atomic_compare_exchange_strong(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 2) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 2) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 2) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 2) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_device); - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 3) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 3) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 3) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 3) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_all_svm_devices); #ifdef cl_khr_subgroups - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 4) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 4) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_sub_group); #endif - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, order, order, scope); } diff --git a/clang/test/CodeGenOpenCL/blocks.cl b/clang/test/CodeGenOpenCL/blocks.cl --- a/clang/test/CodeGenOpenCL/blocks.cl +++ b/clang/test/CodeGenOpenCL/blocks.cl @@ -13,8 +13,8 @@ // AMDGCN: @__block_literal_global = internal addrspace(1) constant { i32, i32, i8* } { i32 16, i32 8, i8* bitcast (void (i8*, i8 addrspace(3)*)* @block_A_block_invoke to i8*) } // COMMON-NOT: .str -// SPIR-LABEL: define internal {{.*}}void @block_A_block_invoke(i8 addrspace(4)* noundef %.block_descriptor, i8 addrspace(3)* noundef %a) -// AMDGCN-LABEL: define internal {{.*}}void @block_A_block_invoke(i8* noundef %.block_descriptor, i8 addrspace(3)* noundef %a) +// SPIR-LABEL: define internal {{.*}}void @block_A_block_invoke(i8 addrspace(4)* %.block_descriptor, i8 addrspace(3)* %a) +// AMDGCN-LABEL: define internal {{.*}}void @block_A_block_invoke(i8* %.block_descriptor, i8 addrspace(3)* %a) void (^block_A)(local void *) = ^(local void *a) { return; }; @@ -44,7 +44,7 @@ // SPIR: store %struct.__opencl_block_literal_generic addrspace(4)* %[[blk_gen_ptr]], %struct.__opencl_block_literal_generic addrspace(4)** %[[block_B:.*]], // SPIR: %[[block_literal:.*]] = load %struct.__opencl_block_literal_generic addrspace(4)*, %struct.__opencl_block_literal_generic addrspace(4)** %[[block_B]] // SPIR: %[[blk_gen_ptr:.*]] = bitcast %struct.__opencl_block_literal_generic addrspace(4)* %[[block_literal]] to i8 addrspace(4)* - // SPIR: call {{.*}}i32 @__foo_block_invoke(i8 addrspace(4)* noundef %[[blk_gen_ptr]]) + // SPIR: call {{.*}}i32 @__foo_block_invoke(i8 addrspace(4)* %[[blk_gen_ptr]]) // AMDGCN: %[[block_invoke:.*]] = getelementptr inbounds <{ i32, i32, i8*, i32 }>, <{ i32, i32, i8*, i32 }> addrspace(5)* %[[block:.*]], i32 0, i32 2 // AMDGCN: store i8* bitcast (i32 (i8*)* @__foo_block_invoke to i8*), i8* addrspace(5)* %[[block_invoke]] // AMDGCN: %[[block_captured:.*]] = getelementptr inbounds <{ i32, i32, i8*, i32 }>, <{ i32, i32, i8*, i32 }> addrspace(5)* %[[block]], i32 0, i32 3 @@ -55,7 +55,7 @@ // AMDGCN: store %struct.__opencl_block_literal_generic* %[[blk_gen_ptr]], %struct.__opencl_block_literal_generic* addrspace(5)* %[[block_B:.*]], // AMDGCN: %[[block_literal:.*]] = load %struct.__opencl_block_literal_generic*, %struct.__opencl_block_literal_generic* addrspace(5)* %[[block_B]] // AMDGCN: %[[blk_gen_ptr:.*]] = bitcast %struct.__opencl_block_literal_generic* %[[block_literal]] to i8* - // AMDGCN: call {{.*}}i32 @__foo_block_invoke(i8* noundef %[[blk_gen_ptr]]) + // AMDGCN: call {{.*}}i32 @__foo_block_invoke(i8* %[[blk_gen_ptr]]) int (^ block_B)(void) = ^{ return i; @@ -63,11 +63,11 @@ block_B(); } -// SPIR-LABEL: define internal {{.*}}i32 @__foo_block_invoke(i8 addrspace(4)* noundef %.block_descriptor) +// SPIR-LABEL: define internal {{.*}}i32 @__foo_block_invoke(i8 addrspace(4)* %.block_descriptor) // SPIR: %[[block:.*]] = bitcast i8 addrspace(4)* %.block_descriptor to <{ i32, i32, i8 addrspace(4)*, i32 }> addrspace(4)* // SPIR: %[[block_capture_addr:.*]] = getelementptr inbounds <{ i32, i32, i8 addrspace(4)*, i32 }>, <{ i32, i32, i8 addrspace(4)*, i32 }> addrspace(4)* %[[block]], i32 0, i32 3 // SPIR: %[[block_capture:.*]] = load i32, i32 addrspace(4)* %[[block_capture_addr]] -// AMDGCN-LABEL: define internal {{.*}}i32 @__foo_block_invoke(i8* noundef %.block_descriptor) +// AMDGCN-LABEL: define internal {{.*}}i32 @__foo_block_invoke(i8* %.block_descriptor) // AMDGCN: %[[block:.*]] = bitcast i8* %.block_descriptor to <{ i32, i32, i8*, i32 }>* // AMDGCN: %[[block_capture_addr:.*]] = getelementptr inbounds <{ i32, i32, i8*, i32 }>, <{ i32, i32, i8*, i32 }>* %[[block]], i32 0, i32 3 // AMDGCN: %[[block_capture:.*]] = load i32, i32* %[[block_capture_addr]] diff --git a/clang/test/CodeGenOpenCL/byval.cl b/clang/test/CodeGenOpenCL/byval.cl --- a/clang/test/CodeGenOpenCL/byval.cl +++ b/clang/test/CodeGenOpenCL/byval.cl @@ -8,8 +8,8 @@ int g() { struct A a; - // CHECK: call i32 @f(%struct.A addrspace(5)* noundef byval{{.*}}%a) + // CHECK: call i32 @f(%struct.A addrspace(5)* byval{{.*}}%a) return f(a); } -// CHECK: declare i32 @f(%struct.A addrspace(5)* noundef byval{{.*}}) +// CHECK: declare i32 @f(%struct.A addrspace(5)* byval{{.*}}) diff --git a/clang/test/CodeGenOpenCL/const-str-array-decay.cl b/clang/test/CodeGenOpenCL/const-str-array-decay.cl --- a/clang/test/CodeGenOpenCL/const-str-array-decay.cl +++ b/clang/test/CodeGenOpenCL/const-str-array-decay.cl @@ -6,6 +6,6 @@ test_func("Test string literal"); } -// CHECK: i8 addrspace(2)* noundef getelementptr inbounds ([20 x i8], [20 x i8] addrspace(2)* +// CHECK: i8 addrspace(2)* getelementptr inbounds ([20 x i8], [20 x i8] addrspace(2)* // CHECK-NOT: addrspacecast diff --git a/clang/test/CodeGenOpenCL/constant-addr-space-globals.cl b/clang/test/CodeGenOpenCL/constant-addr-space-globals.cl --- a/clang/test/CodeGenOpenCL/constant-addr-space-globals.cl +++ b/clang/test/CodeGenOpenCL/constant-addr-space-globals.cl @@ -26,6 +26,6 @@ constant int var1 = 1; - // CHECK: call spir_func void @foo(i32 addrspace(2)* noundef @k.var1, i32 addrspace(2)* noundef getelementptr inbounds ([3 x i32], [3 x i32] addrspace(2)* @k.arr1, i64 0, i64 0) + // CHECK: call spir_func void @foo(i32 addrspace(2)* @k.var1, i32 addrspace(2)* getelementptr inbounds ([3 x i32], [3 x i32] addrspace(2)* @k.arr1, i64 0, i64 0) foo(&var1, arr1, arr2, arr3); } diff --git a/clang/test/CodeGenOpenCL/convergent.cl b/clang/test/CodeGenOpenCL/convergent.cl --- a/clang/test/CodeGenOpenCL/convergent.cl +++ b/clang/test/CodeGenOpenCL/convergent.cl @@ -27,7 +27,7 @@ // non_convfun(); // } // -// CHECK-LABEL: define{{.*}} spir_func void @test_merge_if(i32 noundef %a) local_unnamed_addr #1 { +// CHECK-LABEL: define{{.*}} spir_func void @test_merge_if(i32 %a) local_unnamed_addr #1 { // CHECK: %[[tobool:.+]] = icmp eq i32 %a, 0 // CHECK: br i1 %[[tobool]], label %[[if_end3_critedge:.+]], label %[[if_then:.+]] @@ -60,12 +60,12 @@ // Test two if's are not merged. -// CHECK-LABEL: define{{.*}} spir_func void @test_no_merge_if(i32 noundef %a) local_unnamed_addr #1 +// CHECK-LABEL: define{{.*}} spir_func void @test_no_merge_if(i32 %a) local_unnamed_addr #1 // CHECK: %[[tobool:.+]] = icmp eq i32 %a, 0 // CHECK: br i1 %[[tobool]], label %[[if_end:.+]], label %[[if_then:.+]] // CHECK: [[if_then]]: // CHECK: tail call spir_func void @f() -// CHECK-NOT: call spir_func void @convfun() +// CHECK-NOT: call spir_func void @non_convfun() // CHECK-NOT: call spir_func void @g() // CHECK: br label %[[if_end]] // CHECK: [[if_end]]: diff --git a/clang/test/CodeGenOpenCL/fpmath.cl b/clang/test/CodeGenOpenCL/fpmath.cl --- a/clang/test/CodeGenOpenCL/fpmath.cl +++ b/clang/test/CodeGenOpenCL/fpmath.cl @@ -25,8 +25,8 @@ void printf(constant char* fmt, ...); void testdbllit(long *val) { - // CHECK-FLT: float noundef 2.000000e+01 - // CHECK-DBL: double noundef 2.000000e+01 + // CHECK-FLT: float 2.000000e+01 + // CHECK-DBL: double 2.000000e+01 printf("%f", 20.0); } diff --git a/clang/test/CodeGenOpenCL/half.cl b/clang/test/CodeGenOpenCL/half.cl --- a/clang/test/CodeGenOpenCL/half.cl +++ b/clang/test/CodeGenOpenCL/half.cl @@ -15,7 +15,7 @@ // CHECK: half 0xH3260 } -// CHECK-LABEL: @test_inc(half noundef %x) +// CHECK-LABEL: @test_inc(half %x) // CHECK: [[INC:%.*]] = fadd half %x, 0xH3C00 // CHECK: ret half [[INC]] half test_inc(half x) @@ -30,12 +30,12 @@ __kernel void foo( __global half* buf, __global float* buf2 ) { buf[0] = min( buf[0], 1.5h ); -// CHECK: half noundef 0xH3E00 +// CHECK: half 0xH3E00 buf[0] = min( buf2[0], 1.5f ); -// CHECK: float noundef 1.500000e+00 +// CHECK: float 1.500000e+00 const half one = 1.6666; buf[1] = min( buf[1], one ); -// CHECK: half noundef 0xH3EAB +// CHECK: half 0xH3EAB } diff --git a/clang/test/CodeGenOpenCL/kernel-param-alignment.cl b/clang/test/CodeGenOpenCL/kernel-param-alignment.cl --- a/clang/test/CodeGenOpenCL/kernel-param-alignment.cl +++ b/clang/test/CodeGenOpenCL/kernel-param-alignment.cl @@ -17,10 +17,10 @@ global void *v, global struct packed *p) { // CHECK-LABEL: spir_kernel void @test( -// CHECK-SAME: i32* nocapture noundef align 4 %i32, -// CHECK-SAME: i64* nocapture noundef align 8 %i64, -// CHECK-SAME: <4 x i32>* nocapture noundef align 16 %v4i32, -// CHECK-SAME: <2 x float>* nocapture noundef align 8 %v2f32, -// CHECK-SAME: i8* nocapture noundef %v, -// CHECK-SAME: %struct.packed* nocapture noundef align 1 %p) +// CHECK-SAME: i32* nocapture align 4 %i32, +// CHECK-SAME: i64* nocapture align 8 %i64, +// CHECK-SAME: <4 x i32>* nocapture align 16 %v4i32, +// CHECK-SAME: <2 x float>* nocapture align 8 %v2f32, +// CHECK-SAME: i8* nocapture %v, +// CHECK-SAME: %struct.packed* nocapture align 1 %p) } diff --git a/clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl b/clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl --- a/clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl +++ b/clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl @@ -28,7 +28,7 @@ // CHECK: spir_kernel // AMDGCN: define{{.*}} amdgpu_kernel void @test_single // CHECK: struct.int_single* nocapture {{.*}} byval(%struct.int_single) -// CHECK: i32* nocapture noundef writeonly align 4 %output +// CHECK: i32* nocapture writeonly align 4 %output output[0] = input.a; } @@ -36,7 +36,7 @@ // CHECK: spir_kernel // AMDGCN: define{{.*}} amdgpu_kernel void @test_pair // CHECK: struct.int_pair* nocapture {{.*}} byval(%struct.int_pair) -// CHECK: i32* nocapture noundef writeonly align 4 %output +// CHECK: i32* nocapture writeonly align 4 %output output[0] = (int)input.a; output[1] = (int)input.b; } @@ -45,7 +45,7 @@ // CHECK: spir_kernel // AMDGCN: define{{.*}} amdgpu_kernel void @test_kernel // CHECK: struct.test_struct* nocapture {{.*}} byval(%struct.test_struct) -// CHECK: i32* nocapture noundef writeonly align 4 %output +// CHECK: i32* nocapture writeonly align 4 %output output[0] = input.elementA; output[1] = input.elementB; output[2] = (int)input.elementC; @@ -59,7 +59,7 @@ void test_function(int_pair input, global int* output) { // CHECK-NOT: spir_kernel // AMDGCN-NOT: define{{.*}} amdgpu_kernel void @test_function -// CHECK: i64 %input.coerce0, i64 %input.coerce1, i32* nocapture noundef writeonly %output +// CHECK: i64 %input.coerce0, i64 %input.coerce1, i32* nocapture writeonly %output output[0] = (int)input.a; output[1] = (int)input.b; } diff --git a/clang/test/CodeGenOpenCL/no-half.cl b/clang/test/CodeGenOpenCL/no-half.cl --- a/clang/test/CodeGenOpenCL/no-half.cl +++ b/clang/test/CodeGenOpenCL/no-half.cl @@ -4,7 +4,7 @@ #pragma OPENCL EXTENSION cl_khr_fp64:enable -// CHECK-LABEL: @test_store_float(float noundef %foo, half addrspace({{.}}){{.*}} %bar) +// CHECK-LABEL: @test_store_float(float %foo, half addrspace({{.}}){{.*}} %bar) __kernel void test_store_float(float foo, __global half* bar) { __builtin_store_halff(foo, bar); @@ -12,7 +12,7 @@ // CHECK: store half [[HALF_VAL]], half addrspace({{.}})* %bar, align 2 } -// CHECK-LABEL: @test_store_double(double noundef %foo, half addrspace({{.}}){{.*}} %bar) +// CHECK-LABEL: @test_store_double(double %foo, half addrspace({{.}}){{.*}} %bar) __kernel void test_store_double(double foo, __global half* bar) { __builtin_store_half(foo, bar); diff --git a/clang/test/CodeGenOpenCL/overload.cl b/clang/test/CodeGenOpenCL/overload.cl --- a/clang/test/CodeGenOpenCL/overload.cl +++ b/clang/test/CodeGenOpenCL/overload.cl @@ -3,9 +3,9 @@ typedef short short4 __attribute__((ext_vector_type(4))); -// CHECK-DAG: declare spir_func <4 x i16> @_Z5clampDv4_sS_S_(<4 x i16> noundef, <4 x i16> noundef, <4 x i16> noundef) +// CHECK-DAG: declare spir_func <4 x i16> @_Z5clampDv4_sS_S_(<4 x i16>, <4 x i16>, <4 x i16>) short4 __attribute__ ((overloadable)) clamp(short4 x, short4 minval, short4 maxval); -// CHECK-DAG: declare spir_func <4 x i16> @_Z5clampDv4_sss(<4 x i16> noundef, i16 noundef signext, i16 noundef signext) +// CHECK-DAG: declare spir_func <4 x i16> @_Z5clampDv4_sss(<4 x i16>, i16 signext, i16 signext) short4 __attribute__ ((overloadable)) clamp(short4 x, short minval, short maxval); void __attribute__((overloadable)) foo(global int *a, global int *b); void __attribute__((overloadable)) foo(generic int *a, generic int *b); @@ -21,18 +21,18 @@ generic int *generic *gengen; generic int *local *genloc; generic int *global *genglob; - // CHECK-DAG: call spir_func void @_Z3fooPU3AS1iS0_(i32 addrspace(1)* noundef undef, i32 addrspace(1)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3fooPU3AS1iS0_(i32 addrspace(1)* undef, i32 addrspace(1)* undef) foo(a, b); - // CHECK-DAG: call spir_func void @_Z3fooPU3AS4iS0_(i32 addrspace(4)* noundef undef, i32 addrspace(4)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3fooPU3AS4iS0_(i32 addrspace(4)* undef, i32 addrspace(4)* undef) foo(b, c); - // CHECK-DAG: call spir_func void @_Z3fooPU3AS4iS0_(i32 addrspace(4)* noundef undef, i32 addrspace(4)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3fooPU3AS4iS0_(i32 addrspace(4)* undef, i32 addrspace(4)* undef) foo(a, d); - // CHECK-DAG: call spir_func void @_Z3barPU3AS4PU3AS4iS2_(i32 addrspace(4)* addrspace(4)* noundef undef, i32 addrspace(4)* addrspace(4)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3barPU3AS4PU3AS4iS2_(i32 addrspace(4)* addrspace(4)* undef, i32 addrspace(4)* addrspace(4)* undef) bar(gengen, genloc); - // CHECK-DAG: call spir_func void @_Z3barPU3AS4PU3AS4iS2_(i32 addrspace(4)* addrspace(4)* noundef undef, i32 addrspace(4)* addrspace(4)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3barPU3AS4PU3AS4iS2_(i32 addrspace(4)* addrspace(4)* undef, i32 addrspace(4)* addrspace(4)* undef) bar(gengen, genglob); - // CHECK-DAG: call spir_func void @_Z3barPU3AS1PU3AS4iS2_(i32 addrspace(4)* addrspace(1)* noundef undef, i32 addrspace(4)* addrspace(1)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3barPU3AS1PU3AS4iS2_(i32 addrspace(4)* addrspace(1)* undef, i32 addrspace(4)* addrspace(1)* undef) bar(genglob, genglob); } @@ -40,8 +40,8 @@ void kernel test2() { short4 e0=0; - // CHECK-DAG: call spir_func <4 x i16> @_Z5clampDv4_sss(<4 x i16> noundef zeroinitializer, i16 noundef signext 0, i16 noundef signext 255) + // CHECK-DAG: call spir_func <4 x i16> @_Z5clampDv4_sss(<4 x i16> zeroinitializer, i16 signext 0, i16 signext 255) clamp(e0, 0, 255); - // CHECK-DAG: call spir_func <4 x i16> @_Z5clampDv4_sS_S_(<4 x i16> noundef zeroinitializer, <4 x i16> noundef zeroinitializer, <4 x i16> noundef zeroinitializer) + // CHECK-DAG: call spir_func <4 x i16> @_Z5clampDv4_sS_S_(<4 x i16> zeroinitializer, <4 x i16> zeroinitializer, <4 x i16> zeroinitializer) clamp(e0, e0, e0); } diff --git a/clang/test/CodeGenOpenCL/size_t.cl b/clang/test/CodeGenOpenCL/size_t.cl --- a/clang/test/CodeGenOpenCL/size_t.cl +++ b/clang/test/CodeGenOpenCL/size_t.cl @@ -3,74 +3,74 @@ // RUN: %clang_cc1 -no-opaque-pointers %s -cl-std=CL2.0 -finclude-default-header -fdeclare-opencl-builtins -emit-llvm -O0 -triple amdgcn -o - | FileCheck --check-prefix=SZ64 --check-prefix=AMDGCN %s // RUN: %clang_cc1 -no-opaque-pointers %s -cl-std=CL2.0 -finclude-default-header -fdeclare-opencl-builtins -emit-llvm -O0 -triple amdgcn---opencl -o - | FileCheck --check-prefix=SZ64 --check-prefix=AMDGCN %s -//SZ32: define{{.*}} i32 @test_ptrtoint_private(i8* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_private(i8* %x) //SZ32: ptrtoint i8* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_private(i8* noundef %x) +//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_private(i8* %x) //SZ64ONLY: ptrtoint i8* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_ptrtoint_private(i8 addrspace(5)* noundef %x) +//AMDGCN: define{{.*}} i64 @test_ptrtoint_private(i8 addrspace(5)* %x) //AMDGCN: ptrtoint i8 addrspace(5)* %{{.*}} to i64 size_t test_ptrtoint_private(private char* x) { return (size_t)x; } -//SZ32: define{{.*}} i32 @test_ptrtoint_global(i8 addrspace(1)* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_global(i8 addrspace(1)* %x) //SZ32: ptrtoint i8 addrspace(1)* %{{.*}} to i32 -//SZ64: define{{.*}} i64 @test_ptrtoint_global(i8 addrspace(1)* noundef %x) +//SZ64: define{{.*}} i64 @test_ptrtoint_global(i8 addrspace(1)* %x) //SZ64: ptrtoint i8 addrspace(1)* %{{.*}} to i64 intptr_t test_ptrtoint_global(global char* x) { return (intptr_t)x; } -//SZ32: define{{.*}} i32 @test_ptrtoint_constant(i8 addrspace(2)* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_constant(i8 addrspace(2)* %x) //SZ32: ptrtoint i8 addrspace(2)* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_constant(i8 addrspace(2)* noundef %x) +//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_constant(i8 addrspace(2)* %x) //SZ64ONLY: ptrtoint i8 addrspace(2)* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_ptrtoint_constant(i8 addrspace(4)* noundef %x) +//AMDGCN: define{{.*}} i64 @test_ptrtoint_constant(i8 addrspace(4)* %x) //AMDGCN: ptrtoint i8 addrspace(4)* %{{.*}} to i64 uintptr_t test_ptrtoint_constant(constant char* x) { return (uintptr_t)x; } -//SZ32: define{{.*}} i32 @test_ptrtoint_local(i8 addrspace(3)* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_local(i8 addrspace(3)* %x) //SZ32: ptrtoint i8 addrspace(3)* %{{.*}} to i32 -//SZ64: define{{.*}} i64 @test_ptrtoint_local(i8 addrspace(3)* noundef %x) +//SZ64: define{{.*}} i64 @test_ptrtoint_local(i8 addrspace(3)* %x) //SZ64: ptrtoint i8 addrspace(3)* %{{.*}} to i64 size_t test_ptrtoint_local(local char* x) { return (size_t)x; } -//SZ32: define{{.*}} i32 @test_ptrtoint_generic(i8 addrspace(4)* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_generic(i8 addrspace(4)* %x) //SZ32: ptrtoint i8 addrspace(4)* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_generic(i8 addrspace(4)* noundef %x) +//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_generic(i8 addrspace(4)* %x) //SZ64ONLY: ptrtoint i8 addrspace(4)* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_ptrtoint_generic(i8* noundef %x) +//AMDGCN: define{{.*}} i64 @test_ptrtoint_generic(i8* %x) //AMDGCN: ptrtoint i8* %{{.*}} to i64 size_t test_ptrtoint_generic(generic char* x) { return (size_t)x; } -//SZ32: define{{.*}} i8* @test_inttoptr_private(i32 noundef %x) +//SZ32: define{{.*}} i8* @test_inttoptr_private(i32 %x) //SZ32: inttoptr i32 %{{.*}} to i8* -//SZ64ONLY: define{{.*}} i8* @test_inttoptr_private(i64 noundef %x) +//SZ64ONLY: define{{.*}} i8* @test_inttoptr_private(i64 %x) //SZ64ONLY: inttoptr i64 %{{.*}} to i8* -//AMDGCN: define{{.*}} i8 addrspace(5)* @test_inttoptr_private(i64 noundef %x) +//AMDGCN: define{{.*}} i8 addrspace(5)* @test_inttoptr_private(i64 %x) //AMDGCN: trunc i64 %{{.*}} to i32 //AMDGCN: inttoptr i32 %{{.*}} to i8 addrspace(5)* private char* test_inttoptr_private(size_t x) { return (private char*)x; } -//SZ32: define{{.*}} i8 addrspace(1)* @test_inttoptr_global(i32 noundef %x) +//SZ32: define{{.*}} i8 addrspace(1)* @test_inttoptr_global(i32 %x) //SZ32: inttoptr i32 %{{.*}} to i8 addrspace(1)* -//SZ64: define{{.*}} i8 addrspace(1)* @test_inttoptr_global(i64 noundef %x) +//SZ64: define{{.*}} i8 addrspace(1)* @test_inttoptr_global(i64 %x) //SZ64: inttoptr i64 %{{.*}} to i8 addrspace(1)* global char* test_inttoptr_global(size_t x) { return (global char*)x; } -//SZ32: define{{.*}} i8 addrspace(3)* @test_add_local(i8 addrspace(3)* noundef %x, i32 noundef %y) +//SZ32: define{{.*}} i8 addrspace(3)* @test_add_local(i8 addrspace(3)* %x, i32 %y) //SZ32: getelementptr inbounds i8, i8 addrspace(3)* %{{.*}}, i32 -//SZ64: define{{.*}} i8 addrspace(3)* @test_add_local(i8 addrspace(3)* noundef %x, i64 noundef %y) +//SZ64: define{{.*}} i8 addrspace(3)* @test_add_local(i8 addrspace(3)* %x, i64 %y) //AMDGCN: trunc i64 %{{.*}} to i32 //AMDGCN: getelementptr inbounds i8, i8 addrspace(3)* %{{.*}}, i32 //SZ64ONLY: getelementptr inbounds i8, i8 addrspace(3)* %{{.*}}, i64 @@ -78,44 +78,44 @@ return x + y; } -//SZ32: define{{.*}} i8 addrspace(1)* @test_add_global(i8 addrspace(1)* noundef %x, i32 noundef %y) +//SZ32: define{{.*}} i8 addrspace(1)* @test_add_global(i8 addrspace(1)* %x, i32 %y) //SZ32: getelementptr inbounds i8, i8 addrspace(1)* %{{.*}}, i32 -//SZ64: define{{.*}} i8 addrspace(1)* @test_add_global(i8 addrspace(1)* noundef %x, i64 noundef %y) +//SZ64: define{{.*}} i8 addrspace(1)* @test_add_global(i8 addrspace(1)* %x, i64 %y) //SZ64: getelementptr inbounds i8, i8 addrspace(1)* %{{.*}}, i64 global char* test_add_global(global char* x, ptrdiff_t y) { return x + y; } -//SZ32: define{{.*}} i32 @test_sub_local(i8 addrspace(3)* noundef %x, i8 addrspace(3)* noundef %y) +//SZ32: define{{.*}} i32 @test_sub_local(i8 addrspace(3)* %x, i8 addrspace(3)* %y) //SZ32: ptrtoint i8 addrspace(3)* %{{.*}} to i32 //SZ32: ptrtoint i8 addrspace(3)* %{{.*}} to i32 -//SZ64: define{{.*}} i64 @test_sub_local(i8 addrspace(3)* noundef %x, i8 addrspace(3)* noundef %y) +//SZ64: define{{.*}} i64 @test_sub_local(i8 addrspace(3)* %x, i8 addrspace(3)* %y) //SZ64: ptrtoint i8 addrspace(3)* %{{.*}} to i64 //SZ64: ptrtoint i8 addrspace(3)* %{{.*}} to i64 ptrdiff_t test_sub_local(local char* x, local char *y) { return x - y; } -//SZ32: define{{.*}} i32 @test_sub_private(i8* noundef %x, i8* noundef %y) +//SZ32: define{{.*}} i32 @test_sub_private(i8* %x, i8* %y) //SZ32: ptrtoint i8* %{{.*}} to i32 //SZ32: ptrtoint i8* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_sub_private(i8* noundef %x, i8* noundef %y) +//SZ64ONLY: define{{.*}} i64 @test_sub_private(i8* %x, i8* %y) //SZ64ONLY: ptrtoint i8* %{{.*}} to i64 //SZ64ONLY: ptrtoint i8* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_sub_private(i8 addrspace(5)* noundef %x, i8 addrspace(5)* noundef %y) +//AMDGCN: define{{.*}} i64 @test_sub_private(i8 addrspace(5)* %x, i8 addrspace(5)* %y) //AMDGCN: ptrtoint i8 addrspace(5)* %{{.*}} to i64 //AMDGCN: ptrtoint i8 addrspace(5)* %{{.*}} to i64 ptrdiff_t test_sub_private(private char* x, private char *y) { return x - y; } -//SZ32: define{{.*}} i32 @test_sub_mix(i8* noundef %x, i8 addrspace(4)* noundef %y) +//SZ32: define{{.*}} i32 @test_sub_mix(i8* %x, i8 addrspace(4)* %y) //SZ32: ptrtoint i8* %{{.*}} to i32 //SZ32: ptrtoint i8 addrspace(4)* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_sub_mix(i8* noundef %x, i8 addrspace(4)* noundef %y) +//SZ64ONLY: define{{.*}} i64 @test_sub_mix(i8* %x, i8 addrspace(4)* %y) //SZ64ONLY: ptrtoint i8* %{{.*}} to i64 //SZ64ONLY: ptrtoint i8 addrspace(4)* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_sub_mix(i8 addrspace(5)* noundef %x, i8* noundef %y) +//AMDGCN: define{{.*}} i64 @test_sub_mix(i8 addrspace(5)* %x, i8* %y) //AMDGCN: ptrtoint i8 addrspace(5)* %{{.*}} to i64 //AMDGCN: ptrtoint i8* %{{.*}} to i64 ptrdiff_t test_sub_mix(private char* x, generic char *y) { diff --git a/clang/test/CodeGenOpenCL/spir-calling-conv.cl b/clang/test/CodeGenOpenCL/spir-calling-conv.cl --- a/clang/test/CodeGenOpenCL/spir-calling-conv.cl +++ b/clang/test/CodeGenOpenCL/spir-calling-conv.cl @@ -5,14 +5,14 @@ kernel void bar(global int *A); kernel void foo(global int *A) -// CHECK: define{{.*}} spir_kernel void @foo(i32 addrspace(1)* noundef align 4 %A) +// CHECK: define{{.*}} spir_kernel void @foo(i32 addrspace(1)* align 4 %A) { int id = get_dummy_id(0); - // CHECK: %{{[a-z0-9_]+}} = tail call spir_func i32 @get_dummy_id(i32 noundef 0) + // CHECK: %{{[a-z0-9_]+}} = tail call spir_func i32 @get_dummy_id(i32 0) A[id] = id; bar(A); - // CHECK: tail call spir_kernel void @bar(i32 addrspace(1)* noundef align 4 %A) + // CHECK: tail call spir_kernel void @bar(i32 addrspace(1)* align 4 %A) } -// CHECK: declare spir_func i32 @get_dummy_id(i32 noundef) -// CHECK: declare spir_kernel void @bar(i32 addrspace(1)* noundef align 4) +// CHECK: declare spir_func i32 @get_dummy_id(i32) +// CHECK: declare spir_kernel void @bar(i32 addrspace(1)* align 4) diff --git a/clang/test/CodeGenOpenCLCXX/address-space-deduction.clcpp b/clang/test/CodeGenOpenCLCXX/address-space-deduction.clcpp --- a/clang/test/CodeGenOpenCLCXX/address-space-deduction.clcpp +++ b/clang/test/CodeGenOpenCLCXX/address-space-deduction.clcpp @@ -21,7 +21,7 @@ //COMMON: @loc_ext_p = external addrspace(1) {{global|constant}} i32 addrspace(4)* //COMMON: @loc_ext = external addrspace(1) global i32 -//COMMON: define{{.*}} spir_func noundef i32 @_Z3fooi{{P|R}}U3AS4i(i32 noundef %par, i32 addrspace(4)*{{.*}} %par_p) +//COMMON: define{{.*}} spir_func i32 @_Z3fooi{{P|R}}U3AS4i(i32 %par, i32 addrspace(4)*{{.*}} %par_p) int foo(int par, int PTR par_p){ //COMMON: %loc = alloca i32 int loc; diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-derived-base.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-derived-base.clcpp --- a/clang/test/CodeGenOpenCLCXX/addrspace-derived-base.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-derived-base.clcpp @@ -13,13 +13,13 @@ D d; //CHECK-LABEL: foo //CHECK: addrspacecast %class.D* %d to %class.D addrspace(4)* - //CHECK: call spir_func noundef i32 @_ZNU3AS41D5getmbEv(%class.D addrspace(4)* + //CHECK: call spir_func i32 @_ZNU3AS41D5getmbEv(%class.D addrspace(4)* d.getmb(); } //Derived and Base are in the same address space. -//CHECK: define linkonce_odr spir_func noundef i32 @_ZNU3AS41D5getmbEv(%class.D addrspace(4)* {{[^,]*}} %this) +//CHECK: define linkonce_odr spir_func i32 @_ZNU3AS41D5getmbEv(%class.D addrspace(4)* {{[^,]*}} %this) //CHECK: bitcast %class.D addrspace(4)* %this1 to %struct.B addrspace(4)* diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-new-delete.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-new-delete.clcpp --- a/clang/test/CodeGenOpenCLCXX/addrspace-new-delete.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-new-delete.clcpp @@ -9,7 +9,7 @@ }; void test_new_delete(A **a) { -// CHECK: %{{.*}} = call spir_func noundef i8 addrspace(4)* @_ZNU3AS41AnwEj(i32 {{.*}}) +// CHECK: %{{.*}} = call spir_func i8 addrspace(4)* @_ZNU3AS41AnwEj(i32 {{.*}}) *a = new A; // CHECK: call spir_func void @_ZNU3AS41AdlEPU3AS4v(i8 addrspace(4)* {{.*}}) delete *a; diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp --- a/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp @@ -86,18 +86,18 @@ // COMMON-LABEL: @test__global() // Test the address space of 'this' when invoking a method. -// COMMON: call spir_func noundef i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) +// COMMON: call spir_func i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking a method using a pointer to the object. -// COMMON: call spir_func noundef i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) +// COMMON: call spir_func i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking a method that is declared in the file contex. -// COMMON: call spir_func noundef i32 @_ZNU3AS41C7outsideEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) +// COMMON: call spir_func i32 @_ZNU3AS41C7outsideEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking copy-constructor. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // IMPL: [[C1VOID:%[0-9]+]] = bitcast %class.C* %c1 to i8* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C1VOID]], i8 addrspace(4)* {{.*}}addrspacecast (i8 addrspace(1)* bitcast (%class.C addrspace(1)* @c to i8 addrspace(1)*) to i8 addrspace(4)*) -// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) +// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking a constructor. // EXPL: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* @@ -106,7 +106,7 @@ // Test the address space of 'this' when invoking assignment operator. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* -// EXPL: call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[C1GEN]]) +// EXPL: call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[C1GEN]]) // IMPL: [[C2GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C2GEN]] to i8 addrspace(4)* // IMPL: [[C1GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C1GEN]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p4i8.p4i8.i32(i8 addrspace(4)* {{.*}}[[C2GENVOID]], i8 addrspace(4)* {{.*}}[[C1GENVOID]] @@ -114,20 +114,20 @@ // Test the address space of 'this' when invoking the operator+ // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* -// COMMON: call spir_func void @_ZNU3AS41CplERU3AS4KS_(%class.C* sret(%class.C) align 4 %c3, %class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[C2GEN]]) +// COMMON: call spir_func void @_ZNU3AS41CplERU3AS4KS_(%class.C* sret(%class.C) align 4 %c3, %class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[C2GEN]]) // Test the address space of 'this' when invoking the move constructor // COMMON: [[C4GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c4 to %class.C addrspace(4)* -// COMMON: [[CALL:%call[0-9]+]] = call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_Z3foov() -// EXPL: call spir_func void @_ZNU3AS41CC1EOU3AS4S_(%class.C addrspace(4)* {{[^,]*}} [[C4GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[CALL]]) +// COMMON: [[CALL:%call[0-9]+]] = call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_Z3foov() +// EXPL: call spir_func void @_ZNU3AS41CC1EOU3AS4S_(%class.C addrspace(4)* {{[^,]*}} [[C4GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[CALL]]) // IMPL: [[C4VOID:%[0-9]+]] = bitcast %class.C* %c4 to i8* // IMPL: [[CALLVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[CALL]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C4VOID]], i8 addrspace(4)* {{.*}}[[CALLVOID]] // Test the address space of 'this' when invoking the move assignment // COMMON: [[C5GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c5 to %class.C addrspace(4)* -// COMMON: [[CALL:%call[0-9]+]] = call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_Z3foov() -// EXPL: call spir_func void @_ZNU3AS41CC1EOU3AS4S_(%class.C addrspace(4)* {{[^,]*}} [[C5GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[CALL]]) +// COMMON: [[CALL:%call[0-9]+]] = call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_Z3foov() +// EXPL: call spir_func void @_ZNU3AS41CC1EOU3AS4S_(%class.C addrspace(4)* {{[^,]*}} [[C5GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[CALL]]) // IMPL: [[C5VOID:%[0-9]+]] = bitcast %class.C* %c5 to i8* // IMPL: [[CALLVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[CALL]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C5VOID]], i8 addrspace(4)* {{.*}}[[CALLVOID]] @@ -152,11 +152,11 @@ // EXPL-NOT: call spir_func void @_ZNU3AS41CC1Ev(%class.C addrspace(4)* addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking a method. -// COMMON: call spir_func noundef i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) +// COMMON: call spir_func i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking copy-constructor. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* -// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) +// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) // IMPL: [[C1VOID:%[0-9]+]] = bitcast %class.C* %c1 to i8* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C1VOID]], i8 addrspace(4)* {{.*}}addrspacecast (i8 addrspace(3)* bitcast (%class.C addrspace(3)* @_ZZ11test__localE1c to i8 addrspace(3)*) to i8 addrspace(4)*), i32 4, i1 false) @@ -167,7 +167,7 @@ // Test the address space of 'this' when invoking assignment operator. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* -// EXPL: call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[C1GEN]]) +// EXPL: call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[C1GEN]]) // IMPL: [[C2GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C2GEN]] to i8 addrspace(4)* // IMPL: [[C1GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C1GEN]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p4i8.p4i8.i32(i8 addrspace(4)* {{.*}}[[C2GENVOID]], i8 addrspace(4)* {{.*}}[[C1GENVOID]] @@ -182,12 +182,12 @@ // Test the address space of 'this' when invoking a method. // COMMON: [[CGEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c to %class.C addrspace(4)* -// COMMON: call spir_func noundef i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} [[CGEN]]) +// COMMON: call spir_func i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} [[CGEN]]) // Test the address space of 'this' when invoking a copy-constructor. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[CGEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c to %class.C addrspace(4)* -// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[CGEN]]) +// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[CGEN]]) // IMPL: [[C1VOID:%[0-9]+]] = bitcast %class.C* %c1 to i8* // IMPL: [[CGENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[CGEN]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C1VOID]], i8 addrspace(4)* {{.*}}[[CGENVOID]] @@ -199,7 +199,7 @@ // Test the address space of 'this' when invoking a copy-assignment. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* -// EXPL: call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[C1GEN]]) +// EXPL: call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[C1GEN]]) // IMPL: [[C2GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C2GEN]] to i8 addrspace(4)* // IMPL: [[C1GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C1GEN]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p4i8.p4i8.i32(i8 addrspace(4)* {{.*}}[[C2GENVOID]], i8 addrspace(4)* {{.*}}[[C1GENVOID]] diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp --- a/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp @@ -20,10 +20,10 @@ void bar() { C c; //CHECK: [[A1:%[.a-z0-9]+]] ={{.*}} addrspacecast %class.C* [[C:%[a-z0-9]+]] to %class.C addrspace(4)* - //CHECK: call spir_func void @_ZNU3AS41C6AssignE1E(%class.C addrspace(4)* {{[^,]*}} [[A1]], i32 noundef 0) + //CHECK: call spir_func void @_ZNU3AS41C6AssignE1E(%class.C addrspace(4)* {{[^,]*}} [[A1]], i32 0) c.Assign(a); //CHECK: [[A2:%[.a-z0-9]+]] ={{.*}} addrspacecast %class.C* [[C]] to %class.C addrspace(4)* - //CHECK: call spir_func void @_ZNU3AS41C8OrAssignE1E(%class.C addrspace(4)* {{[^,]*}} [[A2]], i32 noundef 0) + //CHECK: call spir_func void @_ZNU3AS41C8OrAssignE1E(%class.C addrspace(4)* {{[^,]*}} [[A2]], i32 0) c.OrAssign(a); E e; diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-references.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-references.clcpp --- a/clang/test/CodeGenOpenCLCXX/addrspace-references.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-references.clcpp @@ -17,7 +17,7 @@ // CHECK: [[REF:%.*]] = alloca i32 // CHECK: store i32 1, i32* [[REF]] // CHECK: [[REG:%[.a-z0-9]+]] ={{.*}} addrspacecast i32* [[REF]] to i32 addrspace(4)* - // CHECK: call spir_func noundef i32 @_Z3barRU3AS4Kj(i32 addrspace(4)* noundef align 4 dereferenceable(4) [[REG]]) + // CHECK: call spir_func i32 @_Z3barRU3AS4Kj(i32 addrspace(4)* align 4 dereferenceable(4) [[REG]]) bar(1); } diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-with-class.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-with-class.clcpp --- a/clang/test/CodeGenOpenCLCXX/addrspace-with-class.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-with-class.clcpp @@ -23,15 +23,15 @@ // CHECK: @glob ={{.*}} addrspace(1) global %struct.MyType zeroinitializer MyType glob(1); -// CHECK: call spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} @const1, i32 noundef 1) -// CHECK: call spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} @const2, i32 noundef 2) -// CHECK: call spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} addrspacecast (%struct.MyType addrspace(1)* @glob to %struct.MyType addrspace(4)*), i32 noundef 1) +// CHECK: call spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} @const1, i32 1) +// CHECK: call spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} @const2, i32 2) +// CHECK: call spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} addrspacecast (%struct.MyType addrspace(1)* @glob to %struct.MyType addrspace(4)*), i32 1) // CHECK-LABEL: define{{.*}} spir_kernel void @fooGlobal() kernel void fooGlobal() { - // CHECK: call spir_func noundef i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} addrspacecast (%struct.MyType addrspace(1)* @glob to %struct.MyType addrspace(4)*)) + // CHECK: call spir_func i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} addrspacecast (%struct.MyType addrspace(1)* @glob to %struct.MyType addrspace(4)*)) glob.bar(); - // CHECK: call spir_func noundef i32 @_ZNU3AS26MyType3barEv(%struct.MyType addrspace(2)* {{[^,]*}} @const1) + // CHECK: call spir_func i32 @_ZNU3AS26MyType3barEv(%struct.MyType addrspace(2)* {{[^,]*}} @const1) const1.bar(); // CHECK: call spir_func void @_ZNU3AS26MyTypeD1Ev(%struct.MyType addrspace(2)* {{[^,]*}} @const1) const1.~MyType(); @@ -41,19 +41,19 @@ kernel void fooLocal() { // CHECK: [[VAR:%.*]] = alloca %struct.MyType // CHECK: [[REG:%.*]] ={{.*}} addrspacecast %struct.MyType* [[VAR]] to %struct.MyType addrspace(4)* - // CHECK: call spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]], i32 noundef 3) + // CHECK: call spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]], i32 3) MyType myLocal(3); // CHECK: [[REG:%.*]] ={{.*}} addrspacecast %struct.MyType* [[VAR]] to %struct.MyType addrspace(4)* - // CHECK: call spir_func noundef i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]]) + // CHECK: call spir_func i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]]) myLocal.bar(); // CHECK: [[REG:%.*]] ={{.*}} addrspacecast %struct.MyType* [[VAR]] to %struct.MyType addrspace(4)* // CHECK: call spir_func void @_ZNU3AS46MyTypeD1Ev(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]]) } // Ensure all members are defined for all the required address spaces. -// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} %this, i32 noundef %i) -// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} %this, i32 noundef %i) +// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} %this, i32 %i) +// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} %this, i32 %i) // CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS26MyTypeD1Ev(%struct.MyType addrspace(2)* {{[^,]*}} %this) // CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS46MyTypeD1Ev(%struct.MyType addrspace(4)* {{[^,]*}} %this) -// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func noundef i32 @_ZNU3AS26MyType3barEv(%struct.MyType addrspace(2)* {{[^,]*}} %this) -// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func noundef i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} %this) +// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func i32 @_ZNU3AS26MyType3barEv(%struct.MyType addrspace(2)* {{[^,]*}} %this) +// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} %this) diff --git a/clang/test/CodeGenOpenCLCXX/template-address-spaces.clcpp b/clang/test/CodeGenOpenCLCXX/template-address-spaces.clcpp --- a/clang/test/CodeGenOpenCLCXX/template-address-spaces.clcpp +++ b/clang/test/CodeGenOpenCLCXX/template-address-spaces.clcpp @@ -14,11 +14,11 @@ // CHECK: %struct.S.1 = type { i32 addrspace(1)* } // CHECK: [[A1:%[.a-z0-9]+]] = addrspacecast %struct.S* %{{[a-z0-9]+}} to %struct.S addrspace(4)* -// CHECK: %call = call spir_func noundef i32 @_ZNU3AS41SIiE3fooEv(%struct.S addrspace(4)* {{[^,]*}} [[A1]]) #1 +// CHECK: %call = call spir_func i32 @_ZNU3AS41SIiE3fooEv(%struct.S addrspace(4)* {{[^,]*}} [[A1]]) #1 // CHECK: [[A2:%[.a-z0-9]+]] = addrspacecast %struct.S.0* %{{[a-z0-9]+}} to %struct.S.0 addrspace(4)* -// CHECK: %call1 = call spir_func noundef i32 addrspace(4)* @_ZNU3AS41SIPU3AS4iE3fooEv(%struct.S.0 addrspace(4)* {{[^,]*}} [[A2]]) #1 +// CHECK: %call1 = call spir_func i32 addrspace(4)* @_ZNU3AS41SIPU3AS4iE3fooEv(%struct.S.0 addrspace(4)* {{[^,]*}} [[A2]]) #1 // CHECK: [[A3:%[.a-z0-9]+]] = addrspacecast %struct.S.1* %{{[a-z0-9]+}} to %struct.S.1 addrspace(4)* -// CHECK: %call2 = call spir_func noundef i32 addrspace(1)* @_ZNU3AS41SIPU3AS1iE3fooEv(%struct.S.1 addrspace(4)* {{[^,]*}} [[A3]]) #1 +// CHECK: %call2 = call spir_func i32 addrspace(1)* @_ZNU3AS41SIPU3AS1iE3fooEv(%struct.S.1 addrspace(4)* {{[^,]*}} [[A3]]) #1 void bar(){ S sint; diff --git a/clang/test/CodeGenSYCL/address-space-conversions.cpp b/clang/test/CodeGenSYCL/address-space-conversions.cpp --- a/clang/test/CodeGenSYCL/address-space-conversions.cpp +++ b/clang/test/CodeGenSYCL/address-space-conversions.cpp @@ -1,16 +1,16 @@ // RUN: %clang_cc1 -no-opaque-pointers -triple spir64 -fsycl-is-device -disable-llvm-passes -emit-llvm %s -o - | FileCheck %s void bar(int &Data) {} -// CHECK-DAG: define{{.*}} spir_func void @[[RAW_REF:[a-zA-Z0-9_]+]](i32 addrspace(4)* noundef align 4 dereferenceable(4) % +// CHECK-DAG: define{{.*}} spir_func void @[[RAW_REF:[a-zA-Z0-9_]+]](i32 addrspace(4)* align 4 dereferenceable(4) % void bar2(int &Data) {} -// CHECK-DAG: define{{.*}} spir_func void @[[RAW_REF2:[a-zA-Z0-9_]+]](i32 addrspace(4)* noundef align 4 dereferenceable(4) % +// CHECK-DAG: define{{.*}} spir_func void @[[RAW_REF2:[a-zA-Z0-9_]+]](i32 addrspace(4)* align 4 dereferenceable(4) % void bar(__attribute__((opencl_local)) int &Data) {} -// CHECK-DAG: define{{.*}} spir_func void [[LOC_REF:@[a-zA-Z0-9_]+]](i32 addrspace(3)* noundef align 4 dereferenceable(4) % +// CHECK-DAG: define{{.*}} spir_func void [[LOC_REF:@[a-zA-Z0-9_]+]](i32 addrspace(3)* align 4 dereferenceable(4) % void foo(int *Data) {} -// CHECK-DAG: define{{.*}} spir_func void @[[RAW_PTR:[a-zA-Z0-9_]+]](i32 addrspace(4)* noundef % +// CHECK-DAG: define{{.*}} spir_func void @[[RAW_PTR:[a-zA-Z0-9_]+]](i32 addrspace(4)* % void foo2(int *Data) {} -// CHECK-DAG: define{{.*}} spir_func void @[[RAW_PTR2:[a-zA-Z0-9_]+]](i32 addrspace(4)* noundef % +// CHECK-DAG: define{{.*}} spir_func void @[[RAW_PTR2:[a-zA-Z0-9_]+]](i32 addrspace(4)* % void foo(__attribute__((opencl_local)) int *Data) {} -// CHECK-DAG: define{{.*}} spir_func void [[LOC_PTR:@[a-zA-Z0-9_]+]](i32 addrspace(3)* noundef % +// CHECK-DAG: define{{.*}} spir_func void [[LOC_PTR:@[a-zA-Z0-9_]+]](i32 addrspace(3)* % template void tmpl(T t) {} @@ -74,65 +74,65 @@ bar(*GLOB); // CHECK-DAG: [[GLOB_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast // CHECK-DAG: [[GLOB_CAST:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[GLOB_CAST]]) + // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOB_CAST]]) bar2(*GLOB); // CHECK-DAG: [[GLOB_LOAD2:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast // CHECK-DAG: [[GLOB_CAST2:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD2]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[GLOB_CAST2]]) + // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOB_CAST2]]) bar(*LOC); // CHECK-DAG: [[LOC_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast - // CHECK-DAG: call spir_func void [[LOC_REF]](i32 addrspace(3)* noundef align 4 dereferenceable(4) [[LOC_LOAD]]) + // CHECK-DAG: call spir_func void [[LOC_REF]](i32 addrspace(3)* align 4 dereferenceable(4) [[LOC_LOAD]]) bar2(*LOC); // CHECK-DAG: [[LOC_LOAD2:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast // CHECK-DAG: [[LOC_CAST2:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(3)* [[LOC_LOAD2]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[LOC_CAST2]]) + // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* align 4 dereferenceable(4) [[LOC_CAST2]]) bar(*NoAS); // CHECK-DAG: [[NoAS_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[NoAS_LOAD]]) + // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* align 4 dereferenceable(4) [[NoAS_LOAD]]) bar2(*NoAS); // CHECK-DAG: [[NoAS_LOAD2:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[NoAS_LOAD2]]) + // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* align 4 dereferenceable(4) [[NoAS_LOAD2]]) foo(GLOB); // CHECK-DAG: [[GLOB_LOAD3:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast // CHECK-DAG: [[GLOB_CAST3:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD3]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* noundef [[GLOB_CAST3]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* [[GLOB_CAST3]]) foo2(GLOB); // CHECK-DAG: [[GLOB_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast // CHECK-DAG: [[GLOB_CAST4:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD4]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* noundef [[GLOB_CAST4]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[GLOB_CAST4]]) foo(LOC); // CHECK-DAG: [[LOC_LOAD3:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast - // CHECK-DAG: call spir_func void [[LOC_PTR]](i32 addrspace(3)* noundef [[LOC_LOAD3]]) + // CHECK-DAG: call spir_func void [[LOC_PTR]](i32 addrspace(3)* [[LOC_LOAD3]]) foo2(LOC); // CHECK-DAG: [[LOC_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast // CHECK-DAG: [[LOC_CAST4:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(3)* [[LOC_LOAD4]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* noundef [[LOC_CAST4]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[LOC_CAST4]]) foo(NoAS); // CHECK-DAG: [[NoAS_LOAD3:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* noundef [[NoAS_LOAD3]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* [[NoAS_LOAD3]]) foo2(NoAS); // CHECK-DAG: [[NoAS_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* noundef [[NoAS_LOAD4]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[NoAS_LOAD4]]) // Ensure that we still get 3 different template instantiations. tmpl(GLOB); // CHECK-DAG: [[GLOB_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast - // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS1iEvT_(i32 addrspace(1)* noundef [[GLOB_LOAD4]]) + // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS1iEvT_(i32 addrspace(1)* [[GLOB_LOAD4]]) tmpl(LOC); // CHECK-DAG: [[LOC_LOAD5:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast - // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS3iEvT_(i32 addrspace(3)* noundef [[LOC_LOAD5]]) + // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS3iEvT_(i32 addrspace(3)* [[LOC_LOAD5]]) tmpl(PRIV); // CHECK-DAG: [[PRIV_LOAD5:%[a-zA-Z0-9]+]] = load i32*, i32* addrspace(4)* [[PRIV]].ascast - // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS0iEvT_(i32* noundef [[PRIV_LOAD5]]) + // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS0iEvT_(i32* [[PRIV_LOAD5]]) tmpl(NoAS); // CHECK-DAG: [[NoAS_LOAD5:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @_Z4tmplIPiEvT_(i32 addrspace(4)* noundef [[NoAS_LOAD5]]) + // CHECK-DAG: call spir_func void @_Z4tmplIPiEvT_(i32 addrspace(4)* [[NoAS_LOAD5]]) } -// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS1iEvT_(i32 addrspace(1)* noundef % -// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS3iEvT_(i32 addrspace(3)* noundef % -// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS0iEvT_(i32* noundef % -// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPiEvT_(i32 addrspace(4)* noundef % +// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS1iEvT_(i32 addrspace(1)* % +// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS3iEvT_(i32 addrspace(3)* % +// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS0iEvT_(i32* % +// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPiEvT_(i32 addrspace(4)* % diff --git a/clang/test/CodeGenSYCL/address-space-mangling.cpp b/clang/test/CodeGenSYCL/address-space-mangling.cpp --- a/clang/test/CodeGenSYCL/address-space-mangling.cpp +++ b/clang/test/CodeGenSYCL/address-space-mangling.cpp @@ -8,15 +8,15 @@ void foo(__attribute__((opencl_private)) int *); void foo(int *); -// SPIR: declare spir_func void @_Z3fooPU3AS1i(i32 addrspace(1)* noundef) #1 -// SPIR: declare spir_func void @_Z3fooPU3AS3i(i32 addrspace(3)* noundef) #1 -// SPIR: declare spir_func void @_Z3fooPU3AS0i(i32* noundef) #1 -// SPIR: declare spir_func void @_Z3fooPi(i32 addrspace(4)* noundef) #1 +// SPIR: declare spir_func void @_Z3fooPU3AS1i(i32 addrspace(1)*) #1 +// SPIR: declare spir_func void @_Z3fooPU3AS3i(i32 addrspace(3)*) #1 +// SPIR: declare spir_func void @_Z3fooPU3AS0i(i32*) #1 +// SPIR: declare spir_func void @_Z3fooPi(i32 addrspace(4)*) #1 -// X86: declare void @_Z3fooPU8SYglobali(i32* noundef) #1 -// X86: declare void @_Z3fooPU7SYlocali(i32* noundef) #1 -// X86: declare void @_Z3fooPU9SYprivatei(i32* noundef) #1 -// X86: declare void @_Z3fooPi(i32* noundef) #1 +// X86: declare void @_Z3fooPU8SYglobali(i32*) #1 +// X86: declare void @_Z3fooPU7SYlocali(i32*) #1 +// X86: declare void @_Z3fooPU9SYprivatei(i32*) #1 +// X86: declare void @_Z3fooPi(i32*) #1 void test() { __attribute__((opencl_global)) int *glob; diff --git a/clang/test/CodeGenSYCL/functionptr-addrspace.cpp b/clang/test/CodeGenSYCL/functionptr-addrspace.cpp --- a/clang/test/CodeGenSYCL/functionptr-addrspace.cpp +++ b/clang/test/CodeGenSYCL/functionptr-addrspace.cpp @@ -7,7 +7,7 @@ kernelFunc(); } -// CHECK: define dso_local spir_func{{.*}}invoke_function{{.*}}(i32 ()* noundef %fptr, i32 addrspace(4)* noundef %ptr) +// CHECK: define dso_local spir_func{{.*}}invoke_function{{.*}}(i32 ()* %fptr, i32 addrspace(4)* %ptr) void invoke_function(int (*fptr)(), int *ptr) {} int f() { return 0; } diff --git a/clang/test/CodeGenSYCL/unique_stable_name.cpp b/clang/test/CodeGenSYCL/unique_stable_name.cpp --- a/clang/test/CodeGenSYCL/unique_stable_name.cpp +++ b/clang/test/CodeGenSYCL/unique_stable_name.cpp @@ -67,48 +67,48 @@ int main() { kernel_single_task(func); - // CHECK: call spir_func void @_Z18kernel_single_taskIZ4mainE7kernel2PFPKcvEEvT0_(i8 addrspace(4)* ()* noundef @_Z4funcI4DerpEDTu33__builtin_sycl_unique_stable_nameDtsrT_3strEEEv) + // CHECK: call spir_func void @_Z18kernel_single_taskIZ4mainE7kernel2PFPKcvEEvT0_(i8 addrspace(4)* ()* @_Z4funcI4DerpEDTu33__builtin_sycl_unique_stable_nameDtsrT_3strEEEv) auto l1 = []() { return 1; }; auto l2 = [](decltype(l1) *l = nullptr) { return 2; }; kernel_single_task(l2); puts(__builtin_sycl_unique_stable_name(decltype(l2))); // CHECK: call spir_func void @_Z18kernel_single_taskIZ4mainE7kernel3Z4mainEUlPZ4mainEUlvE_E_EvT0_ - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[LAMBDA_K3_SIZE]], [[LAMBDA_K3_SIZE]]* @[[LAMBDA_KERNEL3]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[LAMBDA_K3_SIZE]], [[LAMBDA_K3_SIZE]]* @[[LAMBDA_KERNEL3]], i32 0, i32 0) to i8 addrspace(4)*)) constexpr const char str[] = "lalala"; static_assert(__builtin_strcmp(__builtin_sycl_unique_stable_name(decltype(str)), "_ZTSA7_Kc\0") == 0, "unexpected mangling"); int i = 0; puts(__builtin_sycl_unique_stable_name(decltype(i++))); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT1]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT1]], i32 0, i32 0) to i8 addrspace(4)*)) // FIXME: Ensure that j is incremented because VLAs are terrible. int j = 55; puts(__builtin_sycl_unique_stable_name(int[++j])); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[STRING_SIZE]], [[STRING_SIZE]]* @[[STRING]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[STRING_SIZE]], [[STRING_SIZE]]* @[[STRING]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z18kernel_single_taskIZ4mainE7kernel2PFPKcvEEvT0_ - // CHECK: declare spir_func noundef i8 addrspace(4)* @_Z4funcI4DerpEDTu33__builtin_sycl_unique_stable_nameDtsrT_3strEEEv + // CHECK: declare spir_func i8 addrspace(4)* @_Z4funcI4DerpEDTu33__builtin_sycl_unique_stable_nameDtsrT_3strEEEv // CHECK: define internal spir_func void @_Z18kernel_single_taskIZ4mainE7kernel3Z4mainEUlPZ4mainEUlvE_E_EvT0_ // CHECK: define internal spir_func void @_Z18kernel_single_taskIZ4mainE6kernelZ4mainEUlvE0_EvT0_ kernel_single_task( []() { puts(__builtin_sycl_unique_stable_name(int)); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT2]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT2]], i32 0, i32 0) to i8 addrspace(4)*)) auto x = []() {}; puts(__builtin_sycl_unique_stable_name(decltype(x))); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[LAMBDA_X_SIZE]], [[LAMBDA_X_SIZE]]* @[[LAMBDA_X]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[LAMBDA_X_SIZE]], [[LAMBDA_X_SIZE]]* @[[LAMBDA_X]], i32 0, i32 0) to i8 addrspace(4)*)) DEF_IN_MACRO(); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[MACRO_SIZE]], [[MACRO_SIZE]]* @[[MACRO_X]], i32 0, i32 0) to i8 addrspace(4)*)) - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[MACRO_SIZE]], [[MACRO_SIZE]]* @[[MACRO_Y]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[MACRO_SIZE]], [[MACRO_SIZE]]* @[[MACRO_X]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[MACRO_SIZE]], [[MACRO_SIZE]]* @[[MACRO_Y]], i32 0, i32 0) to i8 addrspace(4)*)) MACRO_CALLS_MACRO(); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[MACRO_MACRO_SIZE]], [[MACRO_MACRO_SIZE]]* @[[MACRO_MACRO_X]], i32 0, i32 0) to i8 addrspace(4)*)) - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[MACRO_MACRO_SIZE]], [[MACRO_MACRO_SIZE]]* @[[MACRO_MACRO_Y]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[MACRO_MACRO_SIZE]], [[MACRO_MACRO_SIZE]]* @[[MACRO_MACRO_X]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[MACRO_MACRO_SIZE]], [[MACRO_MACRO_SIZE]]* @[[MACRO_MACRO_Y]], i32 0, i32 0) to i8 addrspace(4)*)) template_param(); // CHECK: call spir_func void @_Z14template_paramIiEvv @@ -123,7 +123,7 @@ // CHECK: call spir_func void @_Z28lambda_in_dependent_functionIZZ4mainENKUlvE0_clEvEUlvE_Evv lambda_no_dep(3, 5.5); - // CHECK: call spir_func void @_Z13lambda_no_depIidEvT_T0_(i32 noundef 3, double noundef 5.500000e+00) + // CHECK: call spir_func void @_Z13lambda_no_depIidEvT_T0_(i32 3, double 5.500000e+00) int a = 5; double b = 10.7; @@ -138,22 +138,22 @@ } // CHECK: define linkonce_odr spir_func void @_Z14template_paramIiEvv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT3]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT3]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z14template_paramIZZ4mainENKUlvE0_clEvEUlvE_Evv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[LAMBDA_SIZE]], [[LAMBDA_SIZE]]* @[[LAMBDA]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[LAMBDA_SIZE]], [[LAMBDA_SIZE]]* @[[LAMBDA]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define linkonce_odr spir_func void @_Z28lambda_in_dependent_functionIiEvv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[DEP_INT_SIZE]], [[DEP_INT_SIZE]]* @[[LAMBDA_IN_DEP_INT]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[DEP_INT_SIZE]], [[DEP_INT_SIZE]]* @[[LAMBDA_IN_DEP_INT]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z28lambda_in_dependent_functionIZZ4mainENKUlvE0_clEvEUlvE_Evv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA_SIZE]], [[DEP_LAMBDA_SIZE]]* @[[LAMBDA_IN_DEP_X]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA_SIZE]], [[DEP_LAMBDA_SIZE]]* @[[LAMBDA_IN_DEP_X]], i32 0, i32 0) to i8 addrspace(4)*)) -// CHECK: define linkonce_odr spir_func void @_Z13lambda_no_depIidEvT_T0_(i32 noundef %a, double noundef %b) -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[NO_DEP_LAMBDA_SIZE]], [[NO_DEP_LAMBDA_SIZE]]* @[[LAMBDA_NO_DEP]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: define linkonce_odr spir_func void @_Z13lambda_no_depIidEvT_T0_(i32 %a, double %b) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[NO_DEP_LAMBDA_SIZE]], [[NO_DEP_LAMBDA_SIZE]]* @[[LAMBDA_NO_DEP]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z14lambda_two_depIZZ4mainENKUlvE0_clEvEUliE_ZZ4mainENKS0_clEvEUldE_Evv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA1_SIZE]], [[DEP_LAMBDA1_SIZE]]* @[[LAMBDA_TWO_DEP]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA1_SIZE]], [[DEP_LAMBDA1_SIZE]]* @[[LAMBDA_TWO_DEP]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z14lambda_two_depIZZ4mainENKUlvE0_clEvEUldE_ZZ4mainENKS0_clEvEUliE_Evv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA2_SIZE]], [[DEP_LAMBDA2_SIZE]]* @[[LAMBDA_TWO_DEP2]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA2_SIZE]], [[DEP_LAMBDA2_SIZE]]* @[[LAMBDA_TWO_DEP2]], i32 0, i32 0) to i8 addrspace(4)*)) diff --git a/clang/test/OpenMP/amdgcn-attributes.cpp b/clang/test/OpenMP/amdgcn-attributes.cpp --- a/clang/test/OpenMP/amdgcn-attributes.cpp +++ b/clang/test/OpenMP/amdgcn-attributes.cpp @@ -28,7 +28,7 @@ } int callable(int x) { - // ALL-LABEL: @_Z8callablei(i32 noundef %x) #1 + // ALL-LABEL: @_Z8callablei(i32 %x) #1 return x + 1; } diff --git a/clang/test/OpenMP/amdgcn_target_global_constructor.cpp b/clang/test/OpenMP/amdgcn_target_global_constructor.cpp --- a/clang/test/OpenMP/amdgcn_target_global_constructor.cpp +++ b/clang/test/OpenMP/amdgcn_target_global_constructor.cpp @@ -23,41 +23,41 @@ // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_.*_.*}}_A_l19_ctor // CHECK-SAME: () #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) addrspacecast ([[STRUCT_S:%.*]] addrspace(1)* @A to %struct.S*)) #[[ATTR3:[0-9]+]] +// CHECK-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) addrspacecast ([[STRUCT_S:%.*]] addrspace(1)* @A to %struct.S*)) #[[ATTR3:[0-9]+]] // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8, addrspace(5) // CHECK-NEXT: [[THIS_ADDR_ASCAST:%.*]] = addrspacecast %struct.S* addrspace(5)* [[THIS_ADDR]] to %struct.S** // CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR_ASCAST]], align 8 -// CHECK-NEXT: call void @_ZN1SC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_.*_.*}}_A_l19_dtor // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) addrspacecast ([[STRUCT_S:%.*]] addrspace(1)* @A to %struct.S*)) #[[ATTR4:[0-9]+]] +// CHECK-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) addrspacecast ([[STRUCT_S:%.*]] addrspace(1)* @A to %struct.S*)) #[[ATTR4:[0-9]+]] // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8, addrspace(5) // CHECK-NEXT: [[THIS_ADDR_ASCAST:%.*]] = addrspacecast %struct.S* addrspace(5)* [[THIS_ADDR]] to %struct.S** // CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR_ASCAST]], align 8 -// CHECK-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8, addrspace(5) // CHECK-NEXT: [[THIS_ADDR_ASCAST:%.*]] = addrspacecast %struct.S* addrspace(5)* [[THIS_ADDR]] to %struct.S** @@ -69,7 +69,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8, addrspace(5) // CHECK-NEXT: [[THIS_ADDR_ASCAST:%.*]] = addrspacecast %struct.S* addrspace(5)* [[THIS_ADDR]] to %struct.S** diff --git a/clang/test/OpenMP/assumes_include_nvptx.cpp b/clang/test/OpenMP/assumes_include_nvptx.cpp --- a/clang/test/OpenMP/assumes_include_nvptx.cpp +++ b/clang/test/OpenMP/assumes_include_nvptx.cpp @@ -13,11 +13,11 @@ // CHECK: define weak_odr void @__omp_offloading_{{.*}}__Z17complex_reductionIfEvv_{{.*}}() [[attr0:#[0-9]]] // CHECK: call i32 @__kmpc_target_init( -// CHECK: declare noundef float @_Z3sinf(float noundef) [[attr1:#[0-9]*]] +// CHECK: declare float @_Z3sinf(float) [[attr1:#[0-9]*]] // CHECK: declare void @__kmpc_target_deinit( // CHECK: define weak_odr void @__omp_offloading_{{.*}}__Z17complex_reductionIdEvv_{{.*}}() [[attr0]] -// CHECK: %call = call noundef double @_Z3sind(double noundef 0.000000e+00) [[attr2:#[0-9]]] -// CHECK: declare noundef double @_Z3sind(double noundef) [[attr1]] +// CHECK: %call = call double @_Z3sind(double 0.000000e+00) [[attr2:#[0-9]]] +// CHECK: declare double @_Z3sind(double) [[attr1]] // CHECK: attributes [[attr0]] // CHECK-NOT: "llvm.assume" diff --git a/clang/test/OpenMP/declare_target_codegen.cpp b/clang/test/OpenMP/declare_target_codegen.cpp --- a/clang/test/OpenMP/declare_target_codegen.cpp +++ b/clang/test/OpenMP/declare_target_codegen.cpp @@ -139,7 +139,7 @@ int maini1() { int a; static long aa = 32 + bbb + ccc + fff + ggg; -// CHECK-DAG: define weak_odr void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](i32* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %{{.*}}, i64 {{.*}}, i64 {{.*}}) +// CHECK-DAG: define weak_odr void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](i32* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %{{.*}}, i64 {{.*}}, i64 {{.*}}) #pragma omp target map(tofrom \ : a, b) { @@ -243,7 +243,7 @@ // CHECK-DAG: define {{.*}}void @__omp_offloading_{{.*}}emitted{{.*}}_l[[@LINE-5]]() -// CHECK-DAG: declare extern_weak noundef signext i32 @__create() +// CHECK-DAG: declare extern_weak signext i32 @__create() // CHECK-NOT: define {{.*}}{{baz1|baz4|maini1|Base|virtual_}} diff --git a/clang/test/OpenMP/declare_target_codegen_globalization.cpp b/clang/test/OpenMP/declare_target_codegen_globalization.cpp --- a/clang/test/OpenMP/declare_target_codegen_globalization.cpp +++ b/clang/test/OpenMP/declare_target_codegen_globalization.cpp @@ -25,7 +25,7 @@ // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -48,7 +48,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -58,15 +58,15 @@ // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooRi(i32* noundef nonnull align 4 dereferenceable(4) [[B]]) #[[ATTR6:[0-9]+]] -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef i32 @_Z3barv() #[[ATTR6]] +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooRi(i32* nonnull align 4 dereferenceable(4) [[B]]) #[[ATTR6:[0-9]+]] +// CHECK1-NEXT: [[CALL1:%.*]] = call i32 @_Z3barv() #[[ATTR6]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z3fooRi -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 @@ -80,7 +80,7 @@ // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i64 4) // CHECK1-NEXT: [[A_ON_STACK:%.*]] = bitcast i8* [[A]] to i32* -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooRi(i32* noundef nonnull align 4 dereferenceable(4) [[A_ON_STACK]]) #[[ATTR6]] +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooRi(i32* nonnull align 4 dereferenceable(4) [[A_ON_STACK]]) #[[ATTR6]] // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[A]], i64 4) // CHECK1-NEXT: ret i32 [[CALL]] // diff --git a/clang/test/OpenMP/declare_target_link_codegen.cpp b/clang/test/OpenMP/declare_target_link_codegen.cpp --- a/clang/test/OpenMP/declare_target_link_codegen.cpp +++ b/clang/test/OpenMP/declare_target_link_codegen.cpp @@ -50,7 +50,7 @@ return 0; } -// DEVICE: define weak_odr void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l42(i32* noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}} +// DEVICE: define weak_odr void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l42(i32* nonnull align {{[0-9]+}} dereferenceable{{[^,]*}} // DEVICE: [[C_REF:%.+]] = load i32*, i32** @c_decl_tgt_ref_ptr, // DEVICE: [[C:%.+]] = load i32, i32* [[C_REF]], // DEVICE: store i32 [[C]], i32* % diff --git a/clang/test/OpenMP/declare_variant_mixed_codegen.c b/clang/test/OpenMP/declare_variant_mixed_codegen.c --- a/clang/test/OpenMP/declare_variant_mixed_codegen.c +++ b/clang/test/OpenMP/declare_variant_mixed_codegen.c @@ -45,8 +45,8 @@ // HOST: call i32 @dev(double noundef -4.000000e+00) // GPU: define {{.*}}void @__omp_offloading_{{.+}}_foo_l36() -// GPU: call i32 @dev(double noundef -3.000000e+00) -// GPU: call i32 @dev(double noundef -4.000000e+00) +// GPU: call i32 @dev(double -3.000000e+00) +// GPU: call i32 @dev(double -4.000000e+00) // GPU-NOT: @base // GPU: define {{.*}}i32 @dev(double diff --git a/clang/test/OpenMP/distribute_codegen.cpp b/clang/test/OpenMP/distribute_codegen.cpp --- a/clang/test/OpenMP/distribute_codegen.cpp +++ b/clang/test/OpenMP/distribute_codegen.cpp @@ -1945,7 +1945,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1960,7 +1960,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2054,7 +2054,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2069,7 +2069,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2163,7 +2163,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2178,7 +2178,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2289,7 +2289,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -2299,7 +2299,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2392,7 +2392,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -2402,7 +2402,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2483,8 +2483,547 @@ // CHECK17-NEXT: ret void // // +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] +// CHECK18-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] +// CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK18-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] +// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 +// CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] +// CHECK18-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 +// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] +// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] +// CHECK18-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] +// CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK18-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] +// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 +// CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] +// CHECK18-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 +// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] +// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK18: omp.dispatch.cond: +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK18: omp.dispatch.body: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK18-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !11 +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] +// CHECK18-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !11 +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK18-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] +// CHECK18-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK18-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !11 +// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] +// CHECK18-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] +// CHECK18-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !11 +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 +// CHECK18-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] +// CHECK18-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 +// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK18: omp.dispatch.inc: +// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK18-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK18: omp.dispatch.end: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 +// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I5:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK18-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK18-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK18-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK18-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK18-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 +// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK18: omp.precond.then: +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] +// CHECK18-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 +// CHECK18-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK18-NEXT: br label [[OMP_PRECOND_END]] +// CHECK18: omp.precond.end: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 +// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK18-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK18: omp.dispatch.cond: +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK18: omp.dispatch.body: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK18: omp.dispatch.inc: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK18: omp.dispatch.end: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK18-NEXT: ret void +// +// // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2499,7 +3038,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2589,7 +3128,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2604,7 +3143,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2694,7 +3233,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2709,7 +3248,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2816,7 +3355,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -2826,7 +3365,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2919,7 +3458,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -2929,7 +3468,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3009,3 +3548,530 @@ // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK19-NEXT: ret void // +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] +// CHECK20-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] +// CHECK20-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK20-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] +// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 +// CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] +// CHECK20-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] +// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] +// CHECK20-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] +// CHECK20-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK20-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] +// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 +// CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] +// CHECK20-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] +// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK20: omp.dispatch.cond: +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK20: omp.dispatch.body: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK20-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] +// CHECK20-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] +// CHECK20-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK20-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] +// CHECK20-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] +// CHECK20-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] +// CHECK20-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 +// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK20: omp.dispatch.inc: +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK20-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK20: omp.dispatch.end: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 +// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I5:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i8*, i8** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1 +// CHECK20-NEXT: store i8 [[TMP1]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK20-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK20-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 +// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK20: omp.precond.then: +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] +// CHECK20-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK20-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK20-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] +// CHECK20-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 +// CHECK20-NEXT: store i8 [[CONV10]], i8* [[I5]], align 1 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK20-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK20-NEXT: br label [[OMP_PRECOND_END]] +// CHECK20: omp.precond.end: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 +// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK20: omp.dispatch.cond: +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK20: omp.dispatch.body: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK20: omp.dispatch.inc: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK20: omp.dispatch.end: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK20-NEXT: ret void +// diff --git a/clang/test/OpenMP/distribute_simd_codegen.cpp b/clang/test/OpenMP/distribute_simd_codegen.cpp --- a/clang/test/OpenMP/distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_codegen.cpp @@ -5473,7 +5473,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5488,7 +5488,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5591,7 +5591,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5606,7 +5606,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5707,7 +5707,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5722,7 +5722,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5840,7 +5840,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK17-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5853,7 +5853,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5967,7 +5967,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -5977,7 +5977,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6065,8 +6065,601 @@ // CHECK17-NEXT: ret void // // +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8 +// CHECK18-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ] +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] +// CHECK18-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 +// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]] +// CHECK18-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] +// CHECK18-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 +// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]] +// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] +// CHECK18-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]] +// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) +// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK18-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] +// CHECK18-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] +// CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK18-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] +// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 +// CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] +// CHECK18-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 +// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] +// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK18-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK18: omp.dispatch.cond: +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK18: omp.dispatch.body: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK18-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !18 +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] +// CHECK18-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !18 +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK18-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] +// CHECK18-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK18-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !18 +// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] +// CHECK18-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] +// CHECK18-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !18 +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 +// CHECK18-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] +// CHECK18-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 +// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK18: omp.dispatch.inc: +// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK18-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK18: omp.dispatch.end: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 +// CHECK18-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 +// CHECK18-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8 +// CHECK18-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 +// CHECK18-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK18-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK18-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK18-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK18-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 +// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 +// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK18: omp.precond.then: +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK18-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21 +// CHECK18-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 +// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK18-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK18-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK18-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 +// CHECK18-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 +// CHECK18-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] +// CHECK18-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 +// CHECK18-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 +// CHECK18-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 +// CHECK18-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 +// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] +// CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK18-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: br label [[OMP_PRECOND_END]] +// CHECK18: omp.precond.end: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 +// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK18-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK18: omp.dispatch.cond: +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK18: omp.dispatch.body: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK18: omp.dispatch.inc: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK18: omp.dispatch.end: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK18-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6081,7 +6674,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6180,7 +6773,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6195,7 +6788,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6292,7 +6885,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6307,7 +6900,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6421,7 +7014,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK19-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6434,7 +7027,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6548,7 +7141,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -6558,7 +7151,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6646,8 +7239,589 @@ // CHECK19-NEXT: ret void // // +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4 +// CHECK20-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ] +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK20-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]] +// CHECK20-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] +// CHECK20-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]] +// CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] +// CHECK20-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]] +// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) +// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK20-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] +// CHECK20-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] +// CHECK20-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK20-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] +// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 +// CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] +// CHECK20-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] +// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK20-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK20: omp.dispatch.cond: +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK20: omp.dispatch.body: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK20-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] +// CHECK20-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] +// CHECK20-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK20-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] +// CHECK20-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] +// CHECK20-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] +// CHECK20-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 +// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK20: omp.dispatch.inc: +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK20-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK20: omp.dispatch.end: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 +// CHECK20-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 +// CHECK20-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8* +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4 +// CHECK20-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 +// CHECK20-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK20-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK20-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 +// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 +// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK20: omp.precond.then: +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK20-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22 +// CHECK20-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 +// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK20-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK20-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK20-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !22 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK20-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) +// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 +// CHECK20-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 +// CHECK20-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 +// CHECK20-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] +// CHECK20-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 +// CHECK20-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 +// CHECK20-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 +// CHECK20-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 +// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] +// CHECK20-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK20-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: br label [[OMP_PRECOND_END]] +// CHECK20: omp.precond.end: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 +// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK20: omp.dispatch.cond: +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK20: omp.dispatch.body: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK20: omp.dispatch.inc: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK20: omp.dispatch.end: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK20-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6662,7 +7836,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6765,7 +7939,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6780,7 +7954,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6881,7 +8055,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6896,7 +8070,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7014,7 +8188,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK21-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -7027,7 +8201,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7172,7 +8346,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK21-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -7182,7 +8356,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7270,8 +8444,632 @@ // CHECK21-NEXT: ret void // // +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 +// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK22-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK22-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK22-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8 +// CHECK22-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ] +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 +// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] +// CHECK22-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 +// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK22-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]] +// CHECK22-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] +// CHECK22-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 +// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]] +// CHECK22-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] +// CHECK22-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 +// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK22-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]] +// CHECK22-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK22-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) +// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK22-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 +// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK22-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK22-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK22-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK22-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK22-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !nontemporal !16 +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] +// CHECK22-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK22-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 +// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK22-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK22-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] +// CHECK22-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK22-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK22-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 +// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] +// CHECK22-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 +// CHECK22-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] +// CHECK22-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !nontemporal !16 +// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK22-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK22-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] +// CHECK22-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK22-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 +// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 +// CHECK22-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 +// CHECK22-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 +// CHECK22-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK22-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK22: omp.dispatch.cond: +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK22: omp.dispatch.body: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK22-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !19 +// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] +// CHECK22-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !19 +// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] +// CHECK22-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK22-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !19 +// CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 +// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] +// CHECK22-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] +// CHECK22-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !19 +// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 +// CHECK22-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] +// CHECK22-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 +// CHECK22-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK22: omp.dispatch.inc: +// CHECK22-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK22-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK22-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK22: omp.dispatch.end: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK22-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 +// CHECK22-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 +// CHECK22-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8* +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8 +// CHECK22-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 +// CHECK22-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK22-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK22-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK22-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK22-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK22-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK22-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK22-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK22-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK22-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 +// CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK22-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 +// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK22-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK22: omp.precond.then: +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK22-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK22-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1 +// CHECK22-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 +// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK22: omp_if.then: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK22-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK22-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22 +// CHECK22-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 +// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK22-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK22-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK22-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK22-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK22: omp_if.else: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] +// CHECK22: omp.inner.for.cond13: +// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK22-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] +// CHECK22: omp.inner.for.body15: +// CHECK22-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK22-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK22-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] +// CHECK22-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK22-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] +// CHECK22: omp.body.continue20: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] +// CHECK22: omp.inner.for.inc21: +// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK22-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK22: omp.inner.for.end23: +// CHECK22-NEXT: br label [[OMP_IF_END]] +// CHECK22: omp_if.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK22-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK22-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 +// CHECK22-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK22-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 +// CHECK22-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] +// CHECK22-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 +// CHECK22-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 +// CHECK22-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 +// CHECK22-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 +// CHECK22-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] +// CHECK22-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 +// CHECK22-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: br label [[OMP_PRECOND_END]] +// CHECK22: omp.precond.end: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 +// CHECK22-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK22-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK22-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK22: omp.dispatch.cond: +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK22: omp.dispatch.body: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK22-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK22: omp.dispatch.inc: +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK22-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK22-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK22: omp.dispatch.end: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK22-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -7286,7 +9084,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7385,7 +9183,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -7400,7 +9198,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7497,7 +9295,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -7512,7 +9310,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7626,7 +9424,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK23-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7639,7 +9437,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7784,7 +9582,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK23-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -7794,7 +9592,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7881,3 +9679,3291 @@ // CHECK23: .omp.final.done: // CHECK23-NEXT: ret void // +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 +// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK24-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK24-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK24-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4 +// CHECK24-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ] +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK24-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]] +// CHECK24-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] +// CHECK24-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]] +// CHECK24-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] +// CHECK24-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]] +// CHECK24-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK24-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) +// CHECK24-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK24-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 +// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK24-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK24-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK24-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 +// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK24-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK24-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4, !nontemporal !17 +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] +// CHECK24-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK24-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 +// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 +// CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] +// CHECK24-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] +// CHECK24-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 +// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] +// CHECK24-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 +// CHECK24-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] +// CHECK24-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4, !nontemporal !17 +// CHECK24-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] +// CHECK24-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK24-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 +// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 +// CHECK24-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 +// CHECK24-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 +// CHECK24-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) +// CHECK24-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK24: omp.dispatch.cond: +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK24: omp.dispatch.body: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] +// CHECK24-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 +// CHECK24-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] +// CHECK24-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] +// CHECK24-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] +// CHECK24-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] +// CHECK24-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] +// CHECK24-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] +// CHECK24-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 +// CHECK24-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK24: omp.dispatch.inc: +// CHECK24-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] +// CHECK24-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] +// CHECK24-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK24: omp.dispatch.end: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK24-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 +// CHECK24-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 +// CHECK24-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8* +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8* +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4 +// CHECK24-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 +// CHECK24-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK24-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK24-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK24-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK24-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK24-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK24-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK24-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK24-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK24-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 +// CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK24-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 +// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK24-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK24: omp.precond.then: +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK24-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK24-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1 +// CHECK24-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 +// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK24: omp_if.then: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK24-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK24-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !23 +// CHECK24-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 +// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK24-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK24-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK24-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !17, !llvm.access.group !23 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK24-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK24-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK24: omp_if.else: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] +// CHECK24: omp.inner.for.cond13: +// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] +// CHECK24-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] +// CHECK24: omp.inner.for.body15: +// CHECK24-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK24-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK24-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] +// CHECK24-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK24-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] +// CHECK24: omp.body.continue20: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] +// CHECK24: omp.inner.for.inc21: +// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK24-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK24: omp.inner.for.end23: +// CHECK24-NEXT: br label [[OMP_IF_END]] +// CHECK24: omp_if.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK24-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK24-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK24-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 +// CHECK24-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK24-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 +// CHECK24-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] +// CHECK24-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 +// CHECK24-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 +// CHECK24-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 +// CHECK24-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 +// CHECK24-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] +// CHECK24-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 +// CHECK24-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: br label [[OMP_PRECOND_END]] +// CHECK24: omp.precond.end: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 +// CHECK24-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) +// CHECK24-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK24: omp.dispatch.cond: +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK24: omp.dispatch.body: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK24-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK24-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK24: omp.dispatch.inc: +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK24-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK24-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK24: omp.dispatch.end: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 +// CHECK24-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK25-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK25-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK25-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK25-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK25-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ] +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] +// CHECK25-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK25-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]] +// CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]] +// CHECK25-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2 +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK25-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]] +// CHECK25-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]] +// CHECK25-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2 +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]] +// CHECK25-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK25-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK25-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK25-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK25-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK25-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 +// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK25-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 +// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] +// CHECK25-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK25-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK25-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] +// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK25-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK25-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK25-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK25-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] +// CHECK25-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4 +// CHECK25-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] +// CHECK25-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK25-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] +// CHECK25-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK25-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK25-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK25-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK25-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 +// CHECK25-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] +// CHECK25-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK25-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] +// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK25-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK25-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] +// CHECK25-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] +// CHECK25-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] +// CHECK25-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1 +// CHECK25-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z12test_precondv +// CHECK25-SAME: () #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[I7:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: store i8 0, i8* [[A]], align 1 +// CHECK25-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 +// CHECK25-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK25-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK25-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK25-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK25-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK25-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK25-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK25-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK25-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK25-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 +// CHECK25-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK25-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK25-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK25: simd.if.then: +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 +// CHECK25-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK25-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !12 +// CHECK25-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK25-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK25-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK25-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !12 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK25-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK25-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32 +// CHECK25-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK25-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32 +// CHECK25-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] +// CHECK25-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 +// CHECK25-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 +// CHECK25-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 +// CHECK25-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 +// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] +// CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK25-NEXT: store i8 [[CONV21]], i8* [[I]], align 1 +// CHECK25-NEXT: br label [[SIMD_IF_END]] +// CHECK25: simd.if.end: +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z4fintv +// CHECK25-SAME: () #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK25-NEXT: ret i32 [[CALL]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v +// CHECK25-SAME: () #[[ATTR0]] comdat { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK25-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK25-NEXT: ret i32 0 +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK26-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK26-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK26-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK26-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK26-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ] +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] +// CHECK26-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2 +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK26-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]] +// CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]] +// CHECK26-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2 +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK26-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]] +// CHECK26-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]] +// CHECK26-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2 +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]] +// CHECK26-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK26-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK26-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK26-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK26-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK26-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 +// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK26-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 +// CHECK26-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] +// CHECK26-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK26-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK26-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] +// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK26-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK26-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK26-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK26-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] +// CHECK26-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4 +// CHECK26-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] +// CHECK26-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK26-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] +// CHECK26-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK26-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK26-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK26-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK26-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 +// CHECK26-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] +// CHECK26-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK26-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] +// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK26-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK26-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] +// CHECK26-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] +// CHECK26-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] +// CHECK26-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1 +// CHECK26-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z12test_precondv +// CHECK26-SAME: () #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[I7:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: store i8 0, i8* [[A]], align 1 +// CHECK26-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 +// CHECK26-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK26-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK26-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK26-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK26-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK26-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK26-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK26-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK26-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK26-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 +// CHECK26-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK26-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK26-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK26-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK26: simd.if.then: +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 +// CHECK26-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK26-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !12 +// CHECK26-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK26-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK26-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK26-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !12 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK26-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK26-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32 +// CHECK26-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK26-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32 +// CHECK26-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] +// CHECK26-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 +// CHECK26-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 +// CHECK26-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 +// CHECK26-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 +// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] +// CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK26-NEXT: store i8 [[CONV21]], i8* [[I]], align 1 +// CHECK26-NEXT: br label [[SIMD_IF_END]] +// CHECK26: simd.if.end: +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z4fintv +// CHECK26-SAME: () #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK26-NEXT: ret i32 [[CALL]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v +// CHECK26-SAME: () #[[ATTR0]] comdat { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK26-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK26-NEXT: ret i32 0 +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK27-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK27-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK27-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK27-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK27-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ] +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]] +// CHECK27-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]] +// CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]] +// CHECK27-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]] +// CHECK27-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]] +// CHECK27-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] +// CHECK27-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK27-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK27-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK27-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK27-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 +// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK27-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] +// CHECK27-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK27-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] +// CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4 +// CHECK27-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK27-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK27-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] +// CHECK27-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK27-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] +// CHECK27-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK27-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK27-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK27-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK27-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK27-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 +// CHECK27-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] +// CHECK27-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] +// CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK27-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] +// CHECK27-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] +// CHECK27-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK27-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1 +// CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z12test_precondv +// CHECK27-SAME: () #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[I7:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: store i8 0, i8* [[A]], align 1 +// CHECK27-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 +// CHECK27-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK27-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK27-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK27-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK27-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK27-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK27-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK27-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK27-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK27-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 +// CHECK27-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK27-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK27-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK27: simd.if.then: +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 +// CHECK27-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK27-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13 +// CHECK27-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK27-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK27-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK27-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !13 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK27-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK27-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32 +// CHECK27-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK27-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32 +// CHECK27-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] +// CHECK27-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 +// CHECK27-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 +// CHECK27-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 +// CHECK27-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 +// CHECK27-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] +// CHECK27-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK27-NEXT: store i8 [[CONV21]], i8* [[I]], align 1 +// CHECK27-NEXT: br label [[SIMD_IF_END]] +// CHECK27: simd.if.end: +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z4fintv +// CHECK27-SAME: () #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK27-NEXT: ret i32 [[CALL]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v +// CHECK27-SAME: () #[[ATTR0]] comdat { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK27-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK27-NEXT: ret i32 0 +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK28-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK28-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK28-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK28-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK28-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ] +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]] +// CHECK28-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]] +// CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]] +// CHECK28-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]] +// CHECK28-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]] +// CHECK28-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] +// CHECK28-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK28-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK28-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK28-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK28-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 +// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK28-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] +// CHECK28-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK28-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] +// CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4 +// CHECK28-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK28-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK28-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] +// CHECK28-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK28-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] +// CHECK28-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK28-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK28-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK28-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK28-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK28-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 +// CHECK28-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] +// CHECK28-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] +// CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK28-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] +// CHECK28-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] +// CHECK28-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK28-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1 +// CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z12test_precondv +// CHECK28-SAME: () #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[I7:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: store i8 0, i8* [[A]], align 1 +// CHECK28-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 +// CHECK28-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK28-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK28-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK28-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK28-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK28-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK28-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK28-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK28-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK28-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 +// CHECK28-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK28-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK28-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK28: simd.if.then: +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 +// CHECK28-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK28-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13 +// CHECK28-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK28-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK28-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK28-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !13 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK28-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK28-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32 +// CHECK28-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK28-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32 +// CHECK28-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] +// CHECK28-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 +// CHECK28-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 +// CHECK28-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 +// CHECK28-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 +// CHECK28-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] +// CHECK28-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK28-NEXT: store i8 [[CONV21]], i8* [[I]], align 1 +// CHECK28-NEXT: br label [[SIMD_IF_END]] +// CHECK28: simd.if.end: +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z4fintv +// CHECK28-SAME: () #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK28-NEXT: ret i32 [[CALL]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v +// CHECK28-SAME: () #[[ATTR0]] comdat { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK28-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK28-NEXT: ret i32 0 +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK29-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK29-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK29-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK29-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK29-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ] +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] +// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2 +// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] +// CHECK29-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2 +// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK29-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]] +// CHECK29-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]] +// CHECK29-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2 +// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]] +// CHECK29-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]] +// CHECK29-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2 +// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK29-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]] +// CHECK29-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK29-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK29-NEXT: ret void +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK29-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK29-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK29-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK29-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 +// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK29-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK29-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !nontemporal !7 +// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 +// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] +// CHECK29-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK29-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8 +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK29-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK29-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] +// CHECK29-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK29-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK29-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8 +// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK29-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] +// CHECK29-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4 +// CHECK29-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] +// CHECK29-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !nontemporal !7 +// CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK29-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK29-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] +// CHECK29-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK29-NEXT: ret void +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK29-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK29-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK29-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK29-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] +// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 +// CHECK29-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !10 +// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] +// CHECK29-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !10 +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK29-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] +// CHECK29-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK29-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !10 +// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] +// CHECK29-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] +// CHECK29-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !10 +// CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK29-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] +// CHECK29-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1 +// CHECK29-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK29-NEXT: ret void +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z12test_precondv +// CHECK29-SAME: () #[[ATTR0]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[I7:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: store i8 0, i8* [[A]], align 1 +// CHECK29-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 +// CHECK29-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK29-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK29-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK29-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK29-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK29-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK29-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK29-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 +// CHECK29-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK29-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK29: simd.if.then: +// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 +// CHECK29-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 +// CHECK29-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 +// CHECK29-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0 +// CHECK29-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK29: omp_if.then: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK29-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13 +// CHECK29-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32 +// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK29-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK29-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK29-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !7, !llvm.access.group !13 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK29-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK29: omp_if.else: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] +// CHECK29: omp.inner.for.cond13: +// CHECK29-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK29-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] +// CHECK29: omp.inner.for.body15: +// CHECK29-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK29-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK29-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] +// CHECK29-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK29-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] +// CHECK29: omp.body.continue20: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] +// CHECK29: omp.inner.for.inc21: +// CHECK29-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK29-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK29: omp.inner.for.end23: +// CHECK29-NEXT: br label [[OMP_IF_END]] +// CHECK29: omp_if.end: +// CHECK29-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32 +// CHECK29-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32 +// CHECK29-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] +// CHECK29-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 +// CHECK29-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 +// CHECK29-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 +// CHECK29-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 +// CHECK29-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] +// CHECK29-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 +// CHECK29-NEXT: store i8 [[CONV32]], i8* [[I]], align 1 +// CHECK29-NEXT: br label [[SIMD_IF_END]] +// CHECK29: simd.if.end: +// CHECK29-NEXT: ret void +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z4fintv +// CHECK29-SAME: () #[[ATTR0]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK29-NEXT: ret i32 [[CALL]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v +// CHECK29-SAME: () #[[ATTR0]] comdat { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK29-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK29-NEXT: ret i32 0 +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK30-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK30-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK30-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK30-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8 +// CHECK30-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ] +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] +// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2 +// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] +// CHECK30-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2 +// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK30-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]] +// CHECK30-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]] +// CHECK30-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2 +// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]] +// CHECK30-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]] +// CHECK30-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2 +// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK30-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]] +// CHECK30-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK30-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK30-NEXT: ret void +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK30-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK30-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK30-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK30-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 +// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK30-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK30-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !nontemporal !7 +// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 +// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] +// CHECK30-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK30-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8 +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK30-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK30-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] +// CHECK30-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 +// CHECK30-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK30-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8 +// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK30-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] +// CHECK30-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4 +// CHECK30-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] +// CHECK30-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !nontemporal !7 +// CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK30-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK30-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] +// CHECK30-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK30-NEXT: ret void +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK30-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 +// CHECK30-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 +// CHECK30-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 +// CHECK30-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] +// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 +// CHECK30-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !10 +// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] +// CHECK30-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !10 +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK30-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] +// CHECK30-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK30-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !10 +// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] +// CHECK30-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] +// CHECK30-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !10 +// CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK30-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] +// CHECK30-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1 +// CHECK30-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK30-NEXT: ret void +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z12test_precondv +// CHECK30-SAME: () #[[ATTR0]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[I7:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: store i8 0, i8* [[A]], align 1 +// CHECK30-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 +// CHECK30-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK30-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK30-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK30-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK30-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK30-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK30-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK30-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 +// CHECK30-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK30-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK30: simd.if.then: +// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 +// CHECK30-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 +// CHECK30-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 +// CHECK30-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0 +// CHECK30-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK30: omp_if.then: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK30-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13 +// CHECK30-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32 +// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK30-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK30-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK30-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !7, !llvm.access.group !13 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK30-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK30: omp_if.else: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] +// CHECK30: omp.inner.for.cond13: +// CHECK30-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK30-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] +// CHECK30: omp.inner.for.body15: +// CHECK30-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK30-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK30-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] +// CHECK30-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK30-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] +// CHECK30: omp.body.continue20: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] +// CHECK30: omp.inner.for.inc21: +// CHECK30-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK30-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK30: omp.inner.for.end23: +// CHECK30-NEXT: br label [[OMP_IF_END]] +// CHECK30: omp_if.end: +// CHECK30-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32 +// CHECK30-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32 +// CHECK30-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] +// CHECK30-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 +// CHECK30-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 +// CHECK30-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 +// CHECK30-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 +// CHECK30-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] +// CHECK30-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 +// CHECK30-NEXT: store i8 [[CONV32]], i8* [[I]], align 1 +// CHECK30-NEXT: br label [[SIMD_IF_END]] +// CHECK30: simd.if.end: +// CHECK30-NEXT: ret void +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z4fintv +// CHECK30-SAME: () #[[ATTR0]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK30-NEXT: ret i32 [[CALL]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v +// CHECK30-SAME: () #[[ATTR0]] comdat { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK30-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK30-NEXT: ret i32 0 +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK31-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK31-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK31-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK31-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK31-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ] +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] +// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]] +// CHECK31-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]] +// CHECK31-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]] +// CHECK31-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]] +// CHECK31-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]] +// CHECK31-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] +// CHECK31-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK31-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK31-NEXT: ret void +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK31-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK31-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK31-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK31-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 +// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK31-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK31-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !nontemporal !8 +// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] +// CHECK31-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK31-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4 +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK31-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] +// CHECK31-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4 +// CHECK31-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK31-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4 +// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK31-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] +// CHECK31-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK31-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] +// CHECK31-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !nontemporal !8 +// CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK31-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK31-NEXT: ret void +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK31-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK31-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK31-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK31-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] +// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 +// CHECK31-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] +// CHECK31-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] +// CHECK31-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK31-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] +// CHECK31-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] +// CHECK31-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK31-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1 +// CHECK31-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK31-NEXT: ret void +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z12test_precondv +// CHECK31-SAME: () #[[ATTR0]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[I7:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: store i8 0, i8* [[A]], align 1 +// CHECK31-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 +// CHECK31-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK31-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK31-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK31-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK31-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK31-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK31-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK31-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 +// CHECK31-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK31-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK31: simd.if.then: +// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 +// CHECK31-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 +// CHECK31-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 +// CHECK31-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0 +// CHECK31-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK31: omp_if.then: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK31-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !14 +// CHECK31-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32 +// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK31-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK31-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK31-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !8, !llvm.access.group !14 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK31-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK31: omp_if.else: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] +// CHECK31: omp.inner.for.cond13: +// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK31-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] +// CHECK31: omp.inner.for.body15: +// CHECK31-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK31-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] +// CHECK31-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK31-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] +// CHECK31: omp.body.continue20: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] +// CHECK31: omp.inner.for.inc21: +// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK31-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK31: omp.inner.for.end23: +// CHECK31-NEXT: br label [[OMP_IF_END]] +// CHECK31: omp_if.end: +// CHECK31-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32 +// CHECK31-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32 +// CHECK31-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] +// CHECK31-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 +// CHECK31-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 +// CHECK31-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 +// CHECK31-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 +// CHECK31-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] +// CHECK31-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 +// CHECK31-NEXT: store i8 [[CONV32]], i8* [[I]], align 1 +// CHECK31-NEXT: br label [[SIMD_IF_END]] +// CHECK31: simd.if.end: +// CHECK31-NEXT: ret void +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z4fintv +// CHECK31-SAME: () #[[ATTR0]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK31-NEXT: ret i32 [[CALL]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v +// CHECK31-SAME: () #[[ATTR0]] comdat { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK31-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK31-NEXT: ret i32 0 +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ +// CHECK32-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK32-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK32-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK32-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4 +// CHECK32-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ] +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] +// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] +// CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]] +// CHECK32-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]] +// CHECK32-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]] +// CHECK32-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]] +// CHECK32-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]] +// CHECK32-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] +// CHECK32-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK32-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: store i32 32000001, i32* [[I]], align 4 +// CHECK32-NEXT: ret void +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ +// CHECK32-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK32-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK32-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK32-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 +// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] +// CHECK32-NEXT: store i32 [[SUB]], i32* [[I]], align 4 +// CHECK32-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !nontemporal !8 +// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] +// CHECK32-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK32-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4 +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] +// CHECK32-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4 +// CHECK32-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK32-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4 +// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK32-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] +// CHECK32-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4 +// CHECK32-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] +// CHECK32-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !nontemporal !8 +// CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 +// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK32-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: store i32 32, i32* [[I]], align 4 +// CHECK32-NEXT: ret void +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ +// CHECK32-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 +// CHECK32-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 +// CHECK32-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 +// CHECK32-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] +// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 +// CHECK32-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] +// CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] +// CHECK32-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] +// CHECK32-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] +// CHECK32-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] +// CHECK32-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] +// CHECK32-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] +// CHECK32-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1 +// CHECK32-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: store i32 -2147483522, i32* [[I]], align 4 +// CHECK32-NEXT: ret void +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z12test_precondv +// CHECK32-SAME: () #[[ATTR0]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I4:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[I6:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[I7:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: store i8 0, i8* [[A]], align 1 +// CHECK32-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 +// CHECK32-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK32-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] +// CHECK32-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 +// CHECK32-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 +// CHECK32-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK32-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK32-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK32-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 +// CHECK32-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 +// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 +// CHECK32-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK32: simd.if.then: +// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 +// CHECK32-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 +// CHECK32-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 +// CHECK32-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0 +// CHECK32-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK32: omp_if.then: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK32-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !14 +// CHECK32-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32 +// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK32-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] +// CHECK32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 +// CHECK32-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !8, !llvm.access.group !14 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK32-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK32: omp_if.else: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] +// CHECK32: omp.inner.for.cond13: +// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK32-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] +// CHECK32: omp.inner.for.body15: +// CHECK32-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK32-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] +// CHECK32-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK32-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] +// CHECK32: omp.body.continue20: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] +// CHECK32: omp.inner.for.inc21: +// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK32-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK32: omp.inner.for.end23: +// CHECK32-NEXT: br label [[OMP_IF_END]] +// CHECK32: omp_if.end: +// CHECK32-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32 +// CHECK32-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32 +// CHECK32-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] +// CHECK32-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 +// CHECK32-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 +// CHECK32-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 +// CHECK32-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 +// CHECK32-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] +// CHECK32-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 +// CHECK32-NEXT: store i8 [[CONV32]], i8* [[I]], align 1 +// CHECK32-NEXT: br label [[SIMD_IF_END]] +// CHECK32: simd.if.end: +// CHECK32-NEXT: ret void +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z4fintv +// CHECK32-SAME: () #[[ATTR0]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK32-NEXT: ret i32 [[CALL]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v +// CHECK32-SAME: () #[[ATTR0]] comdat { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK32-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: store i32 100, i32* [[I]], align 4 +// CHECK32-NEXT: ret i32 0 +// diff --git a/clang/test/OpenMP/nvptx_allocate_codegen.cpp b/clang/test/OpenMP/nvptx_allocate_codegen.cpp --- a/clang/test/OpenMP/nvptx_allocate_codegen.cpp +++ b/clang/test/OpenMP/nvptx_allocate_codegen.cpp @@ -91,7 +91,7 @@ // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK1-NEXT: store i32 2, i32* @_ZZ4mainE1a, align 4 // CHECK1-NEXT: store double 3.000000e+00, double* [[B]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooIiET_v() #[[ATTR7:[0-9]+]] +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooIiET_v() #[[ATTR7:[0-9]+]] // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -117,7 +117,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -127,12 +127,12 @@ // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[BAR_A]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double // CHECK1-NEXT: store double [[CONV]], double* addrspacecast (double addrspace(3)* @bar_b to double*), align 8 -// CHECK1-NEXT: call void @_Z3bazRf(float* noundef nonnull align 4 dereferenceable(4) [[BAR_A]]) #[[ATTR7]] +// CHECK1-NEXT: call void @_Z3bazRf(float* nonnull align 4 dereferenceable(4) [[BAR_A]]) #[[ATTR7]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_data_sharing.cpp b/clang/test/OpenMP/nvptx_data_sharing.cpp --- a/clang/test/OpenMP/nvptx_data_sharing.cpp +++ b/clang/test/OpenMP/nvptx_data_sharing.cpp @@ -70,7 +70,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -84,7 +84,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -103,7 +103,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -125,7 +125,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_declare_target_var_ctor_dtor_codegen.cpp b/clang/test/OpenMP/nvptx_declare_target_var_ctor_dtor_codegen.cpp --- a/clang/test/OpenMP/nvptx_declare_target_var_ctor_dtor_codegen.cpp +++ b/clang/test/OpenMP/nvptx_declare_target_var_ctor_dtor_codegen.cpp @@ -34,20 +34,20 @@ #pragma omp declare target (bar) int caz() { return 0; } -// DEVICE-DAG: define{{ protected | }}noundef i32 [[FOO:@.*foo.*]]() -// DEVICE-DAG: define{{ protected | }}noundef i32 [[BAR:@.*bar.*]]() -// DEVICE-DAG: define{{ protected | }}noundef i32 [[BAZ:@.*baz.*]]() -// DEVICE-DAG: define{{ protected | }}noundef i32 [[DOO:@.*doo.*]]() -// DEVICE-DAG: define{{ protected | }}noundef i32 [[CAR:@.*car.*]]() -// DEVICE-DAG: define{{ protected | }}noundef i32 [[CAZ:@.*caz.*]]() +// DEVICE-DAG: define{{ protected | }}i32 [[FOO:@.*foo.*]]() +// DEVICE-DAG: define{{ protected | }}i32 [[BAR:@.*bar.*]]() +// DEVICE-DAG: define{{ protected | }}i32 [[BAZ:@.*baz.*]]() +// DEVICE-DAG: define{{ protected | }}i32 [[DOO:@.*doo.*]]() +// DEVICE-DAG: define{{ protected | }}i32 [[CAR:@.*car.*]]() +// DEVICE-DAG: define{{ protected | }}i32 [[CAZ:@.*caz.*]]() static int c = foo() + bar() + baz(); #pragma omp declare target (c) // HOST-DAG: @[[C_CTOR:__omp_offloading__.+_c_l44_ctor]] = private constant i8 0 // DEVICE-DAG: define weak_odr void [[C_CTOR:@__omp_offloading__.+_c_l44_ctor]]() -// DEVICE-DAG: call noundef i32 [[FOO]]() -// DEVICE-DAG: call noundef i32 [[BAR]]() -// DEVICE-DAG: call noundef i32 [[BAZ]]() +// DEVICE-DAG: call i32 [[FOO]]() +// DEVICE-DAG: call i32 [[BAR]]() +// DEVICE-DAG: call i32 [[BAZ]]() // DEVICE-DAG: ret void struct S { @@ -62,9 +62,9 @@ #pragma omp end declare target // HOST-DAG: @[[CD_CTOR:__omp_offloading__.+_cd_l61_ctor]] = private constant i8 0 // DEVICE-DAG: define weak_odr void [[CD_CTOR:@__omp_offloading__.+_cd_l61_ctor]]() -// DEVICE-DAG: call noundef i32 [[DOO]]() -// DEVICE-DAG: call noundef i32 [[CAR]]() -// DEVICE-DAG: call noundef i32 [[CAZ]]() +// DEVICE-DAG: call i32 [[DOO]]() +// DEVICE-DAG: call i32 [[CAR]]() +// DEVICE-DAG: call i32 [[CAZ]]() // DEVICE-DAG: ret void // HOST-DAG: @[[CD_DTOR:__omp_offloading__.+_cd_l61_dtor]] = private constant i8 0 @@ -89,7 +89,7 @@ return 0; } -// DEVICE-DAG: define weak{{.*}} void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-7]](i32* noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}} +// DEVICE-DAG: define weak{{.*}} void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-7]](i32* nonnull align {{[0-9]+}} dereferenceable{{[^,]*}} // DEVICE-DAG: [[C:%.+]] = load i32, i32* [[C_ADDR]], // DEVICE-DAG: store i32 [[C]], i32* % diff --git a/clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp b/clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp --- a/clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp +++ b/clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp @@ -8,8 +8,8 @@ // CHECK-DAG: @_Z3bazv // CHECK-DAG: define{{.*}} @"_Z53bar$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv" // CHECK-DAG: define{{.*}} @"_Z53baz$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv" -// CHECK-DAG: call noundef i32 @"_Z53bar$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv"() -// CHECK-DAG: call noundef i32 @"_Z53baz$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv"() +// CHECK-DAG: call i32 @"_Z53bar$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv"() +// CHECK-DAG: call i32 @"_Z53baz$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv"() #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp b/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp --- a/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp +++ b/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp @@ -25,7 +25,7 @@ #endif // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19 -// CHECK4-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -64,7 +64,7 @@ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -230,7 +230,7 @@ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -310,23 +310,23 @@ // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I6]]) #[[ATTR8:[0-9]+]] -// CHECK4-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP1]]) #[[ATTR8]] +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I6]]) #[[ATTR7:[0-9]+]] +// CHECK4-NEXT: [[CALL9:%.*]] = call i32 @_Z3fooPi(i32* [[TMP1]]) #[[ATTR7]] // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[CALL]], [[CALL9]] // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B4]], i64 0, i64 [[IDXPROM]] -// CHECK4-NEXT: [[CALL11:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX]]) #[[ATTR8]] +// CHECK4-NEXT: [[CALL11:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX]]) #[[ATTR7]] // CHECK4-NEXT: [[ADD12:%.*]] = add nsw i32 [[ADD10]], [[CALL11]] // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP20]] to i64 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[C5]], i64 0, i64 [[IDXPROM13]] -// CHECK4-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX14]]) #[[ATTR8]] +// CHECK4-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX14]]) #[[ATTR7]] // CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD12]], [[CALL15]] // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP21]] to i64 // CHECK4-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i64 0, i64 [[IDXPROM17]] -// CHECK4-NEXT: [[CALL19:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX18]]) #[[ATTR8]] +// CHECK4-NEXT: [[CALL19:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX18]]) #[[ATTR7]] // CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[ADD16]], [[CALL19]] // CHECK4-NEXT: store i32 [[ADD20]], i32* [[TMP1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -359,7 +359,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19 -// CHECK5-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -396,7 +396,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -559,7 +559,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -636,20 +636,20 @@ // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I5]]) #[[ATTR8:[0-9]+]] -// CHECK5-NEXT: [[CALL7:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP1]]) #[[ATTR8]] +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I5]]) #[[ATTR7:[0-9]+]] +// CHECK5-NEXT: [[CALL7:%.*]] = call i32 @_Z3fooPi(i32* [[TMP1]]) #[[ATTR7]] // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[CALL]], [[CALL7]] // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B3]], i32 0, i32 [[TMP19]] -// CHECK5-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX]]) #[[ATTR8]] +// CHECK5-NEXT: [[CALL9:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX]]) #[[ATTR7]] // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CALL9]] // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[C4]], i32 0, i32 [[TMP20]] -// CHECK5-NEXT: [[CALL12:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX11]]) #[[ATTR8]] +// CHECK5-NEXT: [[CALL12:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX11]]) #[[ATTR7]] // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD10]], [[CALL12]] // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 // CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i32 0, i32 [[TMP21]] -// CHECK5-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX14]]) #[[ATTR8]] +// CHECK5-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX14]]) #[[ATTR7]] // CHECK5-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD13]], [[CALL15]] // CHECK5-NEXT: store i32 [[ADD16]], i32* [[TMP1]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -680,3 +680,326 @@ // CHECK5: omp.precond.end: // CHECK5-NEXT: ret void // +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19 +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[C]], [10 x i32]** [[C_ADDR]], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[C_ADDR]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[D_ADDR]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) +// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 +// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK6: user_code.entry: +// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[ARGC_CASTED]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK6-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]], [10 x i32]* [[TMP1]], i32* [[TMP2]], i32 [[TMP7]], [10 x i32]* [[TMP3]]) #[[ATTR5:[0-9]+]] +// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK6-NEXT: ret void +// CHECK6: worker.exit: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[B4:%.*]] = alloca [10 x i32], align 4 +// CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [7 x i8*], align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[C]], [10 x i32]** [[C_ADDR]], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[C_ADDR]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[D_ADDR]], align 4 +// CHECK6-NEXT: [[C1:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i32 40) +// CHECK6-NEXT: [[C_ON_STACK:%.*]] = bitcast i8* [[C1]] to [10 x i32]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast [10 x i32]* [[B4]] to i8* +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false) +// CHECK6-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK6-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP17]], [[ADD]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [7 x i8*], [7 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP19]] to i8* +// CHECK6-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [7 x i8*], [7 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP24:%.*]] = inttoptr i32 [[TMP20]] to i8* +// CHECK6-NEXT: store i8* [[TMP24]], i8** [[TMP23]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [7 x i8*], [7 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP26:%.*]] = bitcast i32* [[ARGC_ADDR]] to i8* +// CHECK6-NEXT: store i8* [[TMP26]], i8** [[TMP25]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [7 x i8*], [7 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast i32* [[TMP2]] to i8* +// CHECK6-NEXT: store i8* [[TMP28]], i8** [[TMP27]], align 4 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [7 x i8*], [7 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP30:%.*]] = bitcast [10 x i32]* [[B4]] to i8* +// CHECK6-NEXT: store i8* [[TMP30]], i8** [[TMP29]], align 4 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [7 x i8*], [7 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 5 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast [10 x i32]* [[C_ON_STACK]] to i8* +// CHECK6-NEXT: store i8* [[TMP32]], i8** [[TMP31]], align 4 +// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [7 x i8*], [7 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 6 +// CHECK6-NEXT: [[TMP34:%.*]] = bitcast [10 x i32]* [[TMP3]] to i8* +// CHECK6-NEXT: store i8* [[TMP34]], i8** [[TMP33]], align 4 +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP35]], 0 +// CHECK6-NEXT: [[TMP36:%.*]] = zext i1 [[TOBOOL]] to i32 +// CHECK6-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP37]], align 4 +// CHECK6-NEXT: [[TMP39:%.*]] = bitcast [7 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP38]], i32 [[TMP36]], i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32*, i32*, [10 x i32]*, [10 x i32]*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP39]], i32 7) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP40]], [[TMP41]] +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP42]], [[TMP43]] +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP44]], [[TMP45]] +// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP46]], [[TMP47]] +// CHECK6-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] +// CHECK6: cond.true12: +// CHECK6-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END14:%.*]] +// CHECK6: cond.false13: +// CHECK6-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END14]] +// CHECK6: cond.end14: +// CHECK6-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP48]], [[COND_TRUE12]] ], [ [[TMP49]], [[COND_FALSE13]] ] +// CHECK6-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP50:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP50]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP51:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP52:%.*]] = load i32, i32* [[TMP51]], align 4 +// CHECK6-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP52]]) +// CHECK6-NEXT: [[TMP53:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0 +// CHECK6-NEXT: br i1 [[TMP54]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP55:%.*]] = bitcast [10 x i32]* [[TMP1]] to i8* +// CHECK6-NEXT: [[TMP56:%.*]] = bitcast [10 x i32]* [[C_ON_STACK]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP55]], i8* align 4 [[TMP56]], i32 40, i1 false) +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: call void @__kmpc_free_shared(i8* [[C1]], i32 40) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[B3:%.*]] = alloca [10 x i32], align 4 +// CHECK6-NEXT: [[C4:%.*]] = alloca [10 x i32], align 4 +// CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[C]], [10 x i32]** [[C_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[C_ADDR]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load [10 x i32]*, [10 x i32]** [[D_ADDR]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[B3]] to i8* +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 40, i1 false) +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP14]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp ule i32 [[TMP16]], [[TMP17]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I5]]) #[[ATTR7:[0-9]+]] +// CHECK6-NEXT: [[CALL7:%.*]] = call i32 @_Z3fooPi(i32* [[TMP1]]) #[[ATTR7]] +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[CALL]], [[CALL7]] +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B3]], i32 0, i32 [[TMP19]] +// CHECK6-NEXT: [[CALL9:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX]]) #[[ATTR7]] +// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CALL9]] +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[C4]], i32 0, i32 [[TMP20]] +// CHECK6-NEXT: [[CALL12:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX11]]) #[[ATTR7]] +// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD10]], [[CALL12]] +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK6-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i32 0, i32 [[TMP21]] +// CHECK6-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX14]]) #[[ATTR7]] +// CHECK6-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD13]], [[CALL15]] +// CHECK6-NEXT: store i32 [[ADD16]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK6-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK6-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP25]]) +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 +// CHECK6-NEXT: br i1 [[TMP27]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK6: .omp.lastprivate.then: +// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [10 x i32]* [[TMP3]] to i8* +// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [10 x i32]* [[C4]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i32 40, i1 false) +// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK6: .omp.lastprivate.done: +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_lambda_capturing.cpp b/clang/test/OpenMP/nvptx_lambda_capturing.cpp --- a/clang/test/OpenMP/nvptx_lambda_capturing.cpp +++ b/clang/test/OpenMP/nvptx_lambda_capturing.cpp @@ -854,7 +854,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (%struct.S* [[THIS:%.*]], %class.anon* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca %class.anon*, align 8 @@ -879,7 +879,7 @@ // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP6]], i32 0, i32 0 // CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* noundef nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR7:[0-9]+]] +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR7:[0-9]+]] // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -887,7 +887,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv -// CHECK2-SAME: (%class.anon* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%class.anon* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 // CHECK2-NEXT: store %class.anon* [[THIS]], %class.anon** [[THIS_ADDR]], align 8 @@ -900,7 +900,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (%struct.S* [[THIS:%.*]], %class.anon* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca %class.anon*, align 8 @@ -932,7 +932,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], %class.anon* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -957,12 +957,12 @@ // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP5]], i32 0, i32 0 // CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* noundef nonnull align 8 dereferenceable(8) [[TMP7]]) #[[ATTR7]] +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(8) [[TMP7]]) #[[ATTR7]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK2-SAME: (i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -1024,7 +1024,7 @@ // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP12]], i32 0, i32 4 // CHECK2-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP4]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR7]] +// CHECK2-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0* nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR7]] // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -1032,7 +1032,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -1094,7 +1094,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1162,12 +1162,12 @@ // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP14]], i32 0, i32 4 // CHECK2-NEXT: store i32* [[A10]], i32** [[TMP21]], align 8 // CHECK2-NEXT: [[TMP22:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP4]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(40) [[TMP22]]) #[[ATTR7]] +// CHECK2-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0* nonnull align 8 dereferenceable(40) [[TMP22]]) #[[ATTR7]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 -// CHECK2-SAME: (%class.anon* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%class.anon* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_ADDR:%.*]] = alloca %class.anon*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca %class.anon*, align 8 @@ -1193,7 +1193,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %class.anon* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1213,12 +1213,12 @@ // CHECK2-NEXT: store %class.anon* [[T1]], %class.anon** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR7]] +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR7]] // CHECK2-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK3-SAME: (i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -1280,7 +1280,7 @@ // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP12]], i32 0, i32 4 // CHECK3-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8 // CHECK3-NEXT: [[TMP20:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR7:[0-9]+]] +// CHECK3-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR7:[0-9]+]] // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -1288,7 +1288,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -1350,7 +1350,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1418,12 +1418,12 @@ // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP14]], i32 0, i32 4 // CHECK3-NEXT: store i32* [[A10]], i32** [[TMP21]], align 8 // CHECK3-NEXT: [[TMP22:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 8 dereferenceable(40) [[TMP22]]) #[[ATTR7]] +// CHECK3-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP22]]) #[[ATTR7]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 @@ -1448,7 +1448,7 @@ // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP6]], i32 0, i32 0 // CHECK3-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR7]] +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR7]] // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -1456,7 +1456,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv -// CHECK3-SAME: (%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -1469,7 +1469,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 @@ -1501,7 +1501,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1526,12 +1526,12 @@ // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP5]], i32 0, i32 0 // CHECK3-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[TMP7]]) #[[ATTR7]] +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP7]]) #[[ATTR7]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 -// CHECK3-SAME: (%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK3-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 @@ -1557,7 +1557,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1577,6 +1577,370 @@ // CHECK3-NEXT: store %class.anon.0* [[T1]], %class.anon.0** [[_TMP2]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR7]] +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR7]] // CHECK3-NEXT: ret void // +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 +// CHECK4-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[L_ADDR:%.*]] = alloca %class.anon*, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[_TMP2:%.*]] = alloca %class.anon*, align 8 +// CHECK4-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK4-NEXT: [[_TMP4:%.*]] = alloca %class.anon*, align 8 +// CHECK4-NEXT: [[B5:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[C7:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon* [[L]], %class.anon** [[L_ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C_ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load %class.anon*, %class.anon** [[L_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 +// CHECK4-NEXT: store i32* [[TMP1]], i32** [[_TMP1]], align 8 +// CHECK4-NEXT: store %class.anon* [[TMP3]], %class.anon** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP5:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = bitcast %class.anon* [[L3]] to i8* +// CHECK4-NEXT: [[TMP7:%.*]] = bitcast %class.anon* [[TMP5]] to i8* +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP6]], i8* align 8 [[TMP7]], i64 40, i1 false) +// CHECK4-NEXT: store %class.anon* [[L3]], %class.anon** [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK4-NEXT: store i32 [[TMP9]], i32* [[B5]], align 4 +// CHECK4-NEXT: store i32* [[B5]], i32** [[_TMP6]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK4-NEXT: store i32 [[TMP11]], i32* [[C7]], align 4 +// CHECK4-NEXT: store i32* [[C7]], i32** [[_TMP8]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP12]], i32 0, i32 0 +// CHECK4-NEXT: store i32* [[CONV]], i32** [[TMP13]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP12]], i32 0, i32 1 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[_TMP6]], align 8 +// CHECK4-NEXT: store i32* [[TMP15]], i32** [[TMP14]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP12]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[_TMP8]], align 8 +// CHECK4-NEXT: store i32* [[TMP17]], i32** [[TMP16]], align 8 +// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP12]], i32 0, i32 3 +// CHECK4-NEXT: store i32** [[D_ADDR]], i32*** [[TMP18]], align 8 +// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP12]], i32 0, i32 4 +// CHECK4-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8 +// CHECK4-NEXT: [[TMP20:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 +// CHECK4-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR7:[0-9]+]] +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[L_ADDR:%.*]] = alloca %class.anon*, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[_TMP2:%.*]] = alloca %class.anon*, align 8 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [6 x i8*], align 8 +// CHECK4-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon* [[L]], %class.anon** [[L_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[C_ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load %class.anon*, %class.anon** [[L_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 +// CHECK4-NEXT: store i32* [[TMP2]], i32** [[_TMP1]], align 8 +// CHECK4-NEXT: store %class.anon* [[TMP4]], %class.anon** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[D_ADDR]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP12:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 +// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 +// CHECK4-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP7]] to i8* +// CHECK4-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 +// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 +// CHECK4-NEXT: [[TMP16:%.*]] = bitcast i32* [[TMP8]] to i8* +// CHECK4-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 +// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 3 +// CHECK4-NEXT: [[TMP18:%.*]] = bitcast i32* [[TMP9]] to i8* +// CHECK4-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8 +// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 4 +// CHECK4-NEXT: [[TMP20:%.*]] = bitcast i32* [[TMP3]] to i8* +// CHECK4-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8 +// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 5 +// CHECK4-NEXT: [[TMP22:%.*]] = bitcast %class.anon* [[TMP10]] to i8* +// CHECK4-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8 +// CHECK4-NEXT: [[TMP23:%.*]] = bitcast [6 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i32*, i32*, i32*, i32*, %class.anon*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP23]], i64 6) +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[L_ADDR:%.*]] = alloca %class.anon*, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[_TMP2:%.*]] = alloca %class.anon*, align 8 +// CHECK4-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK4-NEXT: [[_TMP4:%.*]] = alloca %class.anon*, align 8 +// CHECK4-NEXT: [[ARGC5:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[B6:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[C8:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP9:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[A10:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon* [[L]], %class.anon** [[L_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[C_ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load %class.anon*, %class.anon** [[L_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 +// CHECK4-NEXT: store i32* [[TMP2]], i32** [[_TMP1]], align 8 +// CHECK4-NEXT: store %class.anon* [[TMP4]], %class.anon** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = bitcast %class.anon* [[L3]] to i8* +// CHECK4-NEXT: [[TMP7:%.*]] = bitcast %class.anon* [[TMP5]] to i8* +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP6]], i8* align 8 [[TMP7]], i64 40, i1 false) +// CHECK4-NEXT: store %class.anon* [[L3]], %class.anon** [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARGC5]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK4-NEXT: store i32 [[TMP10]], i32* [[B6]], align 4 +// CHECK4-NEXT: store i32* [[B6]], i32** [[_TMP7]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK4-NEXT: store i32 [[TMP12]], i32* [[C8]], align 4 +// CHECK4-NEXT: store i32* [[C8]], i32** [[_TMP9]], align 8 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK4-NEXT: store i32 [[TMP13]], i32* [[A10]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP14]], i32 0, i32 0 +// CHECK4-NEXT: store i32* [[ARGC5]], i32** [[TMP15]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP14]], i32 0, i32 1 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[_TMP7]], align 8 +// CHECK4-NEXT: store i32* [[TMP17]], i32** [[TMP16]], align 8 +// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP14]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32*, i32** [[_TMP9]], align 8 +// CHECK4-NEXT: store i32* [[TMP19]], i32** [[TMP18]], align 8 +// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP14]], i32 0, i32 3 +// CHECK4-NEXT: store i32** [[D_ADDR]], i32*** [[TMP20]], align 8 +// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP14]], i32 0, i32 4 +// CHECK4-NEXT: store i32* [[A10]], i32** [[TMP21]], align 8 +// CHECK4-NEXT: [[TMP22:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 +// CHECK4-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP22]]) #[[ATTR7]] +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 +// CHECK4-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK4-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK4-NEXT: [[_TMP2:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load %class.anon.0*, %class.anon.0** [[L_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP3:%.*]] = load %class.anon.0*, %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = bitcast %class.anon.0* [[L1]] to i8* +// CHECK4-NEXT: [[TMP5:%.*]] = bitcast %class.anon.0* [[TMP3]] to i8* +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 8, i1 false) +// CHECK4-NEXT: store %class.anon.0* [[L1]], %class.anon.0** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP6]], i32 0, i32 0 +// CHECK4-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR7]] +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv +// CHECK4-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[TMP0]], align 8 +// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[TMP1]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK4-NEXT: ret i32 [[TMP2]] +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 +// CHECK4-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK4-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load %class.anon.0*, %class.anon.0** [[L_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK4-NEXT: [[TMP4:%.*]] = load %class.anon.0*, %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast %class.anon.0* [[TMP4]] to i8* +// CHECK4-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, %struct.S*, %class.anon.0*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP9]], i64 2) +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR4]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK4-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK4-NEXT: [[_TMP2:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load %class.anon.0*, %class.anon.0** [[L_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load %class.anon.0*, %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = bitcast %class.anon.0* [[L1]] to i8* +// CHECK4-NEXT: [[TMP4:%.*]] = bitcast %class.anon.0* [[TMP2]] to i8* +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) +// CHECK4-NEXT: store %class.anon.0* [[L1]], %class.anon.0** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP5]], i32 0, i32 0 +// CHECK4-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP7]]) #[[ATTR7]] +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 +// CHECK4-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[T_ADDR:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: store %class.anon.0* [[T]], %class.anon.0** [[T_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load %class.anon.0*, %class.anon.0** [[T_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon.0* [[TMP0]], %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK4-NEXT: [[TMP3:%.*]] = load %class.anon.0*, %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP5:%.*]] = bitcast %class.anon.0* [[TMP3]] to i8* +// CHECK4-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, %class.anon.0*)* @__omp_outlined__2 to i8*), i8* null, i8** [[TMP6]], i64 1) +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__2 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR4]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[T_ADDR:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: [[T1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK4-NEXT: [[_TMP2:%.*]] = alloca %class.anon.0*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store %class.anon.0* [[T]], %class.anon.0** [[T_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load %class.anon.0*, %class.anon.0** [[T_ADDR]], align 8 +// CHECK4-NEXT: store %class.anon.0* [[TMP0]], %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load %class.anon.0*, %class.anon.0** [[TMP]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = bitcast %class.anon.0* [[T1]] to i8* +// CHECK4-NEXT: [[TMP3:%.*]] = bitcast %class.anon.0* [[TMP1]] to i8* +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP2]], i8* align 8 [[TMP3]], i64 8, i1 false) +// CHECK4-NEXT: store %class.anon.0* [[T1]], %class.anon.0** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR7]] +// CHECK4-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp b/clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp --- a/clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp +++ b/clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp @@ -43,7 +43,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -78,7 +78,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -89,7 +89,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -121,7 +121,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -156,7 +156,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -167,7 +167,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -180,3 +180,81 @@ // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3:[0-9]+]] // CHECK2-NEXT: ret void // +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 +// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK3-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP2]], i32 0) +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: call void @_Z3usev() #[[ATTR8:[0-9]+]] +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@_Z3usev +// CHECK3-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) +// CHECK3-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP1]], i32 0) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 +// CHECK3-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: call void @_Z3usev() #[[ATTR8]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: call void @_Z4workv() #[[ATTR8]] +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper +// CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 +// CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) +// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp b/clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp --- a/clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp +++ b/clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp @@ -34,7 +34,7 @@ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -45,7 +45,7 @@ // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK1-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR7:[0-9]+]] +// CHECK1-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7:[0-9]+]] // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8 @@ -58,7 +58,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3usePi -// CHECK1-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -73,7 +73,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -82,12 +82,12 @@ // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR7]] +// CHECK1-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -106,7 +106,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -116,12 +116,12 @@ // CHECK1-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 8 -// CHECK1-NEXT: call void @_Z4workPi(i32* noundef [[TMP1]]) #[[ATTR7]] +// CHECK1-NEXT: call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR7]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z4workPi -// CHECK1-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4 @@ -130,7 +130,7 @@ // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* -// CHECK1-NEXT: call void @__atomic_load(i64 noundef 4, i8* noundef [[TMP1]], i8* noundef [[TMP2]], i32 noundef 0) #[[ATTR7]] +// CHECK1-NEXT: call void @__atomic_load(i64 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR7]] // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK1: atomic_cont: // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4 @@ -139,14 +139,14 @@ // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8* -// CHECK1-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 4, i8* noundef [[TMP4]], i8* noundef [[TMP5]], i8* noundef [[TMP6]], i32 noundef 0, i32 noundef 0) #[[ATTR7]] +// CHECK1-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR7]] // CHECK1-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK1: atomic_exit: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -165,7 +165,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -176,7 +176,7 @@ // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2: user_code.entry: // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK2-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR7:[0-9]+]] +// CHECK2-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7:[0-9]+]] // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 @@ -189,7 +189,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3usePi -// CHECK2-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -204,7 +204,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -213,12 +213,12 @@ // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK2-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4 -// CHECK2-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR7]] +// CHECK2-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -237,7 +237,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -247,12 +247,12 @@ // CHECK2-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 4 -// CHECK2-NEXT: call void @_Z4workPi(i32* noundef [[TMP1]]) #[[ATTR7]] +// CHECK2-NEXT: call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR7]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_Z4workPi -// CHECK2-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4 @@ -261,7 +261,7 @@ // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* -// CHECK2-NEXT: call void @__atomic_load(i32 noundef 4, i8* noundef [[TMP1]], i8* noundef [[TMP2]], i32 noundef 0) #[[ATTR7]] +// CHECK2-NEXT: call void @__atomic_load(i32 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR7]] // CHECK2-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK2: atomic_cont: // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4 @@ -270,14 +270,14 @@ // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8* -// CHECK2-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i32 noundef 4, i8* noundef [[TMP4]], i8* noundef [[TMP5]], i8* noundef [[TMP6]], i32 noundef 0, i32 noundef 0) #[[ATTR7]] +// CHECK2-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR7]] // CHECK2-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK2: atomic_exit: // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -294,3 +294,134 @@ // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32** [[TMP5]]) #[[ATTR4]] // CHECK2-NEXT: ret void // +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25 +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK3-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK3-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7:[0-9]+]] +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP5]], i32 1) +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@_Z3usePi +// CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK3-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP2:%.*]] = bitcast i32** [[C_ADDR]] to i8* +// CHECK3-NEXT: store i8* [[TMP2]], i8** [[TMP1]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32*, i32*, i32**)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP3]], i32 1) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4 +// CHECK3-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR7]] +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined___wrapper +// CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 +// CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) +// CHECK3-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** +// CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32**, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 4 +// CHECK3-NEXT: call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR7]] +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@_Z4workPi +// CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK3-NEXT: [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* +// CHECK3-NEXT: call void @__atomic_load(i32 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR7]] +// CHECK3-NEXT: br label [[ATOMIC_CONT:%.*]] +// CHECK3: atomic_cont: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[ATOMIC_TEMP1]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK3-NEXT: [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* +// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8* +// CHECK3-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR7]] +// CHECK3-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] +// CHECK3: atomic_exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper +// CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 +// CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) +// CHECK3-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*** +// CHECK3-NEXT: [[TMP5:%.*]] = load i32**, i32*** [[TMP4]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32** [[TMP5]]) #[[ATTR4]] +// CHECK3-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_parallel_codegen.cpp b/clang/test/OpenMP/nvptx_parallel_codegen.cpp --- a/clang/test/OpenMP/nvptx_parallel_codegen.cpp +++ b/clang/test/OpenMP/nvptx_parallel_codegen.cpp @@ -74,7 +74,7 @@ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 @@ -103,7 +103,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -115,7 +115,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -130,7 +130,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -142,7 +142,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -157,7 +157,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -169,7 +169,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -184,7 +184,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43 -// CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -228,7 +228,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -243,7 +243,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -258,7 +258,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -289,7 +289,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -331,7 +331,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -350,7 +350,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 -// CHECK2-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 @@ -378,7 +378,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -390,7 +390,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -405,7 +405,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -417,7 +417,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -432,7 +432,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -444,7 +444,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -459,7 +459,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43 -// CHECK2-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -501,7 +501,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -516,7 +516,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -531,7 +531,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55 -// CHECK2-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -561,7 +561,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -603,7 +603,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp b/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp --- a/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp @@ -33,7 +33,7 @@ #endif // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13 -// CHECK-SAME: (i64 noundef [[N:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-SAME: (i64 [[N:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -71,7 +71,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -161,7 +161,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_target_firstprivate_codegen.cpp b/clang/test/OpenMP/nvptx_target_firstprivate_codegen.cpp --- a/clang/test/OpenMP/nvptx_target_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_firstprivate_codegen.cpp @@ -33,7 +33,7 @@ b[a] += e.X; } - // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}([10 x float] addrspace(1)* noalias noundef [[B_IN:%.+]], i{{[0-9]+}} noundef [[A_IN:%.+]], [[TTII]]* noalias noundef [[E_IN:%.+]]) + // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}([10 x float] addrspace(1)* noalias [[B_IN:%.+]], i{{[0-9]+}} [[A_IN:%.+]], [[TTII]]* noalias [[E_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK-NOT: alloca [[TTII]], // TCHECK: alloca i{{[0-9]+}}, @@ -95,7 +95,7 @@ ptr[0]++; } - // TCHECK: define weak_odr void @__omp_offloading_{{.+}}(double* noundef [[PTR_IN:%.+]]) + // TCHECK: define weak_odr void @__omp_offloading_{{.+}}(double* [[PTR_IN:%.+]]) // TCHECK: [[PTR_ADDR:%.+]] = alloca double*, // TCHECK-NOT: alloca double*, // TCHECK: store double* [[PTR_IN]], double** [[PTR_ADDR]], @@ -179,7 +179,7 @@ return (int)b; } - // TCHECK: define internal void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i{{[0-9]+}} noundef [[B_IN:%.+]]) + // TCHECK: define internal void @__omp_offloading_{{.+}}([[S1]]* [[TH:%.+]], i{{[0-9]+}} [[B_IN:%.+]]) // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*, // TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK-NOT: alloca i{{[0-9]+}}, @@ -211,7 +211,7 @@ // template -// TCHECK: define internal void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} noundef [[B_IN:%.+]]) +// TCHECK: define internal void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*, // TCHECK-NOT: alloca i{{[0-9]+}}, diff --git a/clang/test/OpenMP/nvptx_target_parallel_codegen.cpp b/clang/test/OpenMP/nvptx_target_parallel_codegen.cpp --- a/clang/test/OpenMP/nvptx_target_parallel_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_parallel_codegen.cpp @@ -52,7 +52,7 @@ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK1-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -75,7 +75,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -93,7 +93,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 @@ -128,7 +128,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -159,7 +159,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK2-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -182,7 +182,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -200,7 +200,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -235,7 +235,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -264,3 +264,431 @@ // CHECK2-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: ret void // +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 +// CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8* +// CHECK3-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* +// CHECK3-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 +// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 +// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 +// CHECK3-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 +// CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1) +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK4-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 +// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8* +// CHECK4-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 +// CHECK4-NEXT: [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* +// CHECK4-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3) +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 +// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 +// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 +// CHECK4-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 +// CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) +// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK5: user_code.entry: +// CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* +// CHECK5-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) +// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK5-NEXT: ret void +// CHECK5: worker.exit: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK5-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 +// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK5: user_code.entry: +// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK5-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8* +// CHECK5-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* +// CHECK5-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) +// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK5-NEXT: ret void +// CHECK5: worker.exit: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 +// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 +// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 +// CHECK5-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 +// CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) +// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK6: user_code.entry: +// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* +// CHECK6-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) +// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK6-NEXT: ret void +// CHECK6: worker.exit: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK6-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 +// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK6: user_code.entry: +// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK6-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i16* [[TMP1]] to i8* +// CHECK6-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP10:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* +// CHECK6-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) +// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK6-NEXT: ret void +// CHECK6: worker.exit: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 +// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 +// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 +// CHECK6-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp --- a/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp @@ -47,7 +47,7 @@ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 -// CHECK1-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -70,7 +70,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -88,7 +88,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 @@ -127,7 +127,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -158,7 +158,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 -// CHECK2-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -181,7 +181,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -199,7 +199,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -237,7 +237,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -266,3 +266,444 @@ // CHECK2-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: ret void // +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 +// CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8* +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* +// CHECK3-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP12]], i32 3) +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 +// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 +// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 +// CHECK3-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 +// CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1) +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK4-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK4-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 +// CHECK4-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8* +// CHECK4-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 +// CHECK4-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* +// CHECK4-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP12]], i64 3) +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 +// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 +// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 +// CHECK4-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 +// CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) +// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK5: user_code.entry: +// CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* +// CHECK5-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) +// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK5-NEXT: ret void +// CHECK5: worker.exit: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK5-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK5-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 +// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK5: user_code.entry: +// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK5-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8* +// CHECK5-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* +// CHECK5-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP12]], i32 3) +// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK5-NEXT: ret void +// CHECK5: worker.exit: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 +// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 +// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 +// CHECK5-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 +// CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) +// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK6: user_code.entry: +// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* +// CHECK6-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) +// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK6-NEXT: ret void +// CHECK6: worker.exit: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 +// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK6-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK6-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 +// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK6: user_code.entry: +// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK6-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8* +// CHECK6-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* +// CHECK6-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP12]], i32 3) +// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK6-NEXT: ret void +// CHECK6: worker.exit: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 +// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 +// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 +// CHECK6-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp b/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp --- a/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp @@ -82,7 +82,7 @@ // // Reduction function -// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* %0, i8* %1) // CHECK: [[VAR_RHS_REF:%.+]] = getelementptr inbounds [[RLT]], [[RLT]]* [[RED_LIST_RHS:%.+]], i{{32|64}} 0, i{{32|64}} 0 // CHECK: [[VAR_RHS_VOID:%.+]] = load i8*, i8** [[VAR_RHS_REF]], // CHECK: [[VAR_RHS:%.+]] = bitcast i8* [[VAR_RHS_VOID]] to double* @@ -99,7 +99,7 @@ // // Shuffle and reduce function -// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* noundef %0, i16 noundef {{.*}}, i16 noundef {{.*}}, i16 noundef {{.*}}) +// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* %0, i16 {{.*}}, i16 {{.*}}, i16 {{.*}}) // CHECK: [[REMOTE_RED_LIST:%.+]] = alloca [[RLT]], align // CHECK: [[REMOTE_ELT:%.+]] = alloca double // @@ -176,7 +176,7 @@ // // Inter warp copy function -// CHECK: define internal void [[WARP_COPY_FN]](i8* noundef %0, i32 noundef %1) +// CHECK: define internal void [[WARP_COPY_FN]](i8* %0, i32 %1) // CHECK-DAG: [[LANEID:%.+]] = and i32 {{.+}}, 31 // CHECK-DAG: [[WARPID:%.+]] = ashr i32 {{.+}}, 5 // CHECK-DAG: [[RED_LIST:%.+]] = bitcast i8* {{.+}} to [[RLT]]* @@ -274,7 +274,7 @@ // // Reduction function -// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* %0, i8* %1) // CHECK: [[VAR1_RHS_REF:%.+]] = getelementptr inbounds [[RLT]], [[RLT]]* [[RED_LIST_RHS:%.+]], i{{32|64}} 0, i{{32|64}} 0 // CHECK: [[VAR1_RHS:%.+]] = load i8*, i8** [[VAR1_RHS_REF]], // @@ -305,7 +305,7 @@ // // Shuffle and reduce function -// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* noundef %0, i16 noundef {{.*}}, i16 noundef {{.*}}, i16 noundef {{.*}}) +// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* %0, i16 {{.*}}, i16 {{.*}}, i16 {{.*}}) // CHECK: [[REMOTE_RED_LIST:%.+]] = alloca [[RLT]], align // CHECK: [[REMOTE_ELT1:%.+]] = alloca i8 // CHECK: [[REMOTE_ELT2:%.+]] = alloca float @@ -404,7 +404,7 @@ // // Inter warp copy function -// CHECK: define internal void [[WARP_COPY_FN]](i8* noundef %0, i32 noundef %1) +// CHECK: define internal void [[WARP_COPY_FN]](i8* %0, i32 %1) // CHECK-DAG: [[LANEID:%.+]] = and i32 {{.+}}, 31 // CHECK-DAG: [[WARPID:%.+]] = ashr i32 {{.+}}, 5 // CHECK-DAG: [[RED_LIST:%.+]] = bitcast i8* {{.+}} to [[RLT]]* @@ -557,7 +557,7 @@ // // Reduction function -// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* %0, i8* %1) // CHECK: [[VAR1_RHS_REF:%.+]] = getelementptr inbounds [[RLT]], [[RLT]]* [[RED_LIST_RHS:%.+]], i{{32|64}} 0, i{{32|64}} 0 // CHECK: [[VAR1_RHS_VOID:%.+]] = load i8*, i8** [[VAR1_RHS_REF]], // CHECK: [[VAR1_RHS:%.+]] = bitcast i8* [[VAR1_RHS_VOID]] to i32* @@ -602,7 +602,7 @@ // // Shuffle and reduce function -// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* noundef %0, i16 noundef {{.*}}, i16 noundef {{.*}}, i16 noundef {{.*}}) +// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* %0, i16 {{.*}}, i16 {{.*}}, i16 {{.*}}) // CHECK: [[REMOTE_RED_LIST:%.+]] = alloca [[RLT]], align // CHECK: [[REMOTE_ELT1:%.+]] = alloca i32 // CHECK: [[REMOTE_ELT2:%.+]] = alloca i16 @@ -703,7 +703,7 @@ // // Inter warp copy function -// CHECK: define internal void [[WARP_COPY_FN]](i8* noundef %0, i32 noundef %1) +// CHECK: define internal void [[WARP_COPY_FN]](i8* %0, i32 %1) // CHECK-DAG: [[LANEID:%.+]] = and i32 {{.+}}, 31 // CHECK-DAG: [[WARPID:%.+]] = ashr i32 {{.+}}, 5 // CHECK-DAG: [[RED_LIST:%.+]] = bitcast i8* {{.+}} to [[RLT]]* diff --git a/clang/test/OpenMP/nvptx_target_printf_codegen.c b/clang/test/OpenMP/nvptx_target_printf_codegen.c --- a/clang/test/OpenMP/nvptx_target_printf_codegen.c +++ b/clang/test/OpenMP/nvptx_target_printf_codegen.c @@ -83,7 +83,7 @@ // // // CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36 -// CHECK-64-SAME: (i64 noundef [[FOO:%.*]]) #[[ATTR0]] { +// CHECK-64-SAME: (i64 [[FOO:%.*]]) #[[ATTR0]] { // CHECK-64-NEXT: entry: // CHECK-64-NEXT: [[FOO_ADDR:%.*]] = alloca i64, align 8 // CHECK-64-NEXT: [[TMP:%.*]] = alloca [[PRINTF_ARGS_0:%.*]], align 8 @@ -152,7 +152,7 @@ // // // CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36 -// CHECK-32-SAME: (i32 noundef [[FOO:%.*]]) #[[ATTR0]] { +// CHECK-32-SAME: (i32 [[FOO:%.*]]) #[[ATTR0]] { // CHECK-32-NEXT: entry: // CHECK-32-NEXT: [[FOO_ADDR:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[TMP:%.*]] = alloca [[PRINTF_ARGS_0:%.*]], align 8 diff --git a/clang/test/OpenMP/nvptx_target_teams_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_codegen.cpp --- a/clang/test/OpenMP/nvptx_target_teams_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_codegen.cpp @@ -50,7 +50,7 @@ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -77,7 +77,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -91,7 +91,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -118,7 +118,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -132,7 +132,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -159,7 +159,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -180,7 +180,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -201,7 +201,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -215,7 +215,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23 -// CHECK2-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -242,7 +242,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -256,7 +256,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28 -// CHECK2-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -283,7 +283,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -297,7 +297,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK2-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -324,7 +324,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -345,7 +345,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -366,7 +366,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -378,3 +378,168 @@ // CHECK2-NEXT: store i16 1, i16* [[TMP0]], align 2 // CHECK2-NEXT: ret void // +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23 +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8* +// CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* +// CHECK3-NEXT: store i8 49, i8* [[CONV]], align 1 +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28 +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK3-NEXT: store i16 1, i16* [[CONV]], align 2 +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP1:%.*]] = bitcast i16* [[CONV]] to i8* +// CHECK3-NEXT: store i8* [[TMP1]], i8** [[TMP0]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__3 to i8*), i8* null, i8** [[TMP4]], i32 1) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP2:%.*]] = bitcast i16* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP2]], i8** [[TMP1]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__4 to i8*), i8* null, i8** [[TMP5]], i32 1) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 +// CHECK3-NEXT: store i16 1, i16* [[TMP0]], align 2 +// CHECK3-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp --- a/clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp @@ -52,7 +52,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -120,7 +120,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -136,7 +136,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -174,7 +174,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -242,7 +242,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -258,7 +258,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -275,3 +275,125 @@ // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR5]] // CHECK2-NEXT: ret void // +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16 +// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: [[I:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i32 4) +// CHECK3-NEXT: [[I_ON_STACK:%.*]] = bitcast i8* [[I]] to i32* +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I_ON_STACK]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i32* [[I_ON_STACK]] to i8* +// CHECK3-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP10]], i32 1) +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]]) +// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[I]], i32 4) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper +// CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 +// CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) +// CHECK3-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** +// CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR5]] +// CHECK3-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp --- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp @@ -72,7 +72,7 @@ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -110,7 +110,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -265,7 +265,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -399,7 +399,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8 @@ -429,7 +429,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -563,7 +563,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -658,7 +658,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39 -// CHECK1-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -680,7 +680,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -775,7 +775,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -845,7 +845,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44 -// CHECK1-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8 @@ -875,7 +875,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -984,7 +984,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1078,7 +1078,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 @@ -1108,7 +1108,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1258,7 +1258,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1395,7 +1395,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -1428,7 +1428,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1568,7 +1568,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1666,7 +1666,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -1704,7 +1704,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1859,7 +1859,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1993,7 +1993,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8 @@ -2023,7 +2023,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2157,7 +2157,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2252,7 +2252,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39 -// CHECK2-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -2274,7 +2274,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2369,7 +2369,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2439,7 +2439,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44 -// CHECK2-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8 @@ -2469,7 +2469,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2578,7 +2578,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2672,7 +2672,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 @@ -2702,7 +2702,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2851,7 +2851,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2984,7 +2984,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -3017,7 +3017,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3157,7 +3157,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3255,7 +3255,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -3289,7 +3289,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3438,7 +3438,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3565,7 +3565,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 @@ -3593,7 +3593,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3723,7 +3723,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3813,7 +3813,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39 -// CHECK3-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -3835,7 +3835,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3928,7 +3928,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3994,7 +3994,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44 -// CHECK3-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 @@ -4022,7 +4022,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4127,7 +4127,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4215,7 +4215,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 @@ -4243,7 +4243,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__8 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4393,7 +4393,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4530,7 +4530,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -4561,7 +4561,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4697,7 +4697,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4787,3 +4787,1537 @@ // CHECK3: omp.precond.end: // CHECK3-NEXT: ret void // +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28 +// CHECK4-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK4-NEXT: [[L_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[L_CASTED]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK4-NEXT: [[L_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: [[L1:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i32 4) +// CHECK4-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L1]] to i32* +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK4-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 128) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK4-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP18]], i32* [[L_CASTED]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[L_CASTED]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to i8* +// CHECK4-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4 +// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK4-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to i8* +// CHECK4-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4 +// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to i8* +// CHECK4-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4 +// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK4-NEXT: [[TMP27:%.*]] = bitcast [1000 x i32]* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 4 +// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4 +// CHECK4-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP19]] to i8* +// CHECK4-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 4 +// CHECK4-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 +// CHECK4-NEXT: [[TMP32:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP32]], i32 5) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] +// CHECK4-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK4: cond.true11: +// CHECK4-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: br label [[COND_END13:%.*]] +// CHECK4: cond.false12: +// CHECK4-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END13]] +// CHECK4: cond.end13: +// CHECK4-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ] +// CHECK4-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP45]]) +// CHECK4-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 +// CHECK4-NEXT: br i1 [[TMP47]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK4: .omp.lastprivate.then: +// CHECK4-NEXT: [[TMP48:%.*]] = load i32, i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP48]], i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK4: .omp.lastprivate.done: +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: call void @__kmpc_free_shared(i8* [[L1]], i32 4) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK4-NEXT: [[L_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK4-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 32) +// CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK4: omp.dispatch.cond: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK4: omp.dispatch.body: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK4-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK4-NEXT: store i32 [[TMP20]], i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK4: omp.dispatch.inc: +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK4: omp.dispatch.end: +// CHECK4-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP27]]) +// CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK4-NEXT: br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK4: .omp.lastprivate.then: +// CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP30]], i32* [[L_ADDR]], align 4 +// CHECK4-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK4: .omp.lastprivate.done: +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 +// CHECK4-SAME: (i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 +// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK4-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__2 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK4-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK4-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP19:%.*]] = inttoptr i32 [[TMP14]] to i8* +// CHECK4-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK4-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP15]] to i8* +// CHECK4-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4 +// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP17]] to i8* +// CHECK4-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4 +// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK4-NEXT: [[TMP25:%.*]] = bitcast [1000 x i16]* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4 +// CHECK4-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 +// CHECK4-NEXT: [[TMP28:%.*]] = bitcast [4 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP27]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i16]*)* @__omp_outlined__3 to i8*), i8* null, i8** [[TMP28]], i32 4) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] +// CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] +// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]] +// CHECK4-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK4: cond.true10: +// CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: br label [[COND_END12:%.*]] +// CHECK4: cond.false11: +// CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END12]] +// CHECK4: cond.end12: +// CHECK4-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ] +// CHECK4-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: [[TMP40:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP41:%.*]] = load i32, i32* [[TMP40]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP41]]) +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__3 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK4-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP8]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] +// CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], [1000 x i16]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK4-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 +// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK4-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX]], align 2 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]]) +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39 +// CHECK4-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) +// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK4-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__4 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10 +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to i8* +// CHECK4-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK4-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to i8* +// CHECK4-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP14:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @__omp_outlined__5 to i8*), i8* null, i8** [[TMP15]], i32 3) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9 +// CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] +// CHECK4: cond.true5: +// CHECK4-NEXT: br label [[COND_END7:%.*]] +// CHECK4: cond.false6: +// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END7]] +// CHECK4: cond.end7: +// CHECK4-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ] +// CHECK4-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__5 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK4-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44 +// CHECK4-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 +// CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[F_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[F_CASTED]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK4-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__6 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 +// CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[K:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100 +// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[F_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP9]], i32* [[F_CASTED]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[F_CASTED]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP7]] to i8* +// CHECK4-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK4-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to i8* +// CHECK4-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP16:%.*]] = bitcast [10 x [10 x i32]]* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK4-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP10]] to i8* +// CHECK4-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = bitcast [4 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, [10 x [10 x i32]]*, i32)* @__omp_outlined__7 to i8*), i8* null, i8** [[TMP19]], i32 4) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 99 +// CHECK4-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK4: cond.true6: +// CHECK4-NEXT: br label [[COND_END8:%.*]] +// CHECK4: cond.false7: +// CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END8]] +// CHECK4: cond.end8: +// CHECK4-NEXT: [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP27]], [[COND_FALSE7]] ] +// CHECK4-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP28]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__7 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 +// CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[K:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 10 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP10]], 10 +// CHECK4-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 10 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL3]] +// CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] +// CHECK4-NEXT: store i32 [[ADD5]], i32* [[J]], align 4 +// CHECK4-NEXT: store i32 10, i32* [[K]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[F_ADDR]], align 4 +// CHECK4-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]] +// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], [[MUL6]] +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4 +// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP14]] +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP0]], i32 0, i32 [[TMP15]] +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[J]], align 4 +// CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP16]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX9]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52 +// CHECK4-SAME: (i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 +// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK4-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__8 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I9:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[J10:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK4-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK4-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK4-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK4-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: land.lhs.true: +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK4-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK4-NEXT: [[CONV11:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV11]]) +// CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK4-NEXT: [[CMP12:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]] +// CHECK4-NEXT: br i1 [[CMP12]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK4-NEXT: store i64 [[TMP14]], i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP16]], 1 +// CHECK4-NEXT: [[CMP13:%.*]] = icmp slt i64 [[TMP15]], [[ADD]] +// CHECK4-NEXT: br i1 [[CMP13]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK4-NEXT: [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32 +// CHECK4-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP21]], i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP24:%.*]] = inttoptr i32 [[TMP18]] to i8* +// CHECK4-NEXT: store i8* [[TMP24]], i8** [[TMP23]], align 4 +// CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK4-NEXT: [[TMP26:%.*]] = inttoptr i32 [[TMP20]] to i8* +// CHECK4-NEXT: store i8* [[TMP26]], i8** [[TMP25]], align 4 +// CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP28:%.*]] = inttoptr i32 [[TMP22]] to i8* +// CHECK4-NEXT: store i8* [[TMP28]], i8** [[TMP27]], align 4 +// CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK4-NEXT: [[TMP30:%.*]] = bitcast [10 x [10 x i32]]* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP30]], i8** [[TMP29]], align 4 +// CHECK4-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 +// CHECK4-NEXT: [[TMP33:%.*]] = bitcast [4 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP32]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, [10 x [10 x i32]]*)* @__omp_outlined__9 to i8*), i8* null, i8** [[TMP33]], i32 4) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: [[TMP35:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP34]], [[TMP35]] +// CHECK4-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK4-NEXT: [[TMP37:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK4-NEXT: [[ADD15:%.*]] = add nsw i64 [[TMP36]], [[TMP37]] +// CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK4-NEXT: [[TMP38:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: [[TMP39:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK4-NEXT: [[ADD16:%.*]] = add nsw i64 [[TMP38]], [[TMP39]] +// CHECK4-NEXT: store i64 [[ADD16]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: [[TMP40:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: [[TMP41:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK4-NEXT: [[CMP17:%.*]] = icmp sgt i64 [[TMP40]], [[TMP41]] +// CHECK4-NEXT: br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]] +// CHECK4: cond.true18: +// CHECK4-NEXT: [[TMP42:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK4-NEXT: br label [[COND_END20:%.*]] +// CHECK4: cond.false19: +// CHECK4-NEXT: [[TMP43:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: br label [[COND_END20]] +// CHECK4: cond.end20: +// CHECK4-NEXT: [[COND21:%.*]] = phi i64 [ [[TMP42]], [[COND_TRUE18]] ], [ [[TMP43]], [[COND_FALSE19]] ] +// CHECK4-NEXT: store i64 [[COND21]], i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK4-NEXT: [[TMP44:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK4-NEXT: store i64 [[TMP44]], i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: [[TMP45:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP46:%.*]] = load i32, i32* [[TMP45]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP46]]) +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__9 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I11:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[J12:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK4-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 +// CHECK4-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] +// CHECK4-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK4-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[J]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] +// CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: land.lhs.true: +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 +// CHECK4-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_UB]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: [[CONV9:%.*]] = zext i32 [[TMP8]] to i64 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: [[CONV10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK4-NEXT: store i64 [[CONV9]], i64* [[DOTOMP_LB]], align 8 +// CHECK4-NEXT: store i64 [[CONV10]], i64* [[DOTOMP_UB]], align 8 +// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB3]], i32 [[TMP11]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK4-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: [[CONV13:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK4-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP13]], [[CONV13]] +// CHECK4-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP16]], 0 +// CHECK4-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK4-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK4-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK4-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP15]], [[CONV18]] +// CHECK4-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK4-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK4-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP19]], 0 +// CHECK4-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK4-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK4-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK4-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP18]], [[CONV25]] +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP20]], 0 +// CHECK4-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK4-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK4-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK4-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK4-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP17]], [[MUL31]] +// CHECK4-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK4-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK4-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK4-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK4-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[I11]], align 4 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP0]], i32 0, i32 [[TMP23]] +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[J12]], align 4 +// CHECK4-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP24]] +// CHECK4-NEXT: store i32 [[ADD36]], i32* [[ARRAYIDX37]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK4-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] +// CHECK4-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP28]]) +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59 +// CHECK4-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK4-NEXT: [[V_ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[V_ADDR]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK4-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR3]] +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__10 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK4-NEXT: [[V_ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK4-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK4-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[V_ADDR]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP14]] to i8* +// CHECK4-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK4-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP15]] to i8* +// CHECK4-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 4 +// CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP24:%.*]] = inttoptr i32 [[TMP17]] to i8* +// CHECK4-NEXT: store i8* [[TMP24]], i8** [[TMP23]], align 4 +// CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK4-NEXT: [[TMP26:%.*]] = bitcast [1000 x i32]* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP26]], i8** [[TMP25]], align 4 +// CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4 +// CHECK4-NEXT: [[TMP28:%.*]] = bitcast i32* [[TMP18]] to i8* +// CHECK4-NEXT: store i8* [[TMP28]], i8** [[TMP27]], align 4 +// CHECK4-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK4-NEXT: [[TMP31:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @__omp_outlined__11 to i8*), i8* null, i8** [[TMP31]], i32 5) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] +// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP36]], [[TMP37]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP38]], [[TMP39]] +// CHECK4-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK4: cond.true10: +// CHECK4-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: br label [[COND_END12:%.*]] +// CHECK4: cond.false11: +// CHECK4-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END12]] +// CHECK4: cond.end12: +// CHECK4-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP40]], [[COND_TRUE10]] ], [ [[TMP41]], [[COND_FALSE11]] ] +// CHECK4-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP42]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: [[TMP43:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP44:%.*]] = load i32, i32* [[TMP43]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP44]]) +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__11 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK4-NEXT: [[V_ADDR:%.*]] = alloca i32*, align 4 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK4-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP8]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK4-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] +// CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32*, i32** [[V_ADDR]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i32 [[TMP14]] +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK4-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX5]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP20]]) +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp --- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp @@ -30,7 +30,7 @@ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -68,7 +68,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -213,7 +213,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -304,10 +304,10 @@ // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I7]]) #[[ATTR5:[0-9]+]] -// CHECK1-NEXT: [[CALL13:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP0]]) #[[ATTR5]] +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I7]]) #[[ATTR5:[0-9]+]] +// CHECK1-NEXT: [[CALL13:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR5]] // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CALL]], [[CALL13]] -// CHECK1-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[CONV]]) #[[ATTR5]] +// CHECK1-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[CONV]]) #[[ATTR5]] // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CALL15]] // CHECK1-NEXT: store i32 [[ADD16]], i32* [[TMP0]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -340,7 +340,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -374,7 +374,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -513,7 +513,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -598,10 +598,10 @@ // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I4]]) #[[ATTR5:[0-9]+]] -// CHECK2-NEXT: [[CALL8:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP0]]) #[[ATTR5]] +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR5:[0-9]+]] +// CHECK2-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR5]] // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]] -// CHECK2-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARGC_ADDR]]) #[[ATTR5]] +// CHECK2-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR5]] // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] // CHECK2-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -632,3 +632,1195 @@ // CHECK2: omp.precond.end: // CHECK2-NEXT: ret void // +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 +// CHECK3-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK3: omp.precond.then: +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK3-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARGC_CASTED]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to i8* +// CHECK3-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to i8* +// CHECK3-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to i8* +// CHECK3-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK3-NEXT: [[TMP27:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4 +// CHECK3-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP19]] to i8* +// CHECK3-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 4 +// CHECK3-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 +// CHECK3-NEXT: [[TMP32:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, i32*, i32)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP32]], i32 5) +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] +// CHECK3-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK3: cond.true11: +// CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: br label [[COND_END13:%.*]] +// CHECK3: cond.false12: +// CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END13]] +// CHECK3: cond.end13: +// CHECK3-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ] +// CHECK3-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP45]]) +// CHECK3-NEXT: br label [[OMP_PRECOND_END]] +// CHECK3: omp.precond.end: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK3: omp.precond.then: +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK3: omp.dispatch.cond: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK3: omp.dispatch.body: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR5:[0-9]+]] +// CHECK3-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR5]] +// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]] +// CHECK3-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR5]] +// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] +// CHECK3-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK3: omp.dispatch.inc: +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK3-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK3: omp.dispatch.end: +// CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]]) +// CHECK3-NEXT: br label [[OMP_PRECOND_END]] +// CHECK3: omp.precond.end: +// CHECK3-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 +// CHECK4-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) +// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK4: user_code.entry: +// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32* +// CHECK4-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK4-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK4-NEXT: ret void +// CHECK4: worker.exit: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK4-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK4-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK4-NEXT: [[CONV8:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32* +// CHECK4-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK4-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK4-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8* +// CHECK4-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8 +// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 +// CHECK4-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8* +// CHECK4-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8 +// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 +// CHECK4-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP19]] to i8* +// CHECK4-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 8 +// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 3 +// CHECK4-NEXT: [[TMP29:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK4-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 8 +// CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 4 +// CHECK4-NEXT: [[TMP31:%.*]] = inttoptr i64 [[TMP21]] to i8* +// CHECK4-NEXT: store i8* [[TMP31]], i8** [[TMP30]], align 8 +// CHECK4-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 +// CHECK4-NEXT: [[TMP34:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP33]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i64, i64, i64, i32*, i64)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP34]], i64 5) +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// CHECK4-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP39]], [[TMP40]] +// CHECK4-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK4-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP41]], [[TMP42]] +// CHECK4-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] +// CHECK4: cond.true14: +// CHECK4-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK4-NEXT: br label [[COND_END16:%.*]] +// CHECK4: cond.false15: +// CHECK4-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END16]] +// CHECK4: cond.end16: +// CHECK4-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP43]], [[COND_TRUE14]] ], [ [[TMP44]], [[COND_FALSE15]] ] +// CHECK4-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP47]]) +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 +// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK4: omp.precond.then: +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK4-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK4: omp.dispatch.cond: +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP11]] to i32 +// CHECK4-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP10]], [[CONV8]] +// CHECK4-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK4-NEXT: [[CONV10:%.*]] = trunc i64 [[TMP12]] to i32 +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[CONV10]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK4-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK4: omp.dispatch.body: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK4-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I7]]) #[[ATTR5:[0-9]+]] +// CHECK4-NEXT: [[CALL13:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR5]] +// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[CALL]], [[CALL13]] +// CHECK4-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[CONV]]) #[[ATTR5]] +// CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CALL15]] +// CHECK4-NEXT: store i32 [[ADD16]], i32* [[TMP0]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK4-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK4: omp.dispatch.inc: +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK4-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK4-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK4: omp.dispatch.end: +// CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]]) +// CHECK4-NEXT: br label [[OMP_PRECOND_END]] +// CHECK4: omp.precond.end: +// CHECK4-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 +// CHECK5-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) +// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK5: user_code.entry: +// CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK5-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK5-NEXT: ret void +// CHECK5: worker.exit: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK5-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[ARGC_CASTED]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to i8* +// CHECK5-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to i8* +// CHECK5-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK5-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to i8* +// CHECK5-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK5-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 4 +// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4 +// CHECK5-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP19]] to i8* +// CHECK5-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 4 +// CHECK5-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 +// CHECK5-NEXT: [[TMP32:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, i32*, i32)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP32]], i32 5) +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] +// CHECK5-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK5: cond.true11: +// CHECK5-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: br label [[COND_END13:%.*]] +// CHECK5: cond.false12: +// CHECK5-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END13]] +// CHECK5: cond.end13: +// CHECK5-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ] +// CHECK5-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK5-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK5: omp.loop.exit: +// CHECK5-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 +// CHECK5-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP45]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK5-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK5-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK5: omp.precond.then: +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK5: omp.dispatch.cond: +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK5: cond.true: +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK5-NEXT: br label [[COND_END:%.*]] +// CHECK5: cond.false: +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[COND_END]] +// CHECK5: cond.end: +// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK5: omp.dispatch.body: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK5: omp.inner.for.cond: +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK5: omp.inner.for.body: +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR5:[0-9]+]] +// CHECK5-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR5]] +// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]] +// CHECK5-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR5]] +// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4 +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: +// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK5: omp.inner.for.inc: +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK5: omp.inner.for.end: +// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK5: omp.dispatch.inc: +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_LB]], align 4 +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_UB]], align 4 +// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK5: omp.dispatch.end: +// CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK5-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]]) +// CHECK5-NEXT: br label [[OMP_PRECOND_END]] +// CHECK5: omp.precond.end: +// CHECK5-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 +// CHECK6-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) +// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK6: user_code.entry: +// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK6-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK6-NEXT: ret void +// CHECK6: worker.exit: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK6-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[ARGC_CASTED]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to i8* +// CHECK6-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to i8* +// CHECK6-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to i8* +// CHECK6-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i32* [[TMP0]] to i8* +// CHECK6-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 4 +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4 +// CHECK6-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP19]] to i8* +// CHECK6-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 4 +// CHECK6-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 +// CHECK6-NEXT: [[TMP32:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, i32*, i32)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP32]], i32 5) +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] +// CHECK6-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK6: cond.true11: +// CHECK6-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: br label [[COND_END13:%.*]] +// CHECK6: cond.false12: +// CHECK6-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END13]] +// CHECK6: cond.end13: +// CHECK6-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ] +// CHECK6-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK6-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK6: omp.loop.exit: +// CHECK6-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 +// CHECK6-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP45]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK6: omp.precond.then: +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK6: omp.dispatch.cond: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK6: cond.true: +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK6-NEXT: br label [[COND_END:%.*]] +// CHECK6: cond.false: +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[COND_END]] +// CHECK6: cond.end: +// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK6: omp.dispatch.body: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK6: omp.inner.for.cond: +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK6: omp.inner.for.body: +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR5:[0-9]+]] +// CHECK6-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR5]] +// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]] +// CHECK6-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR5]] +// CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK6: omp.body.continue: +// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK6: omp.inner.for.inc: +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK6: omp.inner.for.end: +// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK6: omp.dispatch.inc: +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_LB]], align 4 +// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_UB]], align 4 +// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK6: omp.dispatch.end: +// CHECK6-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK6-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]]) +// CHECK6-NEXT: br label [[OMP_PRECOND_END]] +// CHECK6: omp.precond.end: +// CHECK6-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp --- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp @@ -60,7 +60,7 @@ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -98,7 +98,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -265,7 +265,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -411,7 +411,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8 @@ -441,7 +441,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -587,7 +587,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -694,7 +694,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37 -// CHECK1-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -716,7 +716,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -818,7 +818,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -895,7 +895,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42 -// CHECK1-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8 @@ -925,7 +925,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1042,7 +1042,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1144,7 +1144,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 -// CHECK2-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -1178,7 +1178,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1339,7 +1339,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1478,7 +1478,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32 -// CHECK2-SAME: (i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 @@ -1506,7 +1506,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1648,7 +1648,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1750,7 +1750,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37 -// CHECK2-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -1772,7 +1772,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1872,7 +1872,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1945,7 +1945,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42 -// CHECK2-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 @@ -1973,7 +1973,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2086,7 +2086,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2180,3 +2180,1041 @@ // CHECK2: .omp.final.done: // CHECK2-NEXT: ret void // +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[L_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[L_CASTED]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[L1:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i32 4) +// CHECK3-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L1]] to i32* +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK3: omp.precond.then: +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 128) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK3-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[L_ADDR]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[TMP18]], i32* [[L_CASTED]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[L_CASTED]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to i8* +// CHECK3-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to i8* +// CHECK3-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to i8* +// CHECK3-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK3-NEXT: [[TMP27:%.*]] = bitcast [1000 x i32]* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4 +// CHECK3-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP19]] to i8* +// CHECK3-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP32:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP32]], i32 5), !llvm.access.group !12 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] +// CHECK3-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK3: cond.true11: +// CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: br label [[COND_END13:%.*]] +// CHECK3: cond.false12: +// CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: br label [[COND_END13]] +// CHECK3: cond.end13: +// CHECK3-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ] +// CHECK3-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP45]]) +// CHECK3-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 +// CHECK3-NEXT: br i1 [[TMP47]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3: .omp.final.then: +// CHECK3-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK3-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV16]], 1 +// CHECK3-NEXT: [[ADD17:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD17]], i32* [[I4]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK3: .omp.final.done: +// CHECK3-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 +// CHECK3-NEXT: br i1 [[TMP50]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK3: .omp.lastprivate.then: +// CHECK3-NEXT: [[TMP51:%.*]] = load i32, i32* [[L_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP51]], i32* [[L_ADDR]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK3: .omp.lastprivate.done: +// CHECK3-NEXT: br label [[OMP_PRECOND_END]] +// CHECK3: omp.precond.end: +// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[L1]], i32 4) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK3: omp.precond.then: +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 32) +// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK3: omp.dispatch.cond: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK3: omp.dispatch.body: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK3-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: store i32 [[TMP20]], i32* [[L_ADDR]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK3: omp.dispatch.inc: +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK3: omp.dispatch.end: +// CHECK3-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP27]]) +// CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK3-NEXT: br i1 [[TMP29]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3: .omp.final.then: +// CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP30]], 0 +// CHECK3-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK3-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1 +// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK3-NEXT: store i32 [[ADD13]], i32* [[I3]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK3: .omp.final.done: +// CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK3-NEXT: br i1 [[TMP32]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// CHECK3: .omp.lastprivate.then: +// CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[L_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP33]], i32* [[L_ADDR]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] +// CHECK3: .omp.lastprivate.done: +// CHECK3-NEXT: br label [[OMP_PRECOND_END]] +// CHECK3: omp.precond.end: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32 +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 +// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK3: omp.precond.then: +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK3-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP19:%.*]] = inttoptr i32 [[TMP14]] to i8* +// CHECK3-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP15]] to i8* +// CHECK3-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP17]] to i8* +// CHECK3-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK3-NEXT: [[TMP25:%.*]] = bitcast [1000 x i16]* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP28:%.*]] = bitcast [4 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP27]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i16]*)* @__omp_outlined__3 to i8*), i8* null, i8** [[TMP28]], i32 4), !llvm.access.group !19 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] +// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] +// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]] +// CHECK3-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK3: cond.true10: +// CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: br label [[COND_END12:%.*]] +// CHECK3: cond.false11: +// CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: br label [[COND_END12]] +// CHECK3: cond.end12: +// CHECK3-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ] +// CHECK3-NEXT: store i32 [[COND13]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: [[TMP40:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[TMP40]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP41]]) +// CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK3-NEXT: br i1 [[TMP43]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3: .omp.final.then: +// CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP44]], 0 +// CHECK3-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV15]], 1 +// CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD16]], i32* [[I3]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK3: .omp.final.done: +// CHECK3-NEXT: br label [[OMP_PRECOND_END]] +// CHECK3: omp.precond.end: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK3: omp.precond.then: +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP8]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], [1000 x i16]* [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX]], align 2, !llvm.access.group !22 +// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK3-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX]], align 2, !llvm.access.group !22 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]]) +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 +// CHECK3-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3: .omp.final.then: +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK3-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP21]], 0 +// CHECK3-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 +// CHECK3-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 1 +// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] +// CHECK3-NEXT: store i32 [[ADD11]], i32* [[I3]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK3: .omp.final.done: +// CHECK3-NEXT: br label [[OMP_PRECOND_END]] +// CHECK3: omp.precond.end: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37 +// CHECK3-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10 +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to i8* +// CHECK3-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to i8* +// CHECK3-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP14:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP15:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @__omp_outlined__5 to i8*), i8* null, i8** [[TMP15]], i32 3), !llvm.access.group !25 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9 +// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] +// CHECK3: cond.true5: +// CHECK3-NEXT: br label [[COND_END7:%.*]] +// CHECK3: cond.false6: +// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: br label [[COND_END7]] +// CHECK3: cond.end7: +// CHECK3-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ] +// CHECK3-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]]) +// CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3: .omp.final.then: +// CHECK3-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK3: .omp.final.done: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__5 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]] +// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3: .omp.final.then: +// CHECK3-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK3: .omp.final.done: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42 +// CHECK3-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 +// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) +// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK3: user_code.entry: +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[F_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[F_CASTED]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK3-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR3]] +// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) +// CHECK3-NEXT: ret void +// CHECK3: worker.exit: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__6 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 +// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[K:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100 +// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[F_ADDR]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: store i32 [[TMP9]], i32* [[F_CASTED]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[F_CASTED]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP7]] to i8* +// CHECK3-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to i8* +// CHECK3-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP16:%.*]] = bitcast [10 x [10 x i32]]* [[TMP0]] to i8* +// CHECK3-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 +// CHECK3-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP10]] to i8* +// CHECK3-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP19:%.*]] = bitcast [4 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** +// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, [10 x [10 x i32]]*, i32)* @__omp_outlined__7 to i8*), i8* null, i8** [[TMP19]], i32 4), !llvm.access.group !31 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 99 +// CHECK3-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK3: cond.true6: +// CHECK3-NEXT: br label [[COND_END8:%.*]] +// CHECK3: cond.false7: +// CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: br label [[COND_END8]] +// CHECK3: cond.end8: +// CHECK3-NEXT: [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP27]], [[COND_FALSE7]] ] +// CHECK3-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: store i32 [[TMP28]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]]) +// CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK3-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3: .omp.final.then: +// CHECK3-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK3-NEXT: store i32 10, i32* [[J]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK3: .omp.final.done: +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__7 +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 +// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[K:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]] +// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 10 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP10]], 10 +// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 10 +// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL3]] +// CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] +// CHECK3-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: store i32 10, i32* [[K]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[F_ADDR]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], [[MUL6]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP14]] +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP0]], i32 0, i32 [[TMP15]] +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX9]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] +// CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 +// CHECK3-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3: .omp.final.then: +// CHECK3-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK3-NEXT: store i32 10, i32* [[J]], align 4 +// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK3: .omp.final.done: +// CHECK3-NEXT: ret void +// diff --git a/clang/test/OpenMP/nvptx_teams_codegen.cpp b/clang/test/OpenMP/nvptx_teams_codegen.cpp --- a/clang/test/OpenMP/nvptx_teams_codegen.cpp +++ b/clang/test/OpenMP/nvptx_teams_codegen.cpp @@ -77,7 +77,7 @@ #endif // CK2 #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 -// CHECK1-SAME: (i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -104,7 +104,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -118,7 +118,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15 -// CHECK1-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -144,7 +144,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -158,7 +158,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -184,7 +184,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -198,7 +198,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15 -// CHECK2-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -224,7 +224,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -238,7 +238,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK3-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -271,7 +271,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -285,7 +285,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53 -// CHECK3-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -317,7 +317,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -331,7 +331,7 @@ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -361,7 +361,7 @@ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -375,7 +375,7 @@ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -405,7 +405,7 @@ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp b/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp --- a/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp +++ b/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp @@ -51,7 +51,7 @@ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l20 -// CHECK1-SAME: (i64 noundef [[E:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[E:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[E_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -78,7 +78,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -117,7 +117,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -193,7 +193,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -254,7 +254,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -278,7 +278,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -302,7 +302,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -326,7 +326,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -350,7 +350,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l26 -// CHECK1-SAME: (i64 noundef [[C:%.*]], i64 noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[C:%.*]], i64 [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8 @@ -384,7 +384,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[C:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[C:%.*]], float* nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -443,7 +443,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func3 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -540,7 +540,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func4 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -616,7 +616,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -646,7 +646,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func6 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -674,7 +674,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func7 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -704,7 +704,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func8 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -732,7 +732,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -757,7 +757,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -823,7 +823,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -896,7 +896,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func12 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -996,7 +996,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func13 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1074,7 +1074,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func15 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -1174,7 +1174,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func16 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1252,7 +1252,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func17 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1283,7 +1283,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func18 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1312,7 +1312,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func19 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1343,7 +1343,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func20 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1372,7 +1372,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l20 -// CHECK2-SAME: (double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[E_ADDR:%.*]] = alloca double*, align 4 // CHECK2-NEXT: [[E1:%.*]] = alloca double, align 8 @@ -1397,7 +1397,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1436,7 +1436,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -1512,7 +1512,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1573,7 +1573,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1597,7 +1597,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1621,7 +1621,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1645,7 +1645,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1669,7 +1669,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l26 -// CHECK2-SAME: (i32 noundef [[C:%.*]], i32 noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[C:%.*]], i32 [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4 @@ -1703,7 +1703,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[C:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[C:%.*]], float* nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1762,7 +1762,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func3 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -1859,7 +1859,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func4 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1935,7 +1935,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1965,7 +1965,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1993,7 +1993,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func7 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2023,7 +2023,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func8 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2051,7 +2051,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2075,7 +2075,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2141,7 +2141,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2214,7 +2214,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func12 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -2314,7 +2314,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func13 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2392,7 +2392,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func15 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -2492,7 +2492,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func16 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2570,7 +2570,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func17 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2601,7 +2601,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func18 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2630,7 +2630,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func19 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2661,7 +2661,7 @@ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func20 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2690,7 +2690,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l20 -// CHECK3-SAME: (double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[E_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[E1:%.*]] = alloca double, align 8 @@ -2715,7 +2715,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2754,7 +2754,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -2830,7 +2830,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2891,7 +2891,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2915,7 +2915,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2939,7 +2939,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2963,7 +2963,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -2987,7 +2987,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l26 -// CHECK3-SAME: (i32 noundef [[C:%.*]], i32 noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[C:%.*]], i32 [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4 @@ -3021,7 +3021,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[C:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[C:%.*]], float* nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3080,7 +3080,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func3 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -3177,7 +3177,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func4 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3253,7 +3253,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func5 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3283,7 +3283,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func6 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3311,7 +3311,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func7 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3341,7 +3341,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func8 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3369,7 +3369,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3393,7 +3393,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3459,7 +3459,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3532,7 +3532,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func12 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -3632,7 +3632,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func13 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3710,7 +3710,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func15 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -3810,7 +3810,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func16 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3888,7 +3888,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func17 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3919,7 +3919,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func18 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3948,7 +3948,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func19 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -3979,7 +3979,7 @@ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func20 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_unsupported_type_codegen.cpp b/clang/test/OpenMP/nvptx_unsupported_type_codegen.cpp --- a/clang/test/OpenMP/nvptx_unsupported_type_codegen.cpp +++ b/clang/test/OpenMP/nvptx_unsupported_type_codegen.cpp @@ -34,7 +34,7 @@ #pragma omp declare target T a = T(); T f = a; -// CHECK: define{{ protected | }}void @{{.+}}foo{{.+}}([[T]]* noundef byval([[T]]) align {{.+}}) +// CHECK: define{{ protected | }}void @{{.+}}foo{{.+}}([[T]]* byval([[T]]) align {{.+}}) void foo(T a = T()) { return; } @@ -54,7 +54,7 @@ } T1 a1 = T1(); T1 f1 = a1; -// CHECK: define{{ protected | }}void @{{.+}}foo1{{.+}}([[T1]]* noundef byval([[T1]]) align {{.+}}) +// CHECK: define{{ protected | }}void @{{.+}}foo1{{.+}}([[T1]]* byval([[T1]]) align {{.+}}) void foo1(T1 a = T1()) { return; } diff --git a/clang/test/OpenMP/openmp_offload_codegen.cpp b/clang/test/OpenMP/openmp_offload_codegen.cpp --- a/clang/test/OpenMP/openmp_offload_codegen.cpp +++ b/clang/test/OpenMP/openmp_offload_codegen.cpp @@ -25,7 +25,7 @@ } } -// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(i32* noundef nonnull align 4 dereferenceable(4){{.*}} +// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(i32* nonnull align 4 dereferenceable(4){{.*}} // CK1: {{.*}}void {{.*}}target_maps_parallel_integer{{.*}} { diff --git a/clang/test/OpenMP/reduction_implicit_map.cpp b/clang/test/OpenMP/reduction_implicit_map.cpp --- a/clang/test/OpenMP/reduction_implicit_map.cpp +++ b/clang/test/OpenMP/reduction_implicit_map.cpp @@ -98,7 +98,7 @@ return 0; } // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l32 -// CHECK-SAME: (double* noundef [[E:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-SAME: (double* [[E:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[E_ADDR:%.*]] = alloca double*, align 8 // CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -121,7 +121,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef [[E:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* [[E:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -167,7 +167,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func -// CHECK-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -243,7 +243,7 @@ // // // CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func -// CHECK-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/target_firstprivate_codegen.cpp b/clang/test/OpenMP/target_firstprivate_codegen.cpp --- a/clang/test/OpenMP/target_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_firstprivate_codegen.cpp @@ -143,7 +143,7 @@ // CHECK: [[PTR_GEP_ARG:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]]) - // TCHECK: define weak_odr void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], i32** noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[P_IN:%.+]], i{{[0-9]+}} noundef [[GA_IN:%.+]]) + // TCHECK: define weak_odr void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A_IN:%.+]], i32** nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[P_IN:%.+]], i{{[0-9]+}} [[GA_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[P_ADDR:%.+]] = alloca i32**, // TCHECK: [[GA_ADDR:%.+]] = alloca i{{64|32}}, @@ -257,7 +257,7 @@ // make sure that firstprivate variables are generated in all cases and that we use those instances for operations inside the // target region - // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A2_IN:%.+]], [10 x float]* {{.+}} [[B_IN:%.+]], i{{[0-9]+}} noundef [[BN_SZ:%.+]], float* {{.+}} [[BN_IN:%.+]], [5 x [10 x double]]* {{.+}} [[C_IN:%.+]], i{{[0-9]+}} noundef [[CN_SZ1:%.+]], i{{[0-9]+}} noundef [[CN_SZ2:%.+]], double* {{.+}} [[CN_IN:%.+]], [[TT]]* {{.+}} [[D_IN:%.+]]) + // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A2_IN:%.+]], [10 x float]* {{.+}} [[B_IN:%.+]], i{{[0-9]+}} [[BN_SZ:%.+]], float* {{.+}} [[BN_IN:%.+]], [5 x [10 x double]]* {{.+}} [[C_IN:%.+]], i{{[0-9]+}} [[CN_SZ1:%.+]], i{{[0-9]+}} [[CN_SZ2:%.+]], double* {{.+}} [[CN_IN:%.+]], [[TT]]* {{.+}} [[D_IN:%.+]]) // TCHECK: [[A2_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[B_ADDR:%.+]] = alloca [10 x float]*, // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, @@ -352,7 +352,7 @@ // CHECK: [[PTR_GEP_ARG3:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[PTR_ARR3]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]]) - // TCHECK: define weak_odr void @__omp_offloading_{{.+}}(double* noundef [[PTR_IN:%.+]], [[TTII]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[E:%.+]]) + // TCHECK: define weak_odr void @__omp_offloading_{{.+}}(double* [[PTR_IN:%.+]], [[TTII]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[E:%.+]]) // TCHECK: [[PTR_ADDR:%.+]] = alloca double*, // TCHECK-NOT: alloca [[TTII]], // TCHECK-NOT: alloca double*, @@ -391,7 +391,7 @@ return a; } -// TCHECK: define weak_odr void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], i{{[0-9]+}} noundef [[A3_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) +// TCHECK: define weak_odr void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A_IN:%.+]], i{{[0-9]+}} [[A3_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[A3_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*, @@ -479,7 +479,7 @@ // only check that we use the map types stored in the global variable // CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]]) - // TCHECK: define weak_odr void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i{{[0-9]+}} noundef [[B_IN:%.+]], i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i{{[0-9]+}}{{.+}} [[C_IN:%.+]]) + // TCHECK: define weak_odr void @__omp_offloading_{{.+}}([[S1]]* [[TH:%.+]], i{{[0-9]+}} [[B_IN:%.+]], i{{[0-9]+}} [[VLA:%.+]], i{{[0-9]+}} [[VLA1:%.+]], i{{[0-9]+}}{{.+}} [[C_IN:%.+]]) // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*, // TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, @@ -587,7 +587,7 @@ // CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]]) -// TCHECK: define weak_odr void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) +// TCHECK: define weak_odr void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*, // TCHECK-NOT: alloca i{{[0-9]+}}, diff --git a/clang/test/OpenMP/target_parallel_codegen.cpp b/clang/test/OpenMP/target_parallel_codegen.cpp --- a/clang/test/OpenMP/target_parallel_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_codegen.cpp @@ -2565,7 +2565,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2575,7 +2575,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -2590,7 +2590,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2617,7 +2617,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2640,7 +2640,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2664,7 +2664,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -2703,7 +2703,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2776,7 +2776,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2810,7 +2810,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2849,7 +2849,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2876,7 +2876,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2915,7 +2915,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2941,7 +2941,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2971,6 +2971,420 @@ // CHECK9-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK10-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK10-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK10: .cancel.exit: +// CHECK10-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK10-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK10: .cancel.continue: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK10-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK10-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK10-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK10-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK10-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK10-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK10-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK10-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK10-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK10-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK10-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK10-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: @@ -2979,7 +3393,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2989,7 +3403,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -3004,7 +3418,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3031,7 +3445,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -3052,7 +3466,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3075,7 +3489,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -3112,7 +3526,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3184,7 +3598,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -3216,7 +3630,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3254,7 +3668,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3279,7 +3693,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3317,7 +3731,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -3341,7 +3755,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3369,3 +3783,6028 @@ // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: ret void // +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK12-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK12-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK12: .cancel.exit: +// CHECK12-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK12-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK12: .cancel.continue: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK12-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK12-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK12-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK12-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK12-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK12-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK12-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK12-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK12-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK12-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK12-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK12-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK12-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK12-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK12-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK12-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK12-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] +// CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* +// CHECK17-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 +// CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 +// CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* +// CHECK17-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 +// CHECK17-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 +// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 +// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* +// CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 +// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 +// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP38]], align 8 +// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK17-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK17-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK17: omp_offload.failed10: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK17: omp_offload.cont11: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK17-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 +// CHECK17-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK17-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 +// CHECK17-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] +// CHECK17: omp_if.then15: +// CHECK17-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK17-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK17-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 +// CHECK17-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP49]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i64 72, i1 false) +// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* +// CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8 +// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* +// CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8 +// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP54]], align 8 +// CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 +// CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 +// CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP59]], align 8 +// CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP61]], align 8 +// CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP63]], align 8 +// CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP64]], align 8 +// CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** +// CHECK17-NEXT: store float* [[VLA]], float** [[TMP66]], align 8 +// CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** +// CHECK17-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 +// CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK17-NEXT: store i64 [[TMP46]], i64* [[TMP69]], align 8 +// CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 +// CHECK17-NEXT: store i8* null, i8** [[TMP70]], align 8 +// CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 8 +// CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 +// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 +// CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8 +// CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 +// CHECK17-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* +// CHECK17-NEXT: store i64 5, i64* [[TMP77]], align 8 +// CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 +// CHECK17-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* +// CHECK17-NEXT: store i64 5, i64* [[TMP79]], align 8 +// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 +// CHECK17-NEXT: store i8* null, i8** [[TMP80]], align 8 +// CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 +// CHECK17-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP82]], align 8 +// CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 +// CHECK17-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP84]], align 8 +// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 +// CHECK17-NEXT: store i8* null, i8** [[TMP85]], align 8 +// CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 +// CHECK17-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** +// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP87]], align 8 +// CHECK17-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 +// CHECK17-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** +// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP89]], align 8 +// CHECK17-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK17-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 8 +// CHECK17-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 +// CHECK17-NEXT: store i8* null, i8** [[TMP91]], align 8 +// CHECK17-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 +// CHECK17-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 8 +// CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 +// CHECK17-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 8 +// CHECK17-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 +// CHECK17-NEXT: store i8* null, i8** [[TMP96]], align 8 +// CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK17-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK17-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] +// CHECK17: omp_offload.failed19: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT20]] +// CHECK17: omp_offload.cont20: +// CHECK17-NEXT: br label [[OMP_IF_END22:%.*]] +// CHECK17: omp_if.else21: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_IF_END22]] +// CHECK17: omp_if.end22: +// CHECK17-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) +// CHECK17-NEXT: ret i32 [[TMP102]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK17-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK17-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 +// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] +// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK17: omp_offload.failed.i: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] +// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK17: .omp_outlined..1.exit: +// CHECK17-NEXT: ret i32 0 +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 +// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK17-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK17-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK17: .cancel.exit: +// CHECK17-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK17-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK17: .cancel.continue: +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK17-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK17-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK17-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK17-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK17-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK17-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3bari +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP8]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK17-NEXT: store double* [[A]], double** [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK17-NEXT: store i64 2, i64* [[TMP22]], align 8 +// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* +// CHECK17-NEXT: store i64 2, i64* [[TMP24]], align 8 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 +// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 +// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 +// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 +// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK17-NEXT: store i8* null, i8** [[TMP36]], align 8 +// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK17-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK17-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] +// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK17-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] +// CHECK17-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK17-NEXT: ret i32 [[ADD4]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP31]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP24]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK17-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK17-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK17-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK17-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] +// CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* +// CHECK18-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 +// CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 +// CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* +// CHECK18-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 +// CHECK18-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 +// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* +// CHECK18-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* +// CHECK18-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 +// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* +// CHECK18-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 +// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* +// CHECK18-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 +// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP38]], align 8 +// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK18-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK18-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK18: omp_offload.failed10: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK18: omp_offload.cont11: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK18-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 +// CHECK18-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK18-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 +// CHECK18-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] +// CHECK18: omp_if.then15: +// CHECK18-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK18-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK18-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 +// CHECK18-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP49]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i64 72, i1 false) +// CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* +// CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8 +// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* +// CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8 +// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP54]], align 8 +// CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 +// CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 +// CHECK18-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP59]], align 8 +// CHECK18-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP61]], align 8 +// CHECK18-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP63]], align 8 +// CHECK18-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP64]], align 8 +// CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** +// CHECK18-NEXT: store float* [[VLA]], float** [[TMP66]], align 8 +// CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** +// CHECK18-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 +// CHECK18-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK18-NEXT: store i64 [[TMP46]], i64* [[TMP69]], align 8 +// CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 +// CHECK18-NEXT: store i8* null, i8** [[TMP70]], align 8 +// CHECK18-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 8 +// CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 +// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 +// CHECK18-NEXT: store i8* null, i8** [[TMP75]], align 8 +// CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 +// CHECK18-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* +// CHECK18-NEXT: store i64 5, i64* [[TMP77]], align 8 +// CHECK18-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 +// CHECK18-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* +// CHECK18-NEXT: store i64 5, i64* [[TMP79]], align 8 +// CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 +// CHECK18-NEXT: store i8* null, i8** [[TMP80]], align 8 +// CHECK18-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 +// CHECK18-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP82]], align 8 +// CHECK18-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 +// CHECK18-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP84]], align 8 +// CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 +// CHECK18-NEXT: store i8* null, i8** [[TMP85]], align 8 +// CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 +// CHECK18-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** +// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP87]], align 8 +// CHECK18-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 +// CHECK18-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** +// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP89]], align 8 +// CHECK18-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK18-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 8 +// CHECK18-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 +// CHECK18-NEXT: store i8* null, i8** [[TMP91]], align 8 +// CHECK18-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 +// CHECK18-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 8 +// CHECK18-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 +// CHECK18-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 8 +// CHECK18-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 +// CHECK18-NEXT: store i8* null, i8** [[TMP96]], align 8 +// CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK18-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK18-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] +// CHECK18: omp_offload.failed19: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT20]] +// CHECK18: omp_offload.cont20: +// CHECK18-NEXT: br label [[OMP_IF_END22:%.*]] +// CHECK18: omp_if.else21: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_IF_END22]] +// CHECK18: omp_if.end22: +// CHECK18-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) +// CHECK18-NEXT: ret i32 [[TMP102]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK18-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK18-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 +// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] +// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK18: omp_offload.failed.i: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] +// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK18: .omp_outlined..1.exit: +// CHECK18-NEXT: ret i32 0 +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 +// CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK18-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK18-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK18: .cancel.exit: +// CHECK18-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK18-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK18: .cancel.continue: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK18-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK18-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK18-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK18-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK18-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3bari +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP8]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK18-NEXT: store double* [[A]], double** [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK18-NEXT: store i64 2, i64* [[TMP22]], align 8 +// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* +// CHECK18-NEXT: store i64 2, i64* [[TMP24]], align 8 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 +// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 +// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 +// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 +// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK18-NEXT: store i8* null, i8** [[TMP36]], align 8 +// CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK18-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK18-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] +// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK18-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] +// CHECK18-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK18-NEXT: ret i32 [[ADD4]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP31]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP24]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK18-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK18-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK18-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK18-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK18-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] +// CHECK19-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK19-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* +// CHECK19-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 +// CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 +// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP31]], align 4 +// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* +// CHECK19-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 +// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* +// CHECK19-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 +// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK19-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 +// CHECK19-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK19: omp_offload.failed8: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK19: omp_offload.cont9: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 +// CHECK19-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 +// CHECK19-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 +// CHECK19-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] +// CHECK19: omp_if.then12: +// CHECK19-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK19-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 +// CHECK19-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK19-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 +// CHECK19-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 +// CHECK19-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i32 72, i1 false) +// CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* +// CHECK19-NEXT: store i32 [[TMP42]], i32* [[TMP51]], align 4 +// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* +// CHECK19-NEXT: store i32 [[TMP42]], i32* [[TMP53]], align 4 +// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 +// CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 +// CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP59]], align 4 +// CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP61]], align 4 +// CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP63]], align 4 +// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP64]], align 4 +// CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** +// CHECK19-NEXT: store float* [[VLA]], float** [[TMP66]], align 4 +// CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** +// CHECK19-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 +// CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK19-NEXT: store i64 [[TMP45]], i64* [[TMP69]], align 4 +// CHECK19-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 +// CHECK19-NEXT: store i8* null, i8** [[TMP70]], align 4 +// CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 4 +// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 +// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 +// CHECK19-NEXT: store i8* null, i8** [[TMP75]], align 4 +// CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 +// CHECK19-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK19-NEXT: store i32 5, i32* [[TMP77]], align 4 +// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 +// CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK19-NEXT: store i32 5, i32* [[TMP79]], align 4 +// CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 +// CHECK19-NEXT: store i8* null, i8** [[TMP80]], align 4 +// CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 +// CHECK19-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP82]], align 4 +// CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 +// CHECK19-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP84]], align 4 +// CHECK19-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 +// CHECK19-NEXT: store i8* null, i8** [[TMP85]], align 4 +// CHECK19-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 +// CHECK19-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** +// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP87]], align 4 +// CHECK19-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 +// CHECK19-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** +// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP89]], align 4 +// CHECK19-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK19-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 4 +// CHECK19-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 +// CHECK19-NEXT: store i8* null, i8** [[TMP91]], align 4 +// CHECK19-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 +// CHECK19-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 4 +// CHECK19-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 +// CHECK19-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 4 +// CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 +// CHECK19-NEXT: store i8* null, i8** [[TMP96]], align 4 +// CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK19-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK19-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK19: omp_offload.failed16: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK19: omp_offload.cont17: +// CHECK19-NEXT: br label [[OMP_IF_END19:%.*]] +// CHECK19: omp_if.else18: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_IF_END19]] +// CHECK19: omp_if.end19: +// CHECK19-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) +// CHECK19-NEXT: ret i32 [[TMP102]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK19-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK19-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] +// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK19: omp_offload.failed.i: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] +// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK19: .omp_outlined..1.exit: +// CHECK19-NEXT: ret i32 0 +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 +// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK19-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK19-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK19: .cancel.exit: +// CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK19-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK19: .cancel.continue: +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK19-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK19-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK19-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK19-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK19-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK19-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK19-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK19-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK19-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK19-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK19-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK19-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK19-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK19-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK19-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK19-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK19-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK19-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3bari +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP8]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK19-NEXT: store double* [[A]], double** [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK19-NEXT: store i32 2, i32* [[TMP22]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK19-NEXT: store i32 2, i32* [[TMP24]], align 4 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 +// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 +// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 +// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK19-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK19-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] +// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK19-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] +// CHECK19-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK19-NEXT: ret i32 [[ADD3]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP31]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP24]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK19-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK19-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK19-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK19-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK19-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK19-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] +// CHECK20-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK20-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* +// CHECK20-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 +// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK20-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* +// CHECK20-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP31]], align 4 +// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* +// CHECK20-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 +// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* +// CHECK20-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 +// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 +// CHECK20-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK20: omp_offload.failed8: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK20: omp_offload.cont9: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 +// CHECK20-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 +// CHECK20-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 +// CHECK20-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] +// CHECK20: omp_if.then12: +// CHECK20-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK20-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 +// CHECK20-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK20-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 +// CHECK20-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 +// CHECK20-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i32 72, i1 false) +// CHECK20-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* +// CHECK20-NEXT: store i32 [[TMP42]], i32* [[TMP51]], align 4 +// CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* +// CHECK20-NEXT: store i32 [[TMP42]], i32* [[TMP53]], align 4 +// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 +// CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 +// CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 +// CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP59]], align 4 +// CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP61]], align 4 +// CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP63]], align 4 +// CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP64]], align 4 +// CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** +// CHECK20-NEXT: store float* [[VLA]], float** [[TMP66]], align 4 +// CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** +// CHECK20-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 +// CHECK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK20-NEXT: store i64 [[TMP45]], i64* [[TMP69]], align 4 +// CHECK20-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP70]], align 4 +// CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 4 +// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 +// CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 +// CHECK20-NEXT: store i8* null, i8** [[TMP75]], align 4 +// CHECK20-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 +// CHECK20-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* +// CHECK20-NEXT: store i32 5, i32* [[TMP77]], align 4 +// CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 +// CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK20-NEXT: store i32 5, i32* [[TMP79]], align 4 +// CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 +// CHECK20-NEXT: store i8* null, i8** [[TMP80]], align 4 +// CHECK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 +// CHECK20-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP82]], align 4 +// CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 +// CHECK20-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP84]], align 4 +// CHECK20-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 +// CHECK20-NEXT: store i8* null, i8** [[TMP85]], align 4 +// CHECK20-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 +// CHECK20-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** +// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP87]], align 4 +// CHECK20-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 +// CHECK20-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** +// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP89]], align 4 +// CHECK20-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK20-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 4 +// CHECK20-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 +// CHECK20-NEXT: store i8* null, i8** [[TMP91]], align 4 +// CHECK20-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 +// CHECK20-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 4 +// CHECK20-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 +// CHECK20-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 4 +// CHECK20-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 +// CHECK20-NEXT: store i8* null, i8** [[TMP96]], align 4 +// CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 +// CHECK20-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK20: omp_offload.failed16: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK20: omp_offload.cont17: +// CHECK20-NEXT: br label [[OMP_IF_END19:%.*]] +// CHECK20: omp_if.else18: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END19]] +// CHECK20: omp_if.end19: +// CHECK20-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) +// CHECK20-NEXT: ret i32 [[TMP102]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK20-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK20-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] +// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK20: omp_offload.failed.i: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] +// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK20: .omp_outlined..1.exit: +// CHECK20-NEXT: ret i32 0 +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 +// CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK20-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK20-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK20: .cancel.exit: +// CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK20-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK20: .cancel.continue: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK20-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK20-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK20-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK20-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK20-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK20-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK20-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK20-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK20-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK20-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK20-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK20-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK20-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK20-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK20-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK20-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK20-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3bari +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP8]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK20-NEXT: store double* [[A]], double** [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK20-NEXT: store i32 2, i32* [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK20-NEXT: store i32 2, i32* [[TMP24]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 +// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 +// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 +// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK20-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] +// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] +// CHECK20-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK20-NEXT: ret i32 [[ADD3]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP31]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP24]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK20-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK20-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK20-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK20-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK20-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK25-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK25-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK25-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK25-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK25: .cancel.exit: +// CHECK25-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK25-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK25: .cancel.continue: +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK25-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK25-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK25-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK25-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK25-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK25-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK25-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK25-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK26-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK26-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK26-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK26-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK26: .cancel.exit: +// CHECK26-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK26-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK26: .cancel.continue: +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK26-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK26-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK26-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK26-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK26-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK26-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK26-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK26-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK27-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK27-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK27-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK27: .cancel.exit: +// CHECK27-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK27-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK27: .cancel.continue: +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK27-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK27-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK27-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK27-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK27-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK27-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK27-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK27-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK27-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK27-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK27-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK27-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK27-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK27-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK27-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK27-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK27-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 +// CHECK28-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) +// CHECK28-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +// CHECK28-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK28: .cancel.exit: +// CHECK28-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) +// CHECK28-NEXT: br label [[DOTCANCEL_CONTINUE]] +// CHECK28: .cancel.continue: +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 +// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK28-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK28-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK28-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK28-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK28-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK28-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK28-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK28-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK28-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK28-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK28-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK28-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK28-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK28-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK28-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK28-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK28-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_parallel_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_debug_codegen.cpp --- a/clang/test/OpenMP/target_parallel_debug_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_debug_codegen.cpp @@ -65,7 +65,7 @@ return 0; } // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]]* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG23:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG23:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -124,7 +124,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]]* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG52:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG52:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -219,7 +219,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG100:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG100:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -256,7 +256,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5:[0-9]+]] !dbg [[DBG115:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5:[0-9]+]] !dbg [[DBG115:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -285,7 +285,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG124:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG124:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -345,7 +345,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG142:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG142:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -428,7 +428,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG183:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG183:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -466,7 +466,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG192:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG192:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -496,7 +496,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 addrspace(1)* noalias noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG199:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG199:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32 addrspace(1)*, align 8 @@ -556,7 +556,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 addrspace(1)* noalias noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG217:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG217:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -648,7 +648,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG259:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG259:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -687,7 +687,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG270:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG270:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/target_parallel_for_codegen.cpp b/clang/test/OpenMP/target_parallel_for_codegen.cpp --- a/clang/test/OpenMP/target_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_codegen.cpp @@ -3782,7 +3782,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3859,7 +3859,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -3890,7 +3890,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3921,7 +3921,7 @@ // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -4008,7 +4008,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -4031,7 +4031,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4106,7 +4106,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -4153,7 +4153,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4298,7 +4298,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -4332,7 +4332,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4356,7 +4356,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4383,7 +4383,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4472,7 +4472,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -4498,7 +4498,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4578,6 +4578,810 @@ // CHECK9-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK10-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK10-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK10: .cancel.exit: +// CHECK10-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK10: .cancel.continue: +// CHECK10-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK10-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK10-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK10: .cancel.exit2: +// CHECK10-NEXT: br label [[CANCEL_EXIT]] +// CHECK10: .cancel.continue3: +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK10: cancel.cont: +// CHECK10-NEXT: ret void +// CHECK10: cancel.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK10-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[LIN4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[A5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 +// CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK10-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK10-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK10-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK10-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK10-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] +// CHECK10-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK10-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK10-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] +// CHECK10-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 +// CHECK10-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 +// CHECK10-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK10-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK10: .omp.linear.pu: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 +// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 +// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK10: .omp.linear.pu.done: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: ret i64 0 +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK10-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK10-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK10-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 +// CHECK10-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK10-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 +// CHECK10-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK10-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK10-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 +// CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK10-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 +// CHECK10-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK10-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK10-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK10-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK10-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 +// CHECK10-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK10-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 +// CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 +// CHECK10-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK10-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 +// CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK10-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK10-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK10-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK10-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK10-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK10-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK10-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK10-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK10-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 +// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK10-NEXT: store double [[INC]], double* [[A5]], align 8 +// CHECK10-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK10-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK10-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 +// CHECK10-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK10-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK10-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK10-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: @@ -4586,7 +5390,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4663,7 +5467,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -4690,7 +5494,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4719,7 +5523,7 @@ // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK11-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK11-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -4806,7 +5610,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4827,7 +5631,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4901,7 +5705,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -4944,7 +5748,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5087,7 +5891,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5119,7 +5923,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5142,7 +5946,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5167,7 +5971,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5255,7 +6059,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5279,7 +6083,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5358,6 +6162,786 @@ // CHECK11-NEXT: ret void // // +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK12-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK12-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK12: .cancel.exit: +// CHECK12-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK12: .cancel.continue: +// CHECK12-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK12-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK12-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK12: .cancel.exit2: +// CHECK12-NEXT: br label [[CANCEL_EXIT]] +// CHECK12: .cancel.continue3: +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK12-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK12: cancel.cont: +// CHECK12-NEXT: ret void +// CHECK12: cancel.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK12-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK12-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK12-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK12-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK12-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK12-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK12-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK12-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK12-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK12-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK12-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK12-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK12-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK12-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK12-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK12-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK12-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK12-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK12-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK12: .omp.linear.pu: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 +// CHECK12-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 +// CHECK12-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK12: .omp.linear.pu.done: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: ret i64 0 +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK12-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK12-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK12-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK12-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK12-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK12-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK12-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK12-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK12-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 +// CHECK12-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK12-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK12-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK12-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 +// CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK12-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK12-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK12-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK12-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 +// CHECK12-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK12-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 +// CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 +// CHECK12-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK12-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 +// CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK12-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK12-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK12-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK12-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK12-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK12-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK12-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK12-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK12-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK12-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK12-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 +// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK12-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK12-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK12-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 +// CHECK12-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK12-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK12-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK12-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK12-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -8815,3 +10399,4745 @@ // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) // CHECK19-NEXT: ret void // +// +// CHECK20-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: ret i64 0 +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK20-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK20-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 +// CHECK20-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK20-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] +// CHECK20-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK20-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK20-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK20-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 +// CHECK20-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) +// CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* +// CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) +// CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* +// CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) +// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 +// CHECK20-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK20-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 +// CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 +// CHECK20-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK20-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 +// CHECK20-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK20-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* +// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 +// CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* +// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 +// CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP66]], align 4 +// CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* +// CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 +// CHECK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* +// CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 +// CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP71]], align 4 +// CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 +// CHECK20-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] +// CHECK20: omp_offload.failed9: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT10]] +// CHECK20: omp_offload.cont10: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 +// CHECK20-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 +// CHECK20-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 +// CHECK20-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] +// CHECK20: omp_if.then13: +// CHECK20-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK20-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 +// CHECK20-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK20-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 +// CHECK20-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 +// CHECK20-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) +// CHECK20-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32* +// CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4 +// CHECK20-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32* +// CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4 +// CHECK20-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP92]], align 4 +// CHECK20-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 +// CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 +// CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP97]], align 4 +// CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4 +// CHECK20-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4 +// CHECK20-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP102]], align 4 +// CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float** +// CHECK20-NEXT: store float* [[VLA]], float** [[TMP104]], align 4 +// CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** +// CHECK20-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 +// CHECK20-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK20-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4 +// CHECK20-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP108]], align 4 +// CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]** +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4 +// CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 +// CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 +// CHECK20-NEXT: store i8* null, i8** [[TMP113]], align 4 +// CHECK20-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 +// CHECK20-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* +// CHECK20-NEXT: store i32 5, i32* [[TMP115]], align 4 +// CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 +// CHECK20-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* +// CHECK20-NEXT: store i32 5, i32* [[TMP117]], align 4 +// CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 +// CHECK20-NEXT: store i8* null, i8** [[TMP118]], align 4 +// CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 +// CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4 +// CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 +// CHECK20-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4 +// CHECK20-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 +// CHECK20-NEXT: store i8* null, i8** [[TMP123]], align 4 +// CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 +// CHECK20-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double** +// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4 +// CHECK20-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 +// CHECK20-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** +// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4 +// CHECK20-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK20-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4 +// CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 +// CHECK20-NEXT: store i8* null, i8** [[TMP129]], align 4 +// CHECK20-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 +// CHECK20-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT** +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4 +// CHECK20-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 +// CHECK20-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4 +// CHECK20-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 +// CHECK20-NEXT: store i8* null, i8** [[TMP134]], align 4 +// CHECK20-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 +// CHECK20-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32* +// CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4 +// CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 +// CHECK20-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32* +// CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4 +// CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 +// CHECK20-NEXT: store i8* null, i8** [[TMP139]], align 4 +// CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0 +// CHECK20-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK20: omp_offload.failed17: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK20: omp_offload.cont18: +// CHECK20-NEXT: br label [[OMP_IF_END20:%.*]] +// CHECK20: omp_if.else19: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END20]] +// CHECK20: omp_if.end20: +// CHECK20-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP146]]) +// CHECK20-NEXT: ret i32 [[TMP145]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK20-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK20-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK20: .cancel.exit: +// CHECK20-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK20: .cancel.continue: +// CHECK20-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK20-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK20-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK20: .cancel.exit2: +// CHECK20-NEXT: br label [[CANCEL_EXIT]] +// CHECK20: .cancel.continue3: +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK20: cancel.cont: +// CHECK20-NEXT: ret void +// CHECK20: cancel.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[K1:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 +// CHECK20-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK20: omp.dispatch.cond: +// CHECK20-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) +// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 +// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK20: omp.dispatch.body: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] +// CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK20-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 +// CHECK20-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] +// CHECK20-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK20: omp.dispatch.inc: +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK20: omp.dispatch.end: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK20: .omp.linear.pu: +// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 +// CHECK20-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 +// CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK20: .omp.linear.pu.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) +// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK20-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK20-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK20-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK20-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK20-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK20-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK20: .omp.linear.pu: +// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 +// CHECK20-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 +// CHECK20-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK20: .omp.linear.pu.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] +// CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] +// CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK20-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] +// CHECK20: omp_offload.failed.i: +// CHECK20-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK20-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 +// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK20-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK20-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] +// CHECK20: .omp_outlined..3.exit: +// CHECK20-NEXT: ret i32 0 +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK20: omp.dispatch.cond: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK20: omp.dispatch.body: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK20-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK20-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 +// CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 +// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK20-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK20-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 +// CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 +// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 +// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 +// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK20: omp.dispatch.inc: +// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK20-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK20: omp.dispatch.end: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3bari +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP8]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK20-NEXT: store double* [[A]], double** [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK20-NEXT: store i32 2, i32* [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK20-NEXT: store i32 2, i32* [[TMP24]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 +// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 +// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 +// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK20-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] +// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] +// CHECK20-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK20-NEXT: ret i32 [[ADD3]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP31]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP24]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK20-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 +// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK20-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK20-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 +// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK20-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK20-SAME: () #[[ATTR6]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK20-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK25-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK25-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK25-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK25: .cancel.exit: +// CHECK25-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK25: .cancel.continue: +// CHECK25-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK25-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK25-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK25: .cancel.exit2: +// CHECK25-NEXT: br label [[CANCEL_EXIT]] +// CHECK25: .cancel.continue3: +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK25-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK25-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK25: cancel.cont: +// CHECK25-NEXT: ret void +// CHECK25: cancel.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK25-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK25-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 +// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[LIN4:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A5:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 +// CHECK25-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK25-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK25-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK25-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK25-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK25-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] +// CHECK25-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK25-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 +// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK25-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK25-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK25-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] +// CHECK25-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 +// CHECK25-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 +// CHECK25-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 +// CHECK25-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK25-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK25: .omp.linear.pu: +// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 +// CHECK25-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 +// CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 +// CHECK25-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK25: .omp.linear.pu.done: +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK25-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: ret i64 0 +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK25-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK25-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK25-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 +// CHECK25-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK25-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK25: omp.dispatch.cond: +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK25: omp.dispatch.body: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK25-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 +// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 +// CHECK25-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK25-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK25-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 +// CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK25-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 +// CHECK25-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 +// CHECK25-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK25-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK25-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK25-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 +// CHECK25-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 +// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 +// CHECK25-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK25-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 +// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK25-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK25-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK25-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK25-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK25-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK25-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK25: omp.dispatch.inc: +// CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK25-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK25-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK25: omp.dispatch.end: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK25-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 +// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK25-NEXT: store double [[INC]], double* [[A5]], align 8 +// CHECK25-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK25-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK25-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK25-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 +// CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK25-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK26-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK26-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK26-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK26: .cancel.exit: +// CHECK26-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK26: .cancel.continue: +// CHECK26-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK26-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK26-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK26: .cancel.exit2: +// CHECK26-NEXT: br label [[CANCEL_EXIT]] +// CHECK26: .cancel.continue3: +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK26-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK26-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK26: cancel.cont: +// CHECK26-NEXT: ret void +// CHECK26: cancel.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK26-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 +// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[LIN4:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A5:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 +// CHECK26-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK26-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK26-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK26-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK26-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK26-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] +// CHECK26-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK26-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 +// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 +// CHECK26-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK26-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK26-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] +// CHECK26-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 +// CHECK26-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 +// CHECK26-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 +// CHECK26-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK26-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK26: .omp.linear.pu: +// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 +// CHECK26-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 +// CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 +// CHECK26-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK26: .omp.linear.pu.done: +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK26-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: ret i64 0 +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK26-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK26-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK26-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 +// CHECK26-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK26-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK26: omp.dispatch.cond: +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK26: omp.dispatch.body: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK26-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 +// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 +// CHECK26-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK26-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK26-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 +// CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK26-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 +// CHECK26-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 +// CHECK26-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK26-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK26-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK26-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 +// CHECK26-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 +// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 +// CHECK26-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK26-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 +// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK26-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK26-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK26-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK26-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK26-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK26-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK26: omp.dispatch.inc: +// CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK26-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK26-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK26: omp.dispatch.end: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK26-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 +// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK26-NEXT: store double [[INC]], double* [[A5]], align 8 +// CHECK26-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK26-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK26-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK26-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 +// CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK26-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK27-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK27-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK27-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK27: .cancel.exit: +// CHECK27-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK27: .cancel.continue: +// CHECK27-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK27-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK27-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK27: .cancel.exit2: +// CHECK27-NEXT: br label [[CANCEL_EXIT]] +// CHECK27: .cancel.continue3: +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK27-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK27-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK27: cancel.cont: +// CHECK27-NEXT: ret void +// CHECK27: cancel.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK27-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK27-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK27-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK27-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK27-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK27-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK27-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK27-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK27-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK27-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 +// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK27-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK27-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK27-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK27-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK27-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 +// CHECK27-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK27-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK27-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK27: .omp.linear.pu: +// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 +// CHECK27-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 +// CHECK27-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK27: .omp.linear.pu.done: +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK27-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: ret i64 0 +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK27-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK27-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK27-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK27-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK27-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK27: omp.dispatch.cond: +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK27: omp.dispatch.body: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK27-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK27-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK27-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 +// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK27-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK27-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK27-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK27-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 +// CHECK27-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK27-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK27-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK27-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 +// CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK27-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK27-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK27-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK27-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 +// CHECK27-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 +// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 +// CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK27-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 +// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK27-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK27-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK27-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK27-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK27-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK27-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK27: omp.dispatch.inc: +// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK27-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK27-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK27: omp.dispatch.end: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK27-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK27-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 +// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK27-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK27-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK27-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK27-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK27-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 +// CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK27-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK27-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK27-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK28-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK28-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK28-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK28: .cancel.exit: +// CHECK28-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK28: .cancel.continue: +// CHECK28-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) +// CHECK28-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK28-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] +// CHECK28: .cancel.exit2: +// CHECK28-NEXT: br label [[CANCEL_EXIT]] +// CHECK28: .cancel.continue3: +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK28-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK28-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK28: cancel.cont: +// CHECK28-NEXT: ret void +// CHECK28: cancel.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK28-NEXT: br label [[CANCEL_CONT]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 +// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK28-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK28-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK28-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK28-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 +// CHECK28-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK28-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK28-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK28-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK28-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 +// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 +// CHECK28-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 +// CHECK28-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK28-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK28-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK28-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 +// CHECK28-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK28-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK28-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK28: .omp.linear.pu: +// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 +// CHECK28-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 +// CHECK28-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK28: .omp.linear.pu.done: +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK28-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: ret i64 0 +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK28-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK28-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK28-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK28-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 +// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK28-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK28: omp.dispatch.cond: +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK28: omp.dispatch.body: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK28-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK28-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK28-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 +// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK28-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK28-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK28-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK28-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 +// CHECK28-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK28-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK28-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK28-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 +// CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK28-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK28-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK28-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK28-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 +// CHECK28-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 +// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 +// CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK28-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 +// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK28-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK28-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK28-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK28-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK28-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK28-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK28: omp.dispatch.inc: +// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK28-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK28-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK28: omp.dispatch.end: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK28-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK28-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 +// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK28-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK28-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK28-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK28-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK28-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 +// CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK28-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK28-NEXT: store i64 [[ADD]], i64* [[I]], align 8 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK28-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp --- a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp @@ -55,7 +55,7 @@ return 0; } // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]]* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]], i1 noundef zeroext [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG13:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]], i1 zeroext [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG13:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -121,7 +121,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]]* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG47:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG47:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -289,7 +289,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG108:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG108:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -326,7 +326,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR5:[0-9]+]] !dbg [[DBG123:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR5:[0-9]+]] !dbg [[DBG123:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -361,7 +361,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG133:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG133:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -421,7 +421,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -577,7 +577,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG205:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG205:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -615,7 +615,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG214:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG214:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -645,7 +645,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 addrspace(1)* noalias noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG223:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG223:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32 addrspace(1)*, align 8 @@ -705,7 +705,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 addrspace(1)* noalias noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG241:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG241:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -870,7 +870,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG296:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG296:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -909,7 +909,7 @@ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG307:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG307:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp --- a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp @@ -9209,7 +9209,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9276,7 +9276,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -9307,7 +9307,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9338,7 +9338,7 @@ // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -9432,7 +9432,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9455,7 +9455,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9537,7 +9537,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -9584,7 +9584,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9736,7 +9736,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9770,7 +9770,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9794,7 +9794,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -9821,7 +9821,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9917,7 +9917,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9943,7 +9943,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10030,6 +10030,835 @@ // CHECK17-NEXT: ret void // // +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 +// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK18-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 +// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[LIN4:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A5:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 +// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17 +// CHECK18-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK18-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] +// CHECK18-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK18-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17 +// CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] +// CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 +// CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17 +// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17 +// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 +// CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK18-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK18: .omp.linear.pu: +// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 +// CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 +// CHECK18-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK18: .omp.linear.pu.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: ret i64 0 +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20 +// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20 +// CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 +// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK18-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i16 22, i16* [[IT]], align 2 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 +// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK18: omp.dispatch.cond: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK18: omp.dispatch.body: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23 +// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK18-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23 +// CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23 +// CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK18-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK18-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK18-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23 +// CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23 +// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23 +// CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23 +// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23 +// CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK18: omp.dispatch.inc: +// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK18-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK18: omp.dispatch.end: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK18-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK18-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i8 96, i8* [[IT]], align 1 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK18-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 +// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26 +// CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 +// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26 +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26 +// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26 +// CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26 +// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26 +// CHECK18-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK18-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK18-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !26 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 +// CHECK18-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 +// CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK18-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK18-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 +// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !29 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !29 +// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !29 +// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !29 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29 +// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 +// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK18-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: @@ -10038,7 +10867,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10105,7 +10934,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -10132,7 +10961,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10161,7 +10990,7 @@ // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK19-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -10255,7 +11084,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10276,7 +11105,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10357,7 +11186,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -10400,7 +11229,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10550,7 +11379,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10582,7 +11411,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10605,7 +11434,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -10630,7 +11459,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10725,7 +11554,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10749,7 +11578,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10835,6 +11664,811 @@ // CHECK19-NEXT: ret void // // +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 +// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK20-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 +// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18 +// CHECK20-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK20-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK20-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK20-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18 +// CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18 +// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18 +// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK20-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK20-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK20: .omp.linear.pu: +// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 +// CHECK20-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 +// CHECK20-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK20: .omp.linear.pu.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: ret i64 0 +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21 +// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21 +// CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK20-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i16 22, i16* [[IT]], align 2 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 +// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK20: omp.dispatch.cond: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK20: omp.dispatch.body: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK20-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK20-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 +// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 +// CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK20-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK20-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 +// CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 +// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK20: omp.dispatch.inc: +// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK20-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK20: omp.dispatch.end: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK20-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i8 96, i8* [[IT]], align 1 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 +// CHECK20-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27 +// CHECK20-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 +// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 +// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4, !llvm.access.group !27 +// CHECK20-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !27 +// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK20-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !27 +// CHECK20-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !27 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 +// CHECK20-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 +// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK20-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK20-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK20-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 +// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30 +// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30 +// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !30 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 +// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: @@ -10843,7 +12477,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10910,7 +12544,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -10941,7 +12575,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10972,7 +12606,7 @@ // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -11066,7 +12700,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -11089,7 +12723,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11171,7 +12805,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK21-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -11218,7 +12852,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11370,7 +13004,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -11404,7 +13038,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11428,7 +13062,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK21-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -11481,7 +13115,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11640,7 +13274,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -11666,7 +13300,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11753,6 +13387,924 @@ // CHECK21-NEXT: ret void // // +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 +// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK22-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK22-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 +// CHECK22-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK22-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 +// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[LIN4:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[A5:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 +// CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 +// CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK22-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK22-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK22-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK22-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK22-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK22-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17 +// CHECK22-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK22-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] +// CHECK22-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK22-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17 +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17 +// CHECK22-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK22-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK22-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] +// CHECK22-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 +// CHECK22-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17 +// CHECK22-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17 +// CHECK22-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK22-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 +// CHECK22-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK22-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK22-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK22: .omp.linear.pu: +// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 +// CHECK22-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 +// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 +// CHECK22-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK22: .omp.linear.pu.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK22-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: ret i64 0 +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 +// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK22-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK22-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20 +// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK22-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20 +// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20 +// CHECK22-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK22-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 +// CHECK22-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK22-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK22-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK22-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i16 22, i16* [[IT]], align 2 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 +// CHECK22-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK22-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK22-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK22-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK22-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK22-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK22-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK22-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK22-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK22: omp.dispatch.cond: +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK22-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK22: omp.dispatch.body: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK22-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK22-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK22-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23 +// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK22-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK22-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK22-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK22-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK22-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK22-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK22-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK22-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK22-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK22-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK22-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23 +// CHECK22-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK22-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23 +// CHECK22-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK22-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK22-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK22-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23 +// CHECK22-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK22-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23 +// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK22-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23 +// CHECK22-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK22-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23 +// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK22-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23 +// CHECK22-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK22-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK22-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK22-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK22-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK22: omp.dispatch.inc: +// CHECK22-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK22-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK22-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK22: omp.dispatch.end: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK22-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK22-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i8 96, i8* [[IT]], align 1 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK22-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 +// CHECK22-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4 +// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 +// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK22-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 +// CHECK22-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK22: omp_if.then: +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) +// CHECK22-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK22: omp_if.else: +// CHECK22-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) +// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK22-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] +// CHECK22-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) +// CHECK22-NEXT: br label [[OMP_IF_END]] +// CHECK22: omp_if.end: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK22: omp_if.then: +// CHECK22-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK22-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 +// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26 +// CHECK22-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] +// CHECK22-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 +// CHECK22-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 +// CHECK22-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26 +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26 +// CHECK22-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double +// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00 +// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26 +// CHECK22-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK22-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26 +// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 +// CHECK22-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26 +// CHECK22-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK22-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]] +// CHECK22-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK22-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !26 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 +// CHECK22-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1 +// CHECK22-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK22: omp_if.else: +// CHECK22-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK22-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3 +// CHECK22-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK22: cond.true11: +// CHECK22-NEXT: br label [[COND_END13:%.*]] +// CHECK22: cond.false12: +// CHECK22-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: br label [[COND_END13]] +// CHECK22: cond.end13: +// CHECK22-NEXT: [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ] +// CHECK22-NEXT: store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK22-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND15:%.*]] +// CHECK22: omp.inner.for.cond15: +// CHECK22-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK22-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] +// CHECK22-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]] +// CHECK22: omp.inner.for.body17: +// CHECK22-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK22-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400 +// CHECK22-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]] +// CHECK22-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8 +// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double +// CHECK22-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00 +// CHECK22-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK22-NEXT: store double [[ADD21]], double* [[A22]], align 8 +// CHECK22-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK22-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8 +// CHECK22-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00 +// CHECK22-NEXT: store double [[INC24]], double* [[A23]], align 8 +// CHECK22-NEXT: [[CONV25:%.*]] = fptosi double [[INC24]] to i16 +// CHECK22-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK22-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]] +// CHECK22-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1 +// CHECK22-NEXT: store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] +// CHECK22: omp.body.continue28: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC29:%.*]] +// CHECK22: omp.inner.for.inc29: +// CHECK22-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK22-NEXT: [[ADD30:%.*]] = add i64 [[TMP28]], 1 +// CHECK22-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP30:![0-9]+]] +// CHECK22: omp.inner.for.end31: +// CHECK22-NEXT: br label [[OMP_IF_END]] +// CHECK22: omp_if.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK22-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK22-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK22-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK22-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 +// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32 +// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK22-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32 +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32 +// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32 +// CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32 +// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32 +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32 +// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK22-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 +// CHECK22-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK22-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK22-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: @@ -11761,7 +14313,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11828,7 +14380,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -11855,7 +14407,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11884,7 +14436,7 @@ // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK23-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK23-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -11978,7 +14530,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11999,7 +14551,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12080,7 +14632,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK23-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -12123,7 +14675,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12273,7 +14825,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -12305,7 +14857,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12328,7 +14880,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK23-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -12379,7 +14931,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12537,7 +15089,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -12561,7 +15113,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12646,3 +15198,4905 @@ // CHECK23: .omp.final.done: // CHECK23-NEXT: ret void // +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 +// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK24-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK24-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 +// CHECK24-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK24-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK24-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[LIN2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[A3:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 +// CHECK24-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK24-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK24-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK24-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK24-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK24-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK24-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK24-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK24-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18 +// CHECK24-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK24-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] +// CHECK24-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] +// CHECK24-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK24-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18 +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18 +// CHECK24-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK24-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] +// CHECK24-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] +// CHECK24-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 +// CHECK24-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18 +// CHECK24-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18 +// CHECK24-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 +// CHECK24-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK24-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 +// CHECK24-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) +// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 +// CHECK24-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK24-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK24: .omp.linear.pu: +// CHECK24-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 +// CHECK24-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 +// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 +// CHECK24-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK24: .omp.linear.pu.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK24-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: ret i64 0 +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i16, align 2 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[IT:%.*]] = alloca i16, align 2 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] +// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK24-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21 +// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK24-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21 +// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21 +// CHECK24-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK24-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK24-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK24-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK24-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i16 22, i16* [[IT]], align 2 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 +// CHECK24-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK24-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK24-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK24-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK24-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i8, align 1 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[IT:%.*]] = alloca i8, align 1 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK24-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK24-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK24-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK24-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK24-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK24: omp.dispatch.cond: +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK24-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK24: omp.dispatch.body: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK24-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] +// CHECK24-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 +// CHECK24-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24 +// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK24-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK24-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double +// CHECK24-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK24-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK24-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK24-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK24-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK24-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK24-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK24-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK24-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 +// CHECK24-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK24-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 +// CHECK24-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK24-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK24-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK24-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 +// CHECK24-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK24-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 +// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK24-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK24-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK24-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK24-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK24-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK24-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK24-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK24: omp.dispatch.inc: +// CHECK24-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK24-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK24-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK24: omp.dispatch.end: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK24-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 +// CHECK24-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i8 96, i8* [[IT]], align 1 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK24-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK24-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 +// CHECK24-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK24-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 +// CHECK24-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK24: omp_if.then: +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) +// CHECK24-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK24: omp_if.else: +// CHECK24-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) +// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK24-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]] +// CHECK24-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) +// CHECK24-NEXT: br label [[OMP_IF_END]] +// CHECK24: omp_if.end: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK24: omp_if.then: +// CHECK24-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK24-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK24-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 +// CHECK24-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27 +// CHECK24-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] +// CHECK24-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 +// CHECK24-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 +// CHECK24-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK24-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27 +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27 +// CHECK24-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double +// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4, !nontemporal !28, !llvm.access.group !27 +// CHECK24-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK24-NEXT: [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27 +// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 +// CHECK24-NEXT: store double [[INC]], double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27 +// CHECK24-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK24-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]] +// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK24-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !27 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 +// CHECK24-NEXT: [[ADD8:%.*]] = add i64 [[TMP16]], 1 +// CHECK24-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK24: omp_if.else: +// CHECK24-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK24-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3 +// CHECK24-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK24: cond.true10: +// CHECK24-NEXT: br label [[COND_END12:%.*]] +// CHECK24: cond.false11: +// CHECK24-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: br label [[COND_END12]] +// CHECK24: cond.end12: +// CHECK24-NEXT: [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ] +// CHECK24-NEXT: store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK24-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND14:%.*]] +// CHECK24: omp.inner.for.cond14: +// CHECK24-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK24-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] +// CHECK24-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]] +// CHECK24: omp.inner.for.body16: +// CHECK24-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK24-NEXT: [[MUL17:%.*]] = mul i64 [[TMP24]], 400 +// CHECK24-NEXT: [[SUB18:%.*]] = sub i64 2000, [[MUL17]] +// CHECK24-NEXT: store i64 [[SUB18]], i64* [[IT]], align 8 +// CHECK24-NEXT: [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double +// CHECK24-NEXT: [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00 +// CHECK24-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK24-NEXT: store double [[ADD20]], double* [[A21]], align 4 +// CHECK24-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK24-NEXT: [[TMP26:%.*]] = load double, double* [[A22]], align 4 +// CHECK24-NEXT: [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00 +// CHECK24-NEXT: store double [[INC23]], double* [[A22]], align 4 +// CHECK24-NEXT: [[CONV24:%.*]] = fptosi double [[INC23]] to i16 +// CHECK24-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK24-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]] +// CHECK24-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1 +// CHECK24-NEXT: store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] +// CHECK24: omp.body.continue27: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] +// CHECK24: omp.inner.for.inc28: +// CHECK24-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK24-NEXT: [[ADD29:%.*]] = add i64 [[TMP28]], 1 +// CHECK24-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK24: omp.inner.for.end30: +// CHECK24-NEXT: br label [[OMP_IF_END]] +// CHECK24: omp_if.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) +// CHECK24-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 +// CHECK24-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK24-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK24-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 +// CHECK24-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK24-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 +// CHECK24-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !33 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK24-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33 +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 +// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 +// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33 +// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33 +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 +// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 +// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 +// CHECK24-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK24-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK25-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: ret i64 0 +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK25-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK25-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK25-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[K8:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[LIN27:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A28:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[IT53:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[IT72:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK25-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK25-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK25-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 +// CHECK25-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK25-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 +// CHECK25-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK25-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK25-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK25-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 +// CHECK25-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 +// CHECK25-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4 +// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8 +// CHECK25-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK25: omp.inner.for.cond9: +// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6 +// CHECK25-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK25-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK25: omp.inner.for.body11: +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK25-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] +// CHECK25-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6 +// CHECK25-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6 +// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK25-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 +// CHECK25-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 +// CHECK25-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] +// CHECK25-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6 +// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6 +// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK25-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK25: omp.body.continue16: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK25: omp.inner.for.inc17: +// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK25-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK25: omp.inner.for.end19: +// CHECK25-NEXT: store i32 1, i32* [[I7]], align 4 +// CHECK25-NEXT: [[TMP20:%.*]] = load i64, i64* [[K8]], align 8 +// CHECK25-NEXT: store i64 [[TMP20]], i64* [[K]], align 8 +// CHECK25-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 +// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 +// CHECK25-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 +// CHECK25-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV23]], align 8 +// CHECK25-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK25-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START24]], align 4 +// CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START25]], align 4 +// CHECK25-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK25-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// CHECK25: omp.inner.for.cond29: +// CHECK25-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] +// CHECK25-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// CHECK25: omp.inner.for.body31: +// CHECK25-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 +// CHECK25-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] +// CHECK25-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK25-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] +// CHECK25-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] +// CHECK25-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK25-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 +// CHECK25-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] +// CHECK25-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] +// CHECK25-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 +// CHECK25-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK25-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 +// CHECK25-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 +// CHECK25-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 +// CHECK25-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// CHECK25: omp.body.continue45: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// CHECK25: omp.inner.for.inc46: +// CHECK25-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 +// CHECK25-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK25: omp.inner.for.end48: +// CHECK25-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK25-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN27]], align 4 +// CHECK25-NEXT: store i32 [[TMP35]], i32* [[LIN]], align 4 +// CHECK25-NEXT: [[TMP36:%.*]] = load i32, i32* [[A28]], align 4 +// CHECK25-NEXT: store i32 [[TMP36]], i32* [[A]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 +// CHECK25-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 +// CHECK25-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 +// CHECK25-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV52]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] +// CHECK25: omp.inner.for.cond54: +// CHECK25-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] +// CHECK25-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] +// CHECK25: omp.inner.for.body56: +// CHECK25-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 +// CHECK25-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] +// CHECK25-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 +// CHECK25-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !12 +// CHECK25-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 +// CHECK25-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK25-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 +// CHECK25-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 +// CHECK25-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 +// CHECK25-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] +// CHECK25: omp.body.continue64: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] +// CHECK25: omp.inner.for.inc65: +// CHECK25-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 +// CHECK25-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK25: omp.inner.for.end67: +// CHECK25-NEXT: store i16 22, i16* [[IT53]], align 2 +// CHECK25-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 +// CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 +// CHECK25-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 +// CHECK25-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV71]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] +// CHECK25: omp.inner.for.cond73: +// CHECK25-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] +// CHECK25-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] +// CHECK25: omp.inner.for.body75: +// CHECK25-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 +// CHECK25-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] +// CHECK25-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 +// CHECK25-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 +// CHECK25-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double +// CHECK25-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 +// CHECK25-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float +// CHECK25-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 +// CHECK25-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double +// CHECK25-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 +// CHECK25-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float +// CHECK25-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 +// CHECK25-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] +// CHECK25-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP53]] +// CHECK25-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i64 3 +// CHECK25-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 +// CHECK25-NEXT: store i64 [[ADD93]], i64* [[X]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK25-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 +// CHECK25-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 +// CHECK25-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 +// CHECK25-NEXT: store i8 [[CONV96]], i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] +// CHECK25: omp.body.continue97: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] +// CHECK25: omp.inner.for.inc98: +// CHECK25-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 +// CHECK25-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK25: omp.inner.for.end100: +// CHECK25-NEXT: store i8 96, i8* [[IT72]], align 1 +// CHECK25-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP59]]) +// CHECK25-NEXT: ret i32 [[TMP58]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z3bari +// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK25-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK25-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK25-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: ret i32 [[TMP8]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK25-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK25-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK25-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK25-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK25-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK25-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400 +// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18 +// CHECK25-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double +// CHECK25-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 +// CHECK25-NEXT: store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK25-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]] +// CHECK25-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK25-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1 +// CHECK25-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK25-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK25-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] +// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 +// CHECK25-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 +// CHECK25-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4 +// CHECK25-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]] +// CHECK25-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) +// CHECK25-NEXT: ret i32 [[ADD10]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK25-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: ret i32 [[TMP0]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK25-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK25-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21 +// CHECK25-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK25-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK25-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 +// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 +// CHECK25-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: ret i32 [[TMP8]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK26-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: ret i64 0 +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK26-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK26-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK26-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[K8:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[LIN27:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A28:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[IT53:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[IT72:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK26-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK26-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK26-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 +// CHECK26-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// CHECK26-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK26-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 +// CHECK26-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK26-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK26-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK26-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 +// CHECK26-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 +// CHECK26-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4 +// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8 +// CHECK26-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK26: omp.inner.for.cond9: +// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6 +// CHECK26-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK26-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK26: omp.inner.for.body11: +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK26-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] +// CHECK26-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6 +// CHECK26-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6 +// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK26-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 +// CHECK26-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 +// CHECK26-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] +// CHECK26-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6 +// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6 +// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK26-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK26: omp.body.continue16: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK26: omp.inner.for.inc17: +// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK26-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK26: omp.inner.for.end19: +// CHECK26-NEXT: store i32 1, i32* [[I7]], align 4 +// CHECK26-NEXT: [[TMP20:%.*]] = load i64, i64* [[K8]], align 8 +// CHECK26-NEXT: store i64 [[TMP20]], i64* [[K]], align 8 +// CHECK26-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 +// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 +// CHECK26-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 +// CHECK26-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV23]], align 8 +// CHECK26-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK26-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START24]], align 4 +// CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START25]], align 4 +// CHECK26-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK26-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// CHECK26: omp.inner.for.cond29: +// CHECK26-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] +// CHECK26-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// CHECK26: omp.inner.for.body31: +// CHECK26-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 +// CHECK26-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] +// CHECK26-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK26-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] +// CHECK26-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] +// CHECK26-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK26-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 +// CHECK26-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] +// CHECK26-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] +// CHECK26-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 +// CHECK26-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK26-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 +// CHECK26-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 +// CHECK26-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 +// CHECK26-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// CHECK26: omp.body.continue45: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// CHECK26: omp.inner.for.inc46: +// CHECK26-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 +// CHECK26-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK26: omp.inner.for.end48: +// CHECK26-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK26-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN27]], align 4 +// CHECK26-NEXT: store i32 [[TMP35]], i32* [[LIN]], align 4 +// CHECK26-NEXT: [[TMP36:%.*]] = load i32, i32* [[A28]], align 4 +// CHECK26-NEXT: store i32 [[TMP36]], i32* [[A]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 +// CHECK26-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 +// CHECK26-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 +// CHECK26-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV52]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] +// CHECK26: omp.inner.for.cond54: +// CHECK26-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] +// CHECK26-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] +// CHECK26: omp.inner.for.body56: +// CHECK26-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 +// CHECK26-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] +// CHECK26-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 +// CHECK26-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !12 +// CHECK26-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 +// CHECK26-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK26-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 +// CHECK26-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 +// CHECK26-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 +// CHECK26-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] +// CHECK26: omp.body.continue64: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] +// CHECK26: omp.inner.for.inc65: +// CHECK26-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 +// CHECK26-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK26: omp.inner.for.end67: +// CHECK26-NEXT: store i16 22, i16* [[IT53]], align 2 +// CHECK26-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 +// CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 +// CHECK26-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 +// CHECK26-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV71]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] +// CHECK26: omp.inner.for.cond73: +// CHECK26-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] +// CHECK26-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] +// CHECK26: omp.inner.for.body75: +// CHECK26-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 +// CHECK26-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] +// CHECK26-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 +// CHECK26-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 +// CHECK26-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double +// CHECK26-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 +// CHECK26-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float +// CHECK26-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 +// CHECK26-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double +// CHECK26-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 +// CHECK26-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float +// CHECK26-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 +// CHECK26-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] +// CHECK26-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP53]] +// CHECK26-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i64 3 +// CHECK26-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 +// CHECK26-NEXT: store i64 [[ADD93]], i64* [[X]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK26-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 +// CHECK26-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 +// CHECK26-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 +// CHECK26-NEXT: store i8 [[CONV96]], i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] +// CHECK26: omp.body.continue97: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] +// CHECK26: omp.inner.for.inc98: +// CHECK26-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 +// CHECK26-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK26: omp.inner.for.end100: +// CHECK26-NEXT: store i8 96, i8* [[IT72]], align 1 +// CHECK26-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP59]]) +// CHECK26-NEXT: ret i32 [[TMP58]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z3bari +// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK26-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK26-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK26-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: ret i32 [[TMP8]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK26-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK26-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK26-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK26-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK26-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK26-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400 +// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18 +// CHECK26-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double +// CHECK26-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 +// CHECK26-NEXT: store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK26-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]] +// CHECK26-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK26-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1 +// CHECK26-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK26-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK26-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] +// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 +// CHECK26-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 +// CHECK26-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4 +// CHECK26-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]] +// CHECK26-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) +// CHECK26-NEXT: ret i32 [[ADD10]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK26-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: ret i32 [[TMP0]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK26-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK26-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21 +// CHECK26-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK26-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK26-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 +// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 +// CHECK26-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: ret i32 [[TMP8]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK27-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: ret i64 0 +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK27-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK27-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK27-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[K8:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 +// CHECK27-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[LIN27:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A28:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[IT53:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[IT72:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK27-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK27-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK27-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 +// CHECK27-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK27-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK27-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK27-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 +// CHECK27-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 +// CHECK27-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4 +// CHECK27-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8 +// CHECK27-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK27: omp.inner.for.cond9: +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7 +// CHECK27-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK27-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK27: omp.inner.for.body11: +// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK27-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] +// CHECK27-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7 +// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7 +// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK27-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 +// CHECK27-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 +// CHECK27-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] +// CHECK27-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7 +// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7 +// CHECK27-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK27-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK27: omp.body.continue16: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK27: omp.inner.for.inc17: +// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK27-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK27-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK27: omp.inner.for.end19: +// CHECK27-NEXT: store i32 1, i32* [[I7]], align 4 +// CHECK27-NEXT: [[TMP18:%.*]] = load i64, i64* [[K8]], align 8 +// CHECK27-NEXT: store i64 [[TMP18]], i64* [[K]], align 8 +// CHECK27-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 +// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 +// CHECK27-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 +// CHECK27-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV23]], align 8 +// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK27-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START24]], align 4 +// CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START25]], align 4 +// CHECK27-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK27-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// CHECK27: omp.inner.for.cond29: +// CHECK27-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] +// CHECK27-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// CHECK27: omp.inner.for.body31: +// CHECK27-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 +// CHECK27-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] +// CHECK27-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK27-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] +// CHECK27-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] +// CHECK27-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK27-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK27-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] +// CHECK27-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] +// CHECK27-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 +// CHECK27-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK27-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 +// CHECK27-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 +// CHECK27-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 +// CHECK27-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// CHECK27: omp.body.continue45: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// CHECK27: omp.inner.for.inc46: +// CHECK27-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 +// CHECK27-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK27: omp.inner.for.end48: +// CHECK27-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK27-NEXT: [[TMP33:%.*]] = load i32, i32* [[LIN27]], align 4 +// CHECK27-NEXT: store i32 [[TMP33]], i32* [[LIN]], align 4 +// CHECK27-NEXT: [[TMP34:%.*]] = load i32, i32* [[A28]], align 4 +// CHECK27-NEXT: store i32 [[TMP34]], i32* [[A]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 +// CHECK27-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 +// CHECK27-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 +// CHECK27-NEXT: store i32 [[TMP35]], i32* [[DOTOMP_IV52]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] +// CHECK27: omp.inner.for.cond54: +// CHECK27-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] +// CHECK27-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] +// CHECK27: omp.inner.for.body56: +// CHECK27-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 +// CHECK27-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] +// CHECK27-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 +// CHECK27-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !13 +// CHECK27-NEXT: [[TMP39:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 +// CHECK27-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[TMP40:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK27-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 +// CHECK27-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 +// CHECK27-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 +// CHECK27-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] +// CHECK27: omp.body.continue64: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] +// CHECK27: omp.inner.for.inc65: +// CHECK27-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 +// CHECK27-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK27: omp.inner.for.end67: +// CHECK27-NEXT: store i16 22, i16* [[IT53]], align 2 +// CHECK27-NEXT: [[TMP42:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 +// CHECK27-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 +// CHECK27-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 +// CHECK27-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV71]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] +// CHECK27: omp.inner.for.cond73: +// CHECK27-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] +// CHECK27-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] +// CHECK27: omp.inner.for.body75: +// CHECK27-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 +// CHECK27-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] +// CHECK27-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 +// CHECK27-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP47:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 +// CHECK27-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP48:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double +// CHECK27-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 +// CHECK27-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float +// CHECK27-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 +// CHECK27-NEXT: [[TMP49:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double +// CHECK27-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 +// CHECK27-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float +// CHECK27-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 +// CHECK27-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP50:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK27-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP51]] +// CHECK27-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i32 3 +// CHECK27-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 +// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP53:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 +// CHECK27-NEXT: store i64 [[ADD93]], i64* [[X]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK27-NEXT: [[TMP54:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 +// CHECK27-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 +// CHECK27-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 +// CHECK27-NEXT: store i8 [[CONV96]], i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] +// CHECK27: omp.body.continue97: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] +// CHECK27: omp.inner.for.inc98: +// CHECK27-NEXT: [[TMP55:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 +// CHECK27-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK27: omp.inner.for.end100: +// CHECK27-NEXT: store i8 96, i8* [[IT72]], align 1 +// CHECK27-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) +// CHECK27-NEXT: ret i32 [[TMP56]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z3bari +// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK27-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK27-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: ret i32 [[TMP8]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK27-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK27-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK27-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK27-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19 +// CHECK27-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400 +// CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// CHECK27-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK27-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]] +// CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK27-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1 +// CHECK27-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] +// CHECK27-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 +// CHECK27-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 +// CHECK27-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32 +// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4 +// CHECK27-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]] +// CHECK27-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) +// CHECK27-NEXT: ret i32 [[ADD10]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK27-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: ret i32 [[TMP0]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK27-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK27-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 +// CHECK27-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK27-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK27-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22 +// CHECK27-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK27-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 +// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 +// CHECK27-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: ret i32 [[TMP8]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK28-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: ret i64 0 +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK28-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK28-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK28-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[K8:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 +// CHECK28-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[LIN27:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A28:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[IT53:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[IT72:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK28-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK28-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK28-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 +// CHECK28-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK28-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK28-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK28-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 +// CHECK28-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 +// CHECK28-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4 +// CHECK28-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8 +// CHECK28-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK28: omp.inner.for.cond9: +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7 +// CHECK28-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK28-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK28: omp.inner.for.body11: +// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK28-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] +// CHECK28-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7 +// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7 +// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK28-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 +// CHECK28-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 +// CHECK28-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] +// CHECK28-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7 +// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7 +// CHECK28-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK28-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK28: omp.body.continue16: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK28: omp.inner.for.inc17: +// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK28-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK28-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK28: omp.inner.for.end19: +// CHECK28-NEXT: store i32 1, i32* [[I7]], align 4 +// CHECK28-NEXT: [[TMP18:%.*]] = load i64, i64* [[K8]], align 8 +// CHECK28-NEXT: store i64 [[TMP18]], i64* [[K]], align 8 +// CHECK28-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 +// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 +// CHECK28-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 +// CHECK28-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV23]], align 8 +// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK28-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START24]], align 4 +// CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START25]], align 4 +// CHECK28-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK28-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// CHECK28: omp.inner.for.cond29: +// CHECK28-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] +// CHECK28-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// CHECK28: omp.inner.for.body31: +// CHECK28-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 +// CHECK28-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] +// CHECK28-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK28-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] +// CHECK28-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] +// CHECK28-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK28-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK28-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] +// CHECK28-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] +// CHECK28-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 +// CHECK28-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK28-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 +// CHECK28-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 +// CHECK28-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 +// CHECK28-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// CHECK28: omp.body.continue45: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// CHECK28: omp.inner.for.inc46: +// CHECK28-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 +// CHECK28-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK28: omp.inner.for.end48: +// CHECK28-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK28-NEXT: [[TMP33:%.*]] = load i32, i32* [[LIN27]], align 4 +// CHECK28-NEXT: store i32 [[TMP33]], i32* [[LIN]], align 4 +// CHECK28-NEXT: [[TMP34:%.*]] = load i32, i32* [[A28]], align 4 +// CHECK28-NEXT: store i32 [[TMP34]], i32* [[A]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 +// CHECK28-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 +// CHECK28-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 +// CHECK28-NEXT: store i32 [[TMP35]], i32* [[DOTOMP_IV52]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] +// CHECK28: omp.inner.for.cond54: +// CHECK28-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] +// CHECK28-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] +// CHECK28: omp.inner.for.body56: +// CHECK28-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 +// CHECK28-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] +// CHECK28-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 +// CHECK28-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !13 +// CHECK28-NEXT: [[TMP39:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 +// CHECK28-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[TMP40:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK28-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 +// CHECK28-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 +// CHECK28-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 +// CHECK28-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] +// CHECK28: omp.body.continue64: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] +// CHECK28: omp.inner.for.inc65: +// CHECK28-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 +// CHECK28-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK28: omp.inner.for.end67: +// CHECK28-NEXT: store i16 22, i16* [[IT53]], align 2 +// CHECK28-NEXT: [[TMP42:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 +// CHECK28-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 +// CHECK28-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 +// CHECK28-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV71]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] +// CHECK28: omp.inner.for.cond73: +// CHECK28-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] +// CHECK28-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] +// CHECK28: omp.inner.for.body75: +// CHECK28-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 +// CHECK28-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] +// CHECK28-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 +// CHECK28-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP47:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 +// CHECK28-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP48:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double +// CHECK28-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 +// CHECK28-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float +// CHECK28-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 +// CHECK28-NEXT: [[TMP49:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double +// CHECK28-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 +// CHECK28-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float +// CHECK28-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 +// CHECK28-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP50:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK28-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP51]] +// CHECK28-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i32 3 +// CHECK28-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 +// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP53:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 +// CHECK28-NEXT: store i64 [[ADD93]], i64* [[X]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK28-NEXT: [[TMP54:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 +// CHECK28-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 +// CHECK28-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 +// CHECK28-NEXT: store i8 [[CONV96]], i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] +// CHECK28: omp.body.continue97: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] +// CHECK28: omp.inner.for.inc98: +// CHECK28-NEXT: [[TMP55:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 +// CHECK28-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK28: omp.inner.for.end100: +// CHECK28-NEXT: store i8 96, i8* [[IT72]], align 1 +// CHECK28-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) +// CHECK28-NEXT: ret i32 [[TMP56]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z3bari +// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK28-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK28-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: ret i32 [[TMP8]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK28-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK28-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK28-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK28-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19 +// CHECK28-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400 +// CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// CHECK28-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK28-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]] +// CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK28-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1 +// CHECK28-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] +// CHECK28-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 +// CHECK28-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 +// CHECK28-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32 +// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4 +// CHECK28-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]] +// CHECK28-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) +// CHECK28-NEXT: ret i32 [[ADD10]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK28-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: ret i32 [[TMP0]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK28-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK28-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 +// CHECK28-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK28-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK28-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22 +// CHECK28-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK28-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 +// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 +// CHECK28-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: ret i32 [[TMP8]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK29-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: ret i64 0 +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[K8:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[LIN27:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A28:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 +// CHECK29-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[IT53:%.*]] = alloca i16, align 2 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[IT72:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 +// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 +// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK29-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK29-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK29-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 +// CHECK29-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 +// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 +// CHECK29-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4 +// CHECK29-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8 +// CHECK29-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK29: omp.inner.for.cond9: +// CHECK29-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6 +// CHECK29-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK29-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK29: omp.inner.for.body11: +// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK29-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] +// CHECK29-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6 +// CHECK29-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6 +// CHECK29-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK29-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 +// CHECK29-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 +// CHECK29-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] +// CHECK29-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6 +// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6 +// CHECK29-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK29-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK29: omp.body.continue16: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK29: omp.inner.for.inc17: +// CHECK29-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK29-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK29-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK29: omp.inner.for.end19: +// CHECK29-NEXT: store i32 1, i32* [[I7]], align 4 +// CHECK29-NEXT: [[TMP20:%.*]] = load i64, i64* [[K8]], align 8 +// CHECK29-NEXT: store i64 [[TMP20]], i64* [[K]], align 8 +// CHECK29-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK29-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 +// CHECK29-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 +// CHECK29-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 +// CHECK29-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV23]], align 8 +// CHECK29-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK29-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START24]], align 4 +// CHECK29-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START25]], align 4 +// CHECK29-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK29-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// CHECK29: omp.inner.for.cond29: +// CHECK29-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] +// CHECK29-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// CHECK29: omp.inner.for.body31: +// CHECK29-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 +// CHECK29-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] +// CHECK29-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !9 +// CHECK29-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK29-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] +// CHECK29-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] +// CHECK29-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK29-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !9 +// CHECK29-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9 +// CHECK29-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 +// CHECK29-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] +// CHECK29-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] +// CHECK29-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 +// CHECK29-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !9 +// CHECK29-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK29-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 +// CHECK29-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 +// CHECK29-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 +// CHECK29-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// CHECK29: omp.body.continue45: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// CHECK29: omp.inner.for.inc46: +// CHECK29-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 +// CHECK29-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK29: omp.inner.for.end48: +// CHECK29-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK29-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN27]], align 4 +// CHECK29-NEXT: store i32 [[TMP35]], i32* [[LIN]], align 4 +// CHECK29-NEXT: [[TMP36:%.*]] = load i32, i32* [[A28]], align 4 +// CHECK29-NEXT: store i32 [[TMP36]], i32* [[A]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 +// CHECK29-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 +// CHECK29-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 +// CHECK29-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV52]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] +// CHECK29: omp.inner.for.cond54: +// CHECK29-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK29-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !12 +// CHECK29-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] +// CHECK29-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] +// CHECK29: omp.inner.for.body56: +// CHECK29-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK29-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 +// CHECK29-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] +// CHECK29-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 +// CHECK29-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !12 +// CHECK29-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12 +// CHECK29-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 +// CHECK29-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !12 +// CHECK29-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK29-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 +// CHECK29-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 +// CHECK29-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 +// CHECK29-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] +// CHECK29: omp.body.continue64: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] +// CHECK29: omp.inner.for.inc65: +// CHECK29-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK29-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 +// CHECK29-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK29: omp.inner.for.end67: +// CHECK29-NEXT: store i16 22, i16* [[IT53]], align 2 +// CHECK29-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 +// CHECK29-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 +// CHECK29-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 +// CHECK29-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV71]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] +// CHECK29: omp.inner.for.cond73: +// CHECK29-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] +// CHECK29-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] +// CHECK29: omp.inner.for.body75: +// CHECK29-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 +// CHECK29-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] +// CHECK29-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 +// CHECK29-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !15 +// CHECK29-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 +// CHECK29-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// CHECK29-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double +// CHECK29-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 +// CHECK29-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float +// CHECK29-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 +// CHECK29-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double +// CHECK29-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 +// CHECK29-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float +// CHECK29-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 +// CHECK29-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i64 0, i64 2 +// CHECK29-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 +// CHECK29-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 +// CHECK29-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 +// CHECK29-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] +// CHECK29-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP53]] +// CHECK29-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i64 3 +// CHECK29-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 +// CHECK29-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 +// CHECK29-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 +// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK29-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15 +// CHECK29-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 +// CHECK29-NEXT: store i64 [[ADD93]], i64* [[X]], align 8, !llvm.access.group !15 +// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK29-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK29-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 +// CHECK29-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 +// CHECK29-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 +// CHECK29-NEXT: store i8 [[CONV96]], i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] +// CHECK29: omp.body.continue97: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] +// CHECK29: omp.inner.for.inc98: +// CHECK29-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 +// CHECK29-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK29: omp.inner.for.end100: +// CHECK29-NEXT: store i8 96, i8* [[IT72]], align 1 +// CHECK29-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP59]]) +// CHECK29-NEXT: ret i32 [[TMP58]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z3bari +// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: ret i32 [[TMP8]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK29-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 +// CHECK29-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK29-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK29-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK29-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK29-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK29-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK29-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK29: omp_if.then: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK29-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 +// CHECK29-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]] +// CHECK29-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK29-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400 +// CHECK29-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK29-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 +// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18 +// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double +// CHECK29-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK29-NEXT: store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18 +// CHECK29-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK29-NEXT: [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18 +// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 +// CHECK29-NEXT: store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18 +// CHECK29-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK29-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] +// CHECK29-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK29-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK29-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1 +// CHECK29-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK29: omp_if.else: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] +// CHECK29: omp.inner.for.cond8: +// CHECK29-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK29-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK29-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]] +// CHECK29-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] +// CHECK29: omp.inner.for.body10: +// CHECK29-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK29-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400 +// CHECK29-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] +// CHECK29-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8 +// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4 +// CHECK29-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double +// CHECK29-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 +// CHECK29-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK29-NEXT: store double [[ADD14]], double* [[A15]], align 8 +// CHECK29-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK29-NEXT: [[TMP19:%.*]] = load double, double* [[A16]], align 8 +// CHECK29-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00 +// CHECK29-NEXT: store double [[INC17]], double* [[A16]], align 8 +// CHECK29-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 +// CHECK29-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK29-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]] +// CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1 +// CHECK29-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] +// CHECK29: omp.body.continue21: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] +// CHECK29: omp.inner.for.inc22: +// CHECK29-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK29-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1 +// CHECK29-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK29: omp.inner.for.end24: +// CHECK29-NEXT: br label [[OMP_IF_END]] +// CHECK29: omp_if.end: +// CHECK29-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK29-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK29-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]] +// CHECK29-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1 +// CHECK29-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2 +// CHECK29-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32 +// CHECK29-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4 +// CHECK29-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]] +// CHECK29-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// CHECK29-NEXT: ret i32 [[ADD28]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: ret i32 [[TMP0]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK29-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK29-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK29-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK29-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 +// CHECK29-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24 +// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] +// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 +// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK29-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24 +// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK29-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK29-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK29-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK29-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 +// CHECK29-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 +// CHECK29-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: ret i32 [[TMP8]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK30-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: ret i64 0 +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[K8:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[LIN27:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A28:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 +// CHECK30-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[IT53:%.*]] = alloca i16, align 2 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[IT72:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 +// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 +// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK30-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK30-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK30-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 +// CHECK30-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 +// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 +// CHECK30-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4 +// CHECK30-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8 +// CHECK30-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK30: omp.inner.for.cond9: +// CHECK30-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6 +// CHECK30-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK30-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK30: omp.inner.for.body11: +// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK30-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] +// CHECK30-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6 +// CHECK30-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6 +// CHECK30-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK30-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 +// CHECK30-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 +// CHECK30-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] +// CHECK30-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6 +// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6 +// CHECK30-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK30-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK30: omp.body.continue16: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK30: omp.inner.for.inc17: +// CHECK30-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK30-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK30-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK30: omp.inner.for.end19: +// CHECK30-NEXT: store i32 1, i32* [[I7]], align 4 +// CHECK30-NEXT: [[TMP20:%.*]] = load i64, i64* [[K8]], align 8 +// CHECK30-NEXT: store i64 [[TMP20]], i64* [[K]], align 8 +// CHECK30-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK30-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 +// CHECK30-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 +// CHECK30-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 +// CHECK30-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV23]], align 8 +// CHECK30-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK30-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START24]], align 4 +// CHECK30-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START25]], align 4 +// CHECK30-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK30-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// CHECK30: omp.inner.for.cond29: +// CHECK30-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] +// CHECK30-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// CHECK30: omp.inner.for.body31: +// CHECK30-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 +// CHECK30-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] +// CHECK30-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !9 +// CHECK30-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK30-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] +// CHECK30-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] +// CHECK30-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK30-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !9 +// CHECK30-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9 +// CHECK30-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 +// CHECK30-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] +// CHECK30-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] +// CHECK30-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 +// CHECK30-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !9 +// CHECK30-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK30-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 +// CHECK30-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 +// CHECK30-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 +// CHECK30-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// CHECK30: omp.body.continue45: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// CHECK30: omp.inner.for.inc46: +// CHECK30-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 +// CHECK30-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK30: omp.inner.for.end48: +// CHECK30-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK30-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN27]], align 4 +// CHECK30-NEXT: store i32 [[TMP35]], i32* [[LIN]], align 4 +// CHECK30-NEXT: [[TMP36:%.*]] = load i32, i32* [[A28]], align 4 +// CHECK30-NEXT: store i32 [[TMP36]], i32* [[A]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 +// CHECK30-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 +// CHECK30-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 +// CHECK30-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV52]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] +// CHECK30: omp.inner.for.cond54: +// CHECK30-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK30-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !12 +// CHECK30-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] +// CHECK30-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] +// CHECK30: omp.inner.for.body56: +// CHECK30-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK30-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 +// CHECK30-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] +// CHECK30-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 +// CHECK30-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !12 +// CHECK30-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12 +// CHECK30-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 +// CHECK30-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !12 +// CHECK30-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK30-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 +// CHECK30-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 +// CHECK30-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 +// CHECK30-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] +// CHECK30: omp.body.continue64: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] +// CHECK30: omp.inner.for.inc65: +// CHECK30-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK30-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 +// CHECK30-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK30: omp.inner.for.end67: +// CHECK30-NEXT: store i16 22, i16* [[IT53]], align 2 +// CHECK30-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 +// CHECK30-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 +// CHECK30-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 +// CHECK30-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV71]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] +// CHECK30: omp.inner.for.cond73: +// CHECK30-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] +// CHECK30-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] +// CHECK30: omp.inner.for.body75: +// CHECK30-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 +// CHECK30-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] +// CHECK30-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 +// CHECK30-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !15 +// CHECK30-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 +// CHECK30-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// CHECK30-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double +// CHECK30-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 +// CHECK30-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float +// CHECK30-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 +// CHECK30-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double +// CHECK30-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 +// CHECK30-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float +// CHECK30-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 +// CHECK30-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i64 0, i64 2 +// CHECK30-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 +// CHECK30-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 +// CHECK30-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 +// CHECK30-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] +// CHECK30-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP53]] +// CHECK30-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i64 3 +// CHECK30-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 +// CHECK30-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 +// CHECK30-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 +// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK30-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15 +// CHECK30-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 +// CHECK30-NEXT: store i64 [[ADD93]], i64* [[X]], align 8, !llvm.access.group !15 +// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK30-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK30-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 +// CHECK30-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 +// CHECK30-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 +// CHECK30-NEXT: store i8 [[CONV96]], i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] +// CHECK30: omp.body.continue97: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] +// CHECK30: omp.inner.for.inc98: +// CHECK30-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 +// CHECK30-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK30: omp.inner.for.end100: +// CHECK30-NEXT: store i8 96, i8* [[IT72]], align 1 +// CHECK30-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP59]]) +// CHECK30-NEXT: ret i32 [[TMP58]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z3bari +// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: ret i32 [[TMP8]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK30-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 +// CHECK30-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK30-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK30-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK30-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK30-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 +// CHECK30-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK30-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK30: omp_if.then: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK30-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 +// CHECK30-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]] +// CHECK30-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK30-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400 +// CHECK30-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK30-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 +// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18 +// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double +// CHECK30-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK30-NEXT: store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18 +// CHECK30-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK30-NEXT: [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18 +// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 +// CHECK30-NEXT: store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18 +// CHECK30-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK30-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] +// CHECK30-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK30-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK30-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1 +// CHECK30-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK30: omp_if.else: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] +// CHECK30: omp.inner.for.cond8: +// CHECK30-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK30-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK30-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]] +// CHECK30-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] +// CHECK30: omp.inner.for.body10: +// CHECK30-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK30-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400 +// CHECK30-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] +// CHECK30-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8 +// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4 +// CHECK30-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double +// CHECK30-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 +// CHECK30-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK30-NEXT: store double [[ADD14]], double* [[A15]], align 8 +// CHECK30-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK30-NEXT: [[TMP19:%.*]] = load double, double* [[A16]], align 8 +// CHECK30-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00 +// CHECK30-NEXT: store double [[INC17]], double* [[A16]], align 8 +// CHECK30-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 +// CHECK30-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK30-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]] +// CHECK30-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1 +// CHECK30-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] +// CHECK30: omp.body.continue21: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] +// CHECK30: omp.inner.for.inc22: +// CHECK30-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK30-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1 +// CHECK30-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK30: omp.inner.for.end24: +// CHECK30-NEXT: br label [[OMP_IF_END]] +// CHECK30: omp_if.end: +// CHECK30-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK30-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK30-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]] +// CHECK30-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1 +// CHECK30-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2 +// CHECK30-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32 +// CHECK30-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4 +// CHECK30-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]] +// CHECK30-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// CHECK30-NEXT: ret i32 [[ADD28]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: ret i32 [[TMP0]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK30-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK30-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK30-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK30-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 +// CHECK30-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24 +// CHECK30-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] +// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 +// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK30-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24 +// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK30-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK30-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK30-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK30-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 +// CHECK30-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 +// CHECK30-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: ret i32 [[TMP8]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK31-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: ret i64 0 +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[K8:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 +// CHECK31-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[LIN27:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A28:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 +// CHECK31-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[IT53:%.*]] = alloca i16, align 2 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[IT72:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 +// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 +// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK31-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK31-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK31-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 +// CHECK31-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 +// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 +// CHECK31-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4 +// CHECK31-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8 +// CHECK31-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK31: omp.inner.for.cond9: +// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK31-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7 +// CHECK31-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK31-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK31: omp.inner.for.body11: +// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK31-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] +// CHECK31-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7 +// CHECK31-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7 +// CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK31-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 +// CHECK31-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 +// CHECK31-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] +// CHECK31-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7 +// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7 +// CHECK31-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK31-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK31: omp.body.continue16: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK31: omp.inner.for.inc17: +// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK31-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK31-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK31: omp.inner.for.end19: +// CHECK31-NEXT: store i32 1, i32* [[I7]], align 4 +// CHECK31-NEXT: [[TMP18:%.*]] = load i64, i64* [[K8]], align 8 +// CHECK31-NEXT: store i64 [[TMP18]], i64* [[K]], align 8 +// CHECK31-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK31-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 +// CHECK31-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 +// CHECK31-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 +// CHECK31-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV23]], align 8 +// CHECK31-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK31-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START24]], align 4 +// CHECK31-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START25]], align 4 +// CHECK31-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK31-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// CHECK31: omp.inner.for.cond29: +// CHECK31-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] +// CHECK31-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// CHECK31: omp.inner.for.body31: +// CHECK31-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 +// CHECK31-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] +// CHECK31-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !10 +// CHECK31-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK31-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] +// CHECK31-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] +// CHECK31-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK31-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !10 +// CHECK31-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10 +// CHECK31-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK31-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] +// CHECK31-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] +// CHECK31-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 +// CHECK31-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !10 +// CHECK31-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK31-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 +// CHECK31-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 +// CHECK31-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 +// CHECK31-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// CHECK31: omp.body.continue45: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// CHECK31: omp.inner.for.inc46: +// CHECK31-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 +// CHECK31-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK31: omp.inner.for.end48: +// CHECK31-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK31-NEXT: [[TMP33:%.*]] = load i32, i32* [[LIN27]], align 4 +// CHECK31-NEXT: store i32 [[TMP33]], i32* [[LIN]], align 4 +// CHECK31-NEXT: [[TMP34:%.*]] = load i32, i32* [[A28]], align 4 +// CHECK31-NEXT: store i32 [[TMP34]], i32* [[A]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 +// CHECK31-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 +// CHECK31-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 +// CHECK31-NEXT: store i32 [[TMP35]], i32* [[DOTOMP_IV52]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] +// CHECK31: omp.inner.for.cond54: +// CHECK31-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK31-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !13 +// CHECK31-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] +// CHECK31-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] +// CHECK31: omp.inner.for.body56: +// CHECK31-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK31-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 +// CHECK31-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] +// CHECK31-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 +// CHECK31-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !13 +// CHECK31-NEXT: [[TMP39:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 +// CHECK31-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 +// CHECK31-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !13 +// CHECK31-NEXT: [[TMP40:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK31-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 +// CHECK31-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 +// CHECK31-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 +// CHECK31-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] +// CHECK31: omp.body.continue64: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] +// CHECK31: omp.inner.for.inc65: +// CHECK31-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK31-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 +// CHECK31-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK31: omp.inner.for.end67: +// CHECK31-NEXT: store i16 22, i16* [[IT53]], align 2 +// CHECK31-NEXT: [[TMP42:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 +// CHECK31-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 +// CHECK31-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 +// CHECK31-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV71]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] +// CHECK31: omp.inner.for.cond73: +// CHECK31-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] +// CHECK31-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] +// CHECK31: omp.inner.for.body75: +// CHECK31-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 +// CHECK31-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] +// CHECK31-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 +// CHECK31-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !16 +// CHECK31-NEXT: [[TMP47:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 +// CHECK31-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK31-NEXT: [[TMP48:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double +// CHECK31-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 +// CHECK31-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float +// CHECK31-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 +// CHECK31-NEXT: [[TMP49:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double +// CHECK31-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 +// CHECK31-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float +// CHECK31-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 +// CHECK31-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i32 0, i32 2 +// CHECK31-NEXT: [[TMP50:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 +// CHECK31-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 +// CHECK31-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 +// CHECK31-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK31-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP51]] +// CHECK31-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i32 3 +// CHECK31-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 +// CHECK31-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 +// CHECK31-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 +// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK31-NEXT: [[TMP53:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 +// CHECK31-NEXT: store i64 [[ADD93]], i64* [[X]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK31-NEXT: [[TMP54:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 +// CHECK31-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 +// CHECK31-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 +// CHECK31-NEXT: store i8 [[CONV96]], i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] +// CHECK31: omp.body.continue97: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] +// CHECK31: omp.inner.for.inc98: +// CHECK31-NEXT: [[TMP55:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 +// CHECK31-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK31: omp.inner.for.end100: +// CHECK31-NEXT: store i8 96, i8* [[IT72]], align 1 +// CHECK31-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) +// CHECK31-NEXT: ret i32 [[TMP56]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z3bari +// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: ret i32 [[TMP8]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK31-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 +// CHECK31-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK31-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK31-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK31-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK31-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK31-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK31-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK31: omp_if.then: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK31-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19 +// CHECK31-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK31-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK31-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK31-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK31-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19 +// CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 +// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double +// CHECK31-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK31-NEXT: store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19 +// CHECK31-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK31-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19 +// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK31-NEXT: store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19 +// CHECK31-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK31-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] +// CHECK31-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK31-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK31-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1 +// CHECK31-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK31: omp_if.else: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] +// CHECK31: omp.inner.for.cond8: +// CHECK31-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK31-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK31-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]] +// CHECK31-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] +// CHECK31: omp.inner.for.body10: +// CHECK31-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK31-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400 +// CHECK31-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] +// CHECK31-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8 +// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 +// CHECK31-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double +// CHECK31-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 +// CHECK31-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK31-NEXT: store double [[ADD14]], double* [[A15]], align 4 +// CHECK31-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK31-NEXT: [[TMP18:%.*]] = load double, double* [[A16]], align 4 +// CHECK31-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00 +// CHECK31-NEXT: store double [[INC17]], double* [[A16]], align 4 +// CHECK31-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 +// CHECK31-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK31-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]] +// CHECK31-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1 +// CHECK31-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] +// CHECK31: omp.body.continue21: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] +// CHECK31: omp.inner.for.inc22: +// CHECK31-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK31-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1 +// CHECK31-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK31: omp.inner.for.end24: +// CHECK31-NEXT: br label [[OMP_IF_END]] +// CHECK31: omp_if.end: +// CHECK31-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK31-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK31-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]] +// CHECK31-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1 +// CHECK31-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2 +// CHECK31-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32 +// CHECK31-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4 +// CHECK31-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]] +// CHECK31-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) +// CHECK31-NEXT: ret i32 [[ADD28]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: ret i32 [[TMP0]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK31-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK31-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK31-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK31-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 +// CHECK31-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25 +// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] +// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 +// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK31-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25 +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK31-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK31-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK31-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK31-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 +// CHECK31-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 +// CHECK31-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: ret i32 [[TMP8]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z7get_valv +// CHECK32-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: ret i64 0 +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[K:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[K8:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 +// CHECK32-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[LIN27:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A28:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 +// CHECK32-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[IT53:%.*]] = alloca i16, align 2 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[IT72:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 +// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 +// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] +// CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK32-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: store i32 33, i32* [[I]], align 4 +// CHECK32-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK32-NEXT: store i64 [[CALL]], i64* [[K]], align 8 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 +// CHECK32-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 +// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 +// CHECK32-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4 +// CHECK32-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8 +// CHECK32-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK32: omp.inner.for.cond9: +// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK32-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7 +// CHECK32-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] +// CHECK32-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK32: omp.inner.for.body11: +// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK32-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] +// CHECK32-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7 +// CHECK32-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7 +// CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK32-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 +// CHECK32-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 +// CHECK32-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] +// CHECK32-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7 +// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7 +// CHECK32-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK32-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK32: omp.body.continue16: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK32: omp.inner.for.inc17: +// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK32-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK32-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK32: omp.inner.for.end19: +// CHECK32-NEXT: store i32 1, i32* [[I7]], align 4 +// CHECK32-NEXT: [[TMP18:%.*]] = load i64, i64* [[K8]], align 8 +// CHECK32-NEXT: store i64 [[TMP18]], i64* [[K]], align 8 +// CHECK32-NEXT: store i32 12, i32* [[LIN]], align 4 +// CHECK32-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 +// CHECK32-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 +// CHECK32-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 +// CHECK32-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV23]], align 8 +// CHECK32-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4 +// CHECK32-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START24]], align 4 +// CHECK32-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START25]], align 4 +// CHECK32-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK32-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// CHECK32: omp.inner.for.cond29: +// CHECK32-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] +// CHECK32-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// CHECK32: omp.inner.for.body31: +// CHECK32-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 +// CHECK32-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] +// CHECK32-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !10 +// CHECK32-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK32-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] +// CHECK32-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] +// CHECK32-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 +// CHECK32-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !10 +// CHECK32-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10 +// CHECK32-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK32-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] +// CHECK32-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] +// CHECK32-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 +// CHECK32-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !10 +// CHECK32-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK32-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 +// CHECK32-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 +// CHECK32-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 +// CHECK32-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// CHECK32: omp.body.continue45: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// CHECK32: omp.inner.for.inc46: +// CHECK32-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 +// CHECK32-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK32: omp.inner.for.end48: +// CHECK32-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK32-NEXT: [[TMP33:%.*]] = load i32, i32* [[LIN27]], align 4 +// CHECK32-NEXT: store i32 [[TMP33]], i32* [[LIN]], align 4 +// CHECK32-NEXT: [[TMP34:%.*]] = load i32, i32* [[A28]], align 4 +// CHECK32-NEXT: store i32 [[TMP34]], i32* [[A]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 +// CHECK32-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 +// CHECK32-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 +// CHECK32-NEXT: store i32 [[TMP35]], i32* [[DOTOMP_IV52]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] +// CHECK32: omp.inner.for.cond54: +// CHECK32-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK32-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !13 +// CHECK32-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] +// CHECK32-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] +// CHECK32: omp.inner.for.body56: +// CHECK32-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK32-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 +// CHECK32-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] +// CHECK32-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 +// CHECK32-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !13 +// CHECK32-NEXT: [[TMP39:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 +// CHECK32-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 +// CHECK32-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !13 +// CHECK32-NEXT: [[TMP40:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK32-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 +// CHECK32-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 +// CHECK32-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 +// CHECK32-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] +// CHECK32: omp.body.continue64: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] +// CHECK32: omp.inner.for.inc65: +// CHECK32-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK32-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 +// CHECK32-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK32: omp.inner.for.end67: +// CHECK32-NEXT: store i16 22, i16* [[IT53]], align 2 +// CHECK32-NEXT: [[TMP42:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 +// CHECK32-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 +// CHECK32-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 +// CHECK32-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV71]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] +// CHECK32: omp.inner.for.cond73: +// CHECK32-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] +// CHECK32-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] +// CHECK32: omp.inner.for.body75: +// CHECK32-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 +// CHECK32-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] +// CHECK32-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 +// CHECK32-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !16 +// CHECK32-NEXT: [[TMP47:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 +// CHECK32-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK32-NEXT: [[TMP48:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double +// CHECK32-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 +// CHECK32-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float +// CHECK32-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 +// CHECK32-NEXT: [[TMP49:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double +// CHECK32-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 +// CHECK32-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float +// CHECK32-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 +// CHECK32-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i32 0, i32 2 +// CHECK32-NEXT: [[TMP50:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 +// CHECK32-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 +// CHECK32-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 +// CHECK32-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK32-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP51]] +// CHECK32-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i32 3 +// CHECK32-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 +// CHECK32-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 +// CHECK32-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 +// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK32-NEXT: [[TMP53:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 +// CHECK32-NEXT: store i64 [[ADD93]], i64* [[X]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK32-NEXT: [[TMP54:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 +// CHECK32-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 +// CHECK32-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 +// CHECK32-NEXT: store i8 [[CONV96]], i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] +// CHECK32: omp.body.continue97: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] +// CHECK32: omp.inner.for.inc98: +// CHECK32-NEXT: [[TMP55:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 +// CHECK32-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK32: omp.inner.for.end100: +// CHECK32-NEXT: store i8 96, i8* [[IT72]], align 1 +// CHECK32-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) +// CHECK32-NEXT: ret i32 [[TMP56]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z3bari +// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: ret i32 [[TMP8]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK32-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[IT:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 +// CHECK32-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK32-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK32-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 +// CHECK32-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK32-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 +// CHECK32-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK32-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK32: omp_if.then: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK32-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19 +// CHECK32-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] +// CHECK32-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK32-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 +// CHECK32-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] +// CHECK32-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19 +// CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 +// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double +// CHECK32-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK32-NEXT: store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19 +// CHECK32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19 +// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK32-NEXT: store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19 +// CHECK32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] +// CHECK32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK32-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1 +// CHECK32-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK32: omp_if.else: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] +// CHECK32: omp.inner.for.cond8: +// CHECK32-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK32-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 +// CHECK32-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]] +// CHECK32-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] +// CHECK32: omp.inner.for.body10: +// CHECK32-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK32-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400 +// CHECK32-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] +// CHECK32-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8 +// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 +// CHECK32-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double +// CHECK32-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 +// CHECK32-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK32-NEXT: store double [[ADD14]], double* [[A15]], align 4 +// CHECK32-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK32-NEXT: [[TMP18:%.*]] = load double, double* [[A16]], align 4 +// CHECK32-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00 +// CHECK32-NEXT: store double [[INC17]], double* [[A16]], align 4 +// CHECK32-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 +// CHECK32-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK32-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]] +// CHECK32-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1 +// CHECK32-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] +// CHECK32: omp.body.continue21: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] +// CHECK32: omp.inner.for.inc22: +// CHECK32-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK32-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1 +// CHECK32-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK32: omp.inner.for.end24: +// CHECK32-NEXT: br label [[OMP_IF_END]] +// CHECK32: omp_if.end: +// CHECK32-NEXT: store i64 400, i64* [[IT]], align 8 +// CHECK32-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK32-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]] +// CHECK32-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1 +// CHECK32-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2 +// CHECK32-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32 +// CHECK32-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4 +// CHECK32-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]] +// CHECK32-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) +// CHECK32-NEXT: ret i32 [[ADD28]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: ret i32 [[TMP0]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i64, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: [[I:%.*]] = alloca i64, align 8 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK32-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 +// CHECK32-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 +// CHECK32-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// CHECK32-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 +// CHECK32-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25 +// CHECK32-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] +// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 +// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] +// CHECK32-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25 +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK32-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK32-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK32-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK32-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 +// CHECK32-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 +// CHECK32-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: store i64 11, i64* [[I]], align 8 +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: ret i32 [[TMP8]] +// diff --git a/clang/test/OpenMP/target_parallel_if_codegen.cpp b/clang/test/OpenMP/target_parallel_if_codegen.cpp --- a/clang/test/OpenMP/target_parallel_if_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_if_codegen.cpp @@ -1487,7 +1487,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -1513,7 +1513,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1530,7 +1530,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1540,7 +1540,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1577,7 +1577,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1598,7 +1598,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -1627,7 +1627,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1642,7 +1642,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK9-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -1664,7 +1664,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1680,7 +1680,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1703,7 +1703,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1723,8 +1723,245 @@ // CHECK9-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK10: omp_if.then: +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK10: omp_if.else: +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_IF_END]] +// CHECK10: omp_if.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -1750,7 +1987,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1767,7 +2004,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1777,7 +2014,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1812,7 +2049,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1832,7 +2069,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -1861,7 +2098,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1876,7 +2113,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK11-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -1896,7 +2133,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1911,7 +2148,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1932,7 +2169,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1950,3 +2187,3313 @@ // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: ret void // +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK12-SAME: () #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK12: omp_if.then: +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK12: omp_if.else: +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_IF_END]] +// CHECK12: omp_if.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3bari +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP6]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 +// CHECK17-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK17-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK17-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK17-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** +// CHECK17-NEXT: store double* [[A]], double** [[TMP8]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK17-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 +// CHECK17-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 +// CHECK17-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 +// CHECK17-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK17-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK17-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 +// CHECK17-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* +// CHECK17-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 +// CHECK17-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 +// CHECK17-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 +// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 +// CHECK17-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 +// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** +// CHECK17-NEXT: store double* [[A13]], double** [[TMP33]], align 8 +// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP34]], align 8 +// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* +// CHECK17-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 +// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* +// CHECK17-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 +// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK17-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 +// CHECK17-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) +// CHECK17-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 +// CHECK17-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] +// CHECK17: omp_offload.failed18: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT19]] +// CHECK17: omp_offload.cont19: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 +// CHECK17-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 +// CHECK17-NEXT: ret i32 [[CONV21]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 +// CHECK17-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK17-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK17-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK17-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK17-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK17-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP8]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK17-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK17-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) +// CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK17-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 +// CHECK17-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 +// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] +// CHECK17: omp_if.then5: +// CHECK17-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK17-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK17: omp_offload.failed6: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK17: omp_offload.cont7: +// CHECK17-NEXT: br label [[OMP_IF_END9:%.*]] +// CHECK17: omp_if.else8: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END9]] +// CHECK17: omp_if.end9: +// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK17-NEXT: ret i32 [[ADD]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) +// CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK17-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* +// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK17: omp_offload.failed7: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK17: omp_offload.cont8: +// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP29]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK17-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] +// CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK17-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] +// CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK17-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] +// CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK17-SAME: () #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK17-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] +// CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK17-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK17-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3bari +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP6]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 +// CHECK18-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK18-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK18-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK18-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** +// CHECK18-NEXT: store double* [[A]], double** [[TMP8]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 +// CHECK18-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR3:[0-9]+]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 +// CHECK18-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 +// CHECK18-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK18-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK18-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 +// CHECK18-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* +// CHECK18-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 +// CHECK18-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 +// CHECK18-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 +// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 +// CHECK18-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 +// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** +// CHECK18-NEXT: store double* [[A13]], double** [[TMP33]], align 8 +// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP34]], align 8 +// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* +// CHECK18-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 +// CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* +// CHECK18-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 +// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 +// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 +// CHECK18-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 +// CHECK18-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) +// CHECK18-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 +// CHECK18-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] +// CHECK18: omp_offload.failed18: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT19]] +// CHECK18: omp_offload.cont19: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 +// CHECK18-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 +// CHECK18-NEXT: ret i32 [[CONV21]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 +// CHECK18-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK18-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK18-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK18-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK18-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP8]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK18-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK18-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) +// CHECK18-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK18-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 +// CHECK18-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 +// CHECK18-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] +// CHECK18: omp_if.then5: +// CHECK18-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK18-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK18-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK18: omp_offload.failed6: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK18: omp_offload.cont7: +// CHECK18-NEXT: br label [[OMP_IF_END9:%.*]] +// CHECK18: omp_if.else8: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END9]] +// CHECK18: omp_if.end9: +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK18-NEXT: ret i32 [[ADD]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) +// CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK18-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* +// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK18: omp_offload.failed7: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK18: omp_offload.cont8: +// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP29]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK18-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] +// CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK18-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] +// CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK18-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] +// CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK18-SAME: () #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK18-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] +// CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK18-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK18-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3bari +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP6]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 +// CHECK19-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK19-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK19-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK19-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** +// CHECK19-NEXT: store double* [[A]], double** [[TMP8]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK19-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 +// CHECK19-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR3:[0-9]+]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 +// CHECK19-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 +// CHECK19-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK19-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK19-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 +// CHECK19-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* +// CHECK19-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 +// CHECK19-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 +// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 +// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 +// CHECK19-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 +// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** +// CHECK19-NEXT: store double* [[A12]], double** [[TMP33]], align 4 +// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* +// CHECK19-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 +// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK19-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 +// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK19-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 +// CHECK19-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) +// CHECK19-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 +// CHECK19-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK19: omp_offload.failed17: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK19: omp_offload.cont18: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 +// CHECK19-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 +// CHECK19-NEXT: ret i32 [[CONV20]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 +// CHECK19-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK19-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK19-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK19-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK19-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK19-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP8]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK19-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK19-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) +// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK19-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 +// CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 +// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] +// CHECK19: omp_if.then5: +// CHECK19-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK19-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK19: omp_offload.failed6: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK19: omp_offload.cont7: +// CHECK19-NEXT: br label [[OMP_IF_END9:%.*]] +// CHECK19: omp_if.else8: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END9]] +// CHECK19: omp_if.end9: +// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK19-NEXT: ret i32 [[ADD]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) +// CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK19-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK19: omp_offload.failed5: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK19: omp_offload.cont6: +// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP29]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK19-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] +// CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK19-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] +// CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK19-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] +// CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK19-SAME: () #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK19-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR3]] +// CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK19-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK19-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3bari +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP6]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 +// CHECK20-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK20-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK20-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK20-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** +// CHECK20-NEXT: store double* [[A]], double** [[TMP8]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 +// CHECK20-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR3:[0-9]+]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 +// CHECK20-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 +// CHECK20-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK20-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK20-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 +// CHECK20-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* +// CHECK20-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 +// CHECK20-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 +// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 +// CHECK20-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 +// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** +// CHECK20-NEXT: store double* [[A12]], double** [[TMP33]], align 4 +// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP34]], align 4 +// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* +// CHECK20-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 +// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* +// CHECK20-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 +// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 +// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 +// CHECK20-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 +// CHECK20-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) +// CHECK20-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 +// CHECK20-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// CHECK20: omp_offload.failed17: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// CHECK20: omp_offload.cont18: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 +// CHECK20-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 +// CHECK20-NEXT: ret i32 [[CONV20]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 +// CHECK20-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK20-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK20-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK20-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK20-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP8]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK20-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 +// CHECK20-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) +// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK20-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 +// CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 +// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] +// CHECK20: omp_if.then5: +// CHECK20-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK20-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK20: omp_offload.failed6: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK20: omp_offload.cont7: +// CHECK20-NEXT: br label [[OMP_IF_END9:%.*]] +// CHECK20: omp_if.else8: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END9]] +// CHECK20: omp_if.end9: +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK20-NEXT: ret i32 [[ADD]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) +// CHECK20-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK20-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* +// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) +// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] +// CHECK20: omp_offload.failed5: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT6]] +// CHECK20: omp_offload.cont6: +// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP29]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK20-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] +// CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK20-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] +// CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK20-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] +// CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK20-SAME: () #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK20-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR3]] +// CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK20-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK20-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK25-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK25: omp_if.then: +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK25: omp_if.else: +// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK25-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK25-NEXT: br label [[OMP_IF_END]] +// CHECK25: omp_if.end: +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK25-SAME: () #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK25: omp_if.then: +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK25-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK25: omp_if.else: +// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK25-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] +// CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK25-NEXT: br label [[OMP_IF_END]] +// CHECK25: omp_if.end: +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK25-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK25: omp_if.then: +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK25-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK25: omp_if.else: +// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK25-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] +// CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK25-NEXT: br label [[OMP_IF_END]] +// CHECK25: omp_if.end: +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK25-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK25-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] +// CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK26-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK26: omp_if.then: +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK26: omp_if.else: +// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK26-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK26-NEXT: br label [[OMP_IF_END]] +// CHECK26: omp_if.end: +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK26-SAME: () #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK26: omp_if.then: +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) +// CHECK26-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK26: omp_if.else: +// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK26-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] +// CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK26-NEXT: br label [[OMP_IF_END]] +// CHECK26: omp_if.end: +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK26-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK26: omp_if.then: +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK26-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK26: omp_if.else: +// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK26-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] +// CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK26-NEXT: br label [[OMP_IF_END]] +// CHECK26: omp_if.end: +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK26-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK26-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] +// CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK27-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK27: omp_if.then: +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK27: omp_if.else: +// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK27-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK27-NEXT: br label [[OMP_IF_END]] +// CHECK27: omp_if.end: +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK27-SAME: () #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK27: omp_if.then: +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK27-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK27: omp_if.else: +// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK27-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] +// CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK27-NEXT: br label [[OMP_IF_END]] +// CHECK27: omp_if.end: +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK27-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK27: omp_if.then: +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK27-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK27: omp_if.else: +// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK27-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] +// CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK27-NEXT: br label [[OMP_IF_END]] +// CHECK27: omp_if.end: +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK27-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK27-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] +// CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK28-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK28: omp_if.then: +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK28: omp_if.else: +// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK28-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] +// CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK28-NEXT: br label [[OMP_IF_END]] +// CHECK28: omp_if.end: +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK28-SAME: () #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK28: omp_if.then: +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) +// CHECK28-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK28: omp_if.else: +// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK28-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] +// CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK28-NEXT: br label [[OMP_IF_END]] +// CHECK28: omp_if.end: +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK28-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 +// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK28: omp_if.then: +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK28-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK28: omp_if.else: +// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK28-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] +// CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK28-NEXT: br label [[OMP_IF_END]] +// CHECK28: omp_if.end: +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 +// CHECK28-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK28-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] +// CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp --- a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp @@ -1318,7 +1318,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -1331,7 +1331,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1341,7 +1341,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1354,7 +1354,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1364,7 +1364,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1388,7 +1388,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1409,7 +1409,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1421,7 +1421,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1445,7 +1445,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1455,7 +1455,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1485,7 +1485,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1505,8 +1505,196 @@ // CHECK9-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK10-SAME: () #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -1518,7 +1706,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1528,7 +1716,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1540,7 +1728,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1550,7 +1738,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1571,7 +1759,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1591,7 +1779,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1603,7 +1791,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1627,7 +1815,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1637,7 +1825,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1665,7 +1853,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1683,3 +1871,2716 @@ // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: ret void // +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK12-SAME: () #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3bari +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP6]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK17-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK17-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK17-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) +// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK17: omp_offload.failed7: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK17: omp_offload.cont8: +// CHECK17-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK17-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK17-NEXT: ret i32 [[CONV10]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) +// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK17: omp_offload.failed7: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK17: omp_offload.cont8: +// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK17-NEXT: ret i32 [[ADD9]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) +// CHECK17-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK17-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK17-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 +// CHECK17-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) +// CHECK17-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK17-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK17: omp_offload.failed3: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK17: omp_offload.cont4: +// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP30]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK17-SAME: () #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK17-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK17-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3bari +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP6]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK18-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK18-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR3:[0-9]+]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK18-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) +// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK18: omp_offload.failed7: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK18: omp_offload.cont8: +// CHECK18-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK18-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK18-NEXT: ret i32 [[CONV10]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP7]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) +// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK18-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK18: omp_offload.failed7: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK18: omp_offload.cont8: +// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK18-NEXT: ret i32 [[ADD9]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) +// CHECK18-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK18-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK18-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 +// CHECK18-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) +// CHECK18-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK18-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK18: omp_offload.failed3: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK18: omp_offload.cont4: +// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP30]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK18-SAME: () #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK18-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK18-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3bari +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP6]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK19-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK19-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR3:[0-9]+]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK19-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) +// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK19: omp_offload.failed6: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK19: omp_offload.cont7: +// CHECK19-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK19-NEXT: ret i32 [[CONV]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) +// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK19: omp_offload.failed6: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK19: omp_offload.cont7: +// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK19-NEXT: ret i32 [[ADD8]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) +// CHECK19-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK19-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK19-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 +// CHECK19-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) +// CHECK19-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK19-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK19: omp_offload.failed2: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK19: omp_offload.cont3: +// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP30]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK19-SAME: () #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK19-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK19-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3bari +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP6]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK20-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK20-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR3:[0-9]+]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK20-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) +// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK20: omp_offload.failed6: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK20: omp_offload.cont7: +// CHECK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK20-NEXT: ret i32 [[CONV]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) +// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) +// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK20: omp_offload.failed6: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK20: omp_offload.cont7: +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK20-NEXT: ret i32 [[ADD8]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) +// CHECK20-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK20-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK20-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 +// CHECK20-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) +// CHECK20-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK20-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK20: omp_offload.failed2: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK20: omp_offload.cont3: +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP30]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK20-SAME: () #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK20-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK20-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK25-SAME: () #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK26-SAME: () #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK27-SAME: () #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK28-SAME: () #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_private_codegen.cpp b/clang/test/OpenMP/target_private_codegen.cpp --- a/clang/test/OpenMP/target_private_codegen.cpp +++ b/clang/test/OpenMP/target_private_codegen.cpp @@ -85,7 +85,7 @@ } // make sure that private variables are generated in all cases and that we use those instances for operations inside the // target region - // TCHECK: define weak_odr void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i{{[0-9]+}} noundef [[VLA3:%.+]]) + // TCHECK: define weak_odr void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[VLA:%.+]], i{{[0-9]+}} [[VLA1:%.+]], i{{[0-9]+}} [[VLA3:%.+]]) // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[VLA_ADDR4:%.+]] = alloca i{{[0-9]+}}, @@ -207,7 +207,7 @@ return c[1][1] + (int)b; } - // TCHECK: define weak_odr void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]]) + // TCHECK: define weak_odr void @__omp_offloading_{{.+}}([[S1]]* [[TH:%.+]], i{{[0-9]+}} [[VLA:%.+]], i{{[0-9]+}} [[VLA1:%.+]]) // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*, // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}}, diff --git a/clang/test/OpenMP/target_reduction_codegen.cpp b/clang/test/OpenMP/target_reduction_codegen.cpp --- a/clang/test/OpenMP/target_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_reduction_codegen.cpp @@ -154,7 +154,7 @@ return c[1][1] + (int)b; } - // TCHECK: define weak_odr void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i32*{{.+}}, i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i16*{{.+}}) + // TCHECK: define weak_odr void @__omp_offloading_{{.+}}([[S1]]* [[TH:%.+]], i32*{{.+}}, i{{[0-9]+}} [[VLA:%.+]], i{{[0-9]+}} [[VLA1:%.+]], i16*{{.+}}) // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*, // TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}}*, // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, diff --git a/clang/test/OpenMP/target_teams_codegen.cpp b/clang/test/OpenMP/target_teams_codegen.cpp --- a/clang/test/OpenMP/target_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_codegen.cpp @@ -3372,7 +3372,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -3397,7 +3397,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3410,7 +3410,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -3425,7 +3425,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3443,7 +3443,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3466,7 +3466,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3490,7 +3490,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -3529,7 +3529,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3602,7 +3602,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -3617,7 +3617,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3636,7 +3636,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3649,7 +3649,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -3664,7 +3664,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3678,7 +3678,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3691,7 +3691,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK9-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 @@ -3701,7 +3701,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3715,7 +3715,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3749,7 +3749,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3788,7 +3788,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3815,7 +3815,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3854,7 +3854,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3880,7 +3880,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3910,8 +3910,547 @@ // CHECK9-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK10-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK10-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK10-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK10-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK10-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK10-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK10-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK10-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK10-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK10-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK10-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[F:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK10-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK10-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -3934,7 +4473,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3947,7 +4486,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -3962,7 +4501,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3980,7 +4519,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4001,7 +4540,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4024,7 +4563,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -4061,7 +4600,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4133,7 +4672,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -4146,7 +4685,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4163,7 +4702,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4175,7 +4714,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -4188,7 +4727,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4201,7 +4740,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4214,7 +4753,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK11-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 @@ -4224,7 +4763,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4238,7 +4777,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4270,7 +4809,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4308,7 +4847,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4333,7 +4872,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4371,7 +4910,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4395,7 +4934,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4423,3 +4962,8001 @@ // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: ret void // +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK12-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK12-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK12-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK12-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK12-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK12-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK12-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK12-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK12-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK12-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK12-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK12-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK12-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK12-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK12-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK12-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK12-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK12-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 +// CHECK17-NEXT: [[NN:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* +// CHECK17-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 +// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 +// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK17-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK17-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 +// CHECK17-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) +// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) +// CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) +// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 +// CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK17-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 +// CHECK17-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* +// CHECK17-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 +// CHECK17-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 +// CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 +// CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 +// CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP65]], align 8 +// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 +// CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK17-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 +// CHECK17-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK17-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* +// CHECK17-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 +// CHECK17-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 +// CHECK17-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 +// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 +// CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 +// CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 +// CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 +// CHECK17-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] +// CHECK17: omp_offload.failed19: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT20]] +// CHECK17: omp_offload.cont20: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* +// CHECK17-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 +// CHECK17-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 +// CHECK17-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 +// CHECK17-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] +// CHECK17: omp_if.then24: +// CHECK17-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK17-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK17-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 +// CHECK17-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) +// CHECK17-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* +// CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP97]], align 8 +// CHECK17-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* +// CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP99]], align 8 +// CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP100]], align 8 +// CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 +// CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 +// CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP105]], align 8 +// CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP107]], align 8 +// CHECK17-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP109]], align 8 +// CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP110]], align 8 +// CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** +// CHECK17-NEXT: store float* [[VLA]], float** [[TMP112]], align 8 +// CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** +// CHECK17-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 +// CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK17-NEXT: store i64 [[TMP92]], i64* [[TMP115]], align 8 +// CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 +// CHECK17-NEXT: store i8* null, i8** [[TMP116]], align 8 +// CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8 +// CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 +// CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 +// CHECK17-NEXT: store i8* null, i8** [[TMP121]], align 8 +// CHECK17-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 +// CHECK17-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64* +// CHECK17-NEXT: store i64 5, i64* [[TMP123]], align 8 +// CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 +// CHECK17-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* +// CHECK17-NEXT: store i64 5, i64* [[TMP125]], align 8 +// CHECK17-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 +// CHECK17-NEXT: store i8* null, i8** [[TMP126]], align 8 +// CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 +// CHECK17-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 +// CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 +// CHECK17-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP130]], align 8 +// CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 +// CHECK17-NEXT: store i8* null, i8** [[TMP131]], align 8 +// CHECK17-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 +// CHECK17-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** +// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP133]], align 8 +// CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 +// CHECK17-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** +// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP135]], align 8 +// CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK17-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 8 +// CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 +// CHECK17-NEXT: store i8* null, i8** [[TMP137]], align 8 +// CHECK17-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 +// CHECK17-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8 +// CHECK17-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 +// CHECK17-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8 +// CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 +// CHECK17-NEXT: store i8* null, i8** [[TMP142]], align 8 +// CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 +// CHECK17-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] +// CHECK17: omp_offload.failed28: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT29]] +// CHECK17: omp_offload.cont29: +// CHECK17-NEXT: br label [[OMP_IF_END31:%.*]] +// CHECK17: omp_if.else30: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END31]] +// CHECK17: omp_if.end31: +// CHECK17-NEXT: store i32 0, i32* [[NN]], align 4 +// CHECK17-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK17-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP148]], i32* [[CONV32]], align 4 +// CHECK17-NEXT: [[TMP149:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* +// CHECK17-NEXT: store i64 [[TMP149]], i64* [[TMP151]], align 8 +// CHECK17-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* +// CHECK17-NEXT: store i64 [[TMP149]], i64* [[TMP153]], align 8 +// CHECK17-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP154]], align 8 +// CHECK17-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 +// CHECK17-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] +// CHECK17: omp_offload.failed36: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP149]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT37]] +// CHECK17: omp_offload.cont37: +// CHECK17-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK17-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* +// CHECK17-NEXT: store i32 [[TMP159]], i32* [[CONV39]], align 4 +// CHECK17-NEXT: [[TMP160:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 +// CHECK17-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i64* +// CHECK17-NEXT: store i64 [[TMP160]], i64* [[TMP162]], align 8 +// CHECK17-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i64* +// CHECK17-NEXT: store i64 [[TMP160]], i64* [[TMP164]], align 8 +// CHECK17-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP165]], align 8 +// CHECK17-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 +// CHECK17-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] +// CHECK17: omp_offload.failed43: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP160]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT44]] +// CHECK17: omp_offload.cont44: +// CHECK17-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) +// CHECK17-NEXT: ret i32 [[TMP170]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 +// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 +// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 +// CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 +// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 +// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] +// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK17: omp_offload.failed.i: +// CHECK17-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 +// CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* +// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24 +// CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24 +// CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK17-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* +// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24 +// CHECK17-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24 +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK17: .omp_outlined..1.exit: +// CHECK17-NEXT: ret i32 0 +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 +// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK17-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK17-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK17-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK17-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK17-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK17-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK17-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK17-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z6bazzzziPi +// CHECK17-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK17-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK17-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..20 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[F:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3bari +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP8]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i64 40, i1 false) +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK17-NEXT: store double* [[A]], double** [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK17-NEXT: store i64 2, i64* [[TMP22]], align 8 +// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* +// CHECK17-NEXT: store i64 2, i64* [[TMP24]], align 8 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 +// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 +// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 +// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 +// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK17-NEXT: store i8* null, i8** [[TMP36]], align 8 +// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK17-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] +// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK17-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] +// CHECK17-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK17-NEXT: ret i32 [[ADD4]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP31]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP24]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..23 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK17-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK17-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK17-SAME: () #[[ATTR4]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK17-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 +// CHECK18-NEXT: [[NN:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* +// CHECK18-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 +// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 +// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK18-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK18-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK18-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 +// CHECK18-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) +// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) +// CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) +// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 +// CHECK18-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK18-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 +// CHECK18-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] +// CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* +// CHECK18-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 +// CHECK18-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 +// CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 +// CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 +// CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP65]], align 8 +// CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 +// CHECK18-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK18-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 +// CHECK18-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK18-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* +// CHECK18-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 +// CHECK18-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 +// CHECK18-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 +// CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 +// CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 +// CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 +// CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 +// CHECK18-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] +// CHECK18: omp_offload.failed19: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT20]] +// CHECK18: omp_offload.cont20: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* +// CHECK18-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 +// CHECK18-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 +// CHECK18-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 +// CHECK18-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] +// CHECK18: omp_if.then24: +// CHECK18-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK18-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK18-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 +// CHECK18-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) +// CHECK18-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* +// CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP97]], align 8 +// CHECK18-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* +// CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP99]], align 8 +// CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP100]], align 8 +// CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 +// CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 +// CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP105]], align 8 +// CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP107]], align 8 +// CHECK18-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP109]], align 8 +// CHECK18-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP110]], align 8 +// CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** +// CHECK18-NEXT: store float* [[VLA]], float** [[TMP112]], align 8 +// CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** +// CHECK18-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 +// CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK18-NEXT: store i64 [[TMP92]], i64* [[TMP115]], align 8 +// CHECK18-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 +// CHECK18-NEXT: store i8* null, i8** [[TMP116]], align 8 +// CHECK18-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8 +// CHECK18-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 +// CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 +// CHECK18-NEXT: store i8* null, i8** [[TMP121]], align 8 +// CHECK18-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 +// CHECK18-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64* +// CHECK18-NEXT: store i64 5, i64* [[TMP123]], align 8 +// CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 +// CHECK18-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* +// CHECK18-NEXT: store i64 5, i64* [[TMP125]], align 8 +// CHECK18-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 +// CHECK18-NEXT: store i8* null, i8** [[TMP126]], align 8 +// CHECK18-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 +// CHECK18-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 +// CHECK18-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 +// CHECK18-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP130]], align 8 +// CHECK18-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 +// CHECK18-NEXT: store i8* null, i8** [[TMP131]], align 8 +// CHECK18-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 +// CHECK18-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** +// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP133]], align 8 +// CHECK18-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 +// CHECK18-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** +// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP135]], align 8 +// CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK18-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 8 +// CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 +// CHECK18-NEXT: store i8* null, i8** [[TMP137]], align 8 +// CHECK18-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 +// CHECK18-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8 +// CHECK18-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 +// CHECK18-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8 +// CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 +// CHECK18-NEXT: store i8* null, i8** [[TMP142]], align 8 +// CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 +// CHECK18-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] +// CHECK18: omp_offload.failed28: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT29]] +// CHECK18: omp_offload.cont29: +// CHECK18-NEXT: br label [[OMP_IF_END31:%.*]] +// CHECK18: omp_if.else30: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END31]] +// CHECK18: omp_if.end31: +// CHECK18-NEXT: store i32 0, i32* [[NN]], align 4 +// CHECK18-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK18-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP148]], i32* [[CONV32]], align 4 +// CHECK18-NEXT: [[TMP149:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* +// CHECK18-NEXT: store i64 [[TMP149]], i64* [[TMP151]], align 8 +// CHECK18-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* +// CHECK18-NEXT: store i64 [[TMP149]], i64* [[TMP153]], align 8 +// CHECK18-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP154]], align 8 +// CHECK18-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 +// CHECK18-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] +// CHECK18: omp_offload.failed36: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP149]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT37]] +// CHECK18: omp_offload.cont37: +// CHECK18-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK18-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* +// CHECK18-NEXT: store i32 [[TMP159]], i32* [[CONV39]], align 4 +// CHECK18-NEXT: [[TMP160:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 +// CHECK18-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i64* +// CHECK18-NEXT: store i64 [[TMP160]], i64* [[TMP162]], align 8 +// CHECK18-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i64* +// CHECK18-NEXT: store i64 [[TMP160]], i64* [[TMP164]], align 8 +// CHECK18-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP165]], align 8 +// CHECK18-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 +// CHECK18-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] +// CHECK18: omp_offload.failed43: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP160]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT44]] +// CHECK18: omp_offload.cont44: +// CHECK18-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) +// CHECK18-NEXT: ret i32 [[TMP170]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK18-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 +// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 +// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 +// CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 +// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 +// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] +// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK18: omp_offload.failed.i: +// CHECK18-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 +// CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* +// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24 +// CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24 +// CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK18-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* +// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24 +// CHECK18-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24 +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK18: .omp_outlined..1.exit: +// CHECK18-NEXT: ret i32 0 +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 +// CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK18-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK18-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK18-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK18-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK18-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK18-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK18-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z6bazzzziPi +// CHECK18-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK18-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK18-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..20 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[F:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3bari +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP8]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i64 40, i1 false) +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK18-NEXT: store double* [[A]], double** [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK18-NEXT: store i64 2, i64* [[TMP22]], align 8 +// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* +// CHECK18-NEXT: store i64 2, i64* [[TMP24]], align 8 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 +// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 +// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 +// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 +// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK18-NEXT: store i8* null, i8** [[TMP36]], align 8 +// CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK18-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] +// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK18-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] +// CHECK18-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK18-NEXT: ret i32 [[ADD4]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 +// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP31]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP24]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..23 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK18-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK18-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK18-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK18-SAME: () #[[ATTR4]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK18-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 +// CHECK19-NEXT: [[NN:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 +// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 +// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK19-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 +// CHECK19-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) +// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* +// CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) +// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) +// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 +// CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) +// CHECK19-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] +// CHECK19-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK19-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 +// CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* +// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 +// CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 +// CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP63]], align 4 +// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 +// CHECK19-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 +// CHECK19-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* +// CHECK19-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 +// CHECK19-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 +// CHECK19-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 +// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 +// CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 +// CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 +// CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK19-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK19: omp_offload.failed15: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK19: omp_offload.cont16: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 +// CHECK19-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 +// CHECK19-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 +// CHECK19-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] +// CHECK19: omp_if.then19: +// CHECK19-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK19-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 +// CHECK19-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK19-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 +// CHECK19-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 +// CHECK19-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) +// CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* +// CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP97]], align 4 +// CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* +// CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP99]], align 4 +// CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP100]], align 4 +// CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 +// CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 +// CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP105]], align 4 +// CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP107]], align 4 +// CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP109]], align 4 +// CHECK19-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP110]], align 4 +// CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** +// CHECK19-NEXT: store float* [[VLA]], float** [[TMP112]], align 4 +// CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** +// CHECK19-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 +// CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK19-NEXT: store i64 [[TMP91]], i64* [[TMP115]], align 4 +// CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 +// CHECK19-NEXT: store i8* null, i8** [[TMP116]], align 4 +// CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4 +// CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 +// CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 +// CHECK19-NEXT: store i8* null, i8** [[TMP121]], align 4 +// CHECK19-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 +// CHECK19-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32* +// CHECK19-NEXT: store i32 5, i32* [[TMP123]], align 4 +// CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 +// CHECK19-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* +// CHECK19-NEXT: store i32 5, i32* [[TMP125]], align 4 +// CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 +// CHECK19-NEXT: store i8* null, i8** [[TMP126]], align 4 +// CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 +// CHECK19-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP128]], align 4 +// CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 +// CHECK19-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP130]], align 4 +// CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 +// CHECK19-NEXT: store i8* null, i8** [[TMP131]], align 4 +// CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 +// CHECK19-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** +// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP133]], align 4 +// CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 +// CHECK19-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** +// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP135]], align 4 +// CHECK19-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK19-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 4 +// CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 +// CHECK19-NEXT: store i8* null, i8** [[TMP137]], align 4 +// CHECK19-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 +// CHECK19-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4 +// CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 +// CHECK19-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4 +// CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 +// CHECK19-NEXT: store i8* null, i8** [[TMP142]], align 4 +// CHECK19-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 +// CHECK19-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] +// CHECK19: omp_offload.failed23: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT24]] +// CHECK19: omp_offload.cont24: +// CHECK19-NEXT: br label [[OMP_IF_END26:%.*]] +// CHECK19: omp_if.else25: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END26]] +// CHECK19: omp_if.end26: +// CHECK19-NEXT: store i32 0, i32* [[NN]], align 4 +// CHECK19-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK19-NEXT: store i32 [[TMP148]], i32* [[NN_CASTED]], align 4 +// CHECK19-NEXT: [[TMP149:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* +// CHECK19-NEXT: store i32 [[TMP149]], i32* [[TMP151]], align 4 +// CHECK19-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* +// CHECK19-NEXT: store i32 [[TMP149]], i32* [[TMP153]], align 4 +// CHECK19-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP154]], align 4 +// CHECK19-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 +// CHECK19-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK19: omp_offload.failed30: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP149]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK19: omp_offload.cont31: +// CHECK19-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK19-NEXT: store i32 [[TMP159]], i32* [[NN_CASTED32]], align 4 +// CHECK19-NEXT: [[TMP160:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 +// CHECK19-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32* +// CHECK19-NEXT: store i32 [[TMP160]], i32* [[TMP162]], align 4 +// CHECK19-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32* +// CHECK19-NEXT: store i32 [[TMP160]], i32* [[TMP164]], align 4 +// CHECK19-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP165]], align 4 +// CHECK19-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 +// CHECK19-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] +// CHECK19: omp_offload.failed36: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP160]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT37]] +// CHECK19: omp_offload.cont37: +// CHECK19-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) +// CHECK19-NEXT: ret i32 [[TMP170]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] +// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK19: omp_offload.failed.i: +// CHECK19-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25 +// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 +// CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK19: .omp_outlined..1.exit: +// CHECK19-NEXT: ret i32 0 +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 +// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK19-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK19-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK19-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK19-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK19-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK19-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK19-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK19-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK19-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK19-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK19-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK19-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK19-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK19-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK19-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK19-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK19-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK19-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK19-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK19-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z6bazzzziPi +// CHECK19-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP5]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK19-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK19-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..20 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3bari +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP8]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i32 40, i1 false) +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK19-NEXT: store double* [[A]], double** [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK19-NEXT: store i32 2, i32* [[TMP22]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK19-NEXT: store i32 2, i32* [[TMP24]], align 4 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 +// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 +// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 +// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK19-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] +// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK19-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] +// CHECK19-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK19-NEXT: ret i32 [[ADD3]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP31]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP24]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..23 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK19-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK19-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK19-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK19-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK19-SAME: () #[[ATTR4]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK19-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 +// CHECK20-NEXT: [[NN:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 +// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK20-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 +// CHECK20-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) +// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* +// CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK20-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) +// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) +// CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 +// CHECK20-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) +// CHECK20-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] +// CHECK20-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK20-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 +// CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* +// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 +// CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 +// CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP63]], align 4 +// CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK20-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 +// CHECK20-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 +// CHECK20-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* +// CHECK20-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 +// CHECK20-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 +// CHECK20-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 +// CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 +// CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 +// CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 +// CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK20-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK20: omp_offload.failed15: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK20: omp_offload.cont16: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 +// CHECK20-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 +// CHECK20-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 +// CHECK20-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] +// CHECK20: omp_if.then19: +// CHECK20-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK20-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 +// CHECK20-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK20-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 +// CHECK20-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 +// CHECK20-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) +// CHECK20-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* +// CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP97]], align 4 +// CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* +// CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP99]], align 4 +// CHECK20-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP100]], align 4 +// CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 +// CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 +// CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP105]], align 4 +// CHECK20-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP107]], align 4 +// CHECK20-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP109]], align 4 +// CHECK20-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP110]], align 4 +// CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** +// CHECK20-NEXT: store float* [[VLA]], float** [[TMP112]], align 4 +// CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** +// CHECK20-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 +// CHECK20-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK20-NEXT: store i64 [[TMP91]], i64* [[TMP115]], align 4 +// CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP116]], align 4 +// CHECK20-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4 +// CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 +// CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 +// CHECK20-NEXT: store i8* null, i8** [[TMP121]], align 4 +// CHECK20-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 +// CHECK20-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32* +// CHECK20-NEXT: store i32 5, i32* [[TMP123]], align 4 +// CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 +// CHECK20-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* +// CHECK20-NEXT: store i32 5, i32* [[TMP125]], align 4 +// CHECK20-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 +// CHECK20-NEXT: store i8* null, i8** [[TMP126]], align 4 +// CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 +// CHECK20-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP128]], align 4 +// CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 +// CHECK20-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP130]], align 4 +// CHECK20-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 +// CHECK20-NEXT: store i8* null, i8** [[TMP131]], align 4 +// CHECK20-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 +// CHECK20-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** +// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP133]], align 4 +// CHECK20-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 +// CHECK20-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** +// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP135]], align 4 +// CHECK20-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK20-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 4 +// CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 +// CHECK20-NEXT: store i8* null, i8** [[TMP137]], align 4 +// CHECK20-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 +// CHECK20-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4 +// CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 +// CHECK20-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4 +// CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 +// CHECK20-NEXT: store i8* null, i8** [[TMP142]], align 4 +// CHECK20-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 +// CHECK20-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] +// CHECK20: omp_offload.failed23: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT24]] +// CHECK20: omp_offload.cont24: +// CHECK20-NEXT: br label [[OMP_IF_END26:%.*]] +// CHECK20: omp_if.else25: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END26]] +// CHECK20: omp_if.end26: +// CHECK20-NEXT: store i32 0, i32* [[NN]], align 4 +// CHECK20-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK20-NEXT: store i32 [[TMP148]], i32* [[NN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP149:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* +// CHECK20-NEXT: store i32 [[TMP149]], i32* [[TMP151]], align 4 +// CHECK20-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* +// CHECK20-NEXT: store i32 [[TMP149]], i32* [[TMP153]], align 4 +// CHECK20-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP154]], align 4 +// CHECK20-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 +// CHECK20-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] +// CHECK20: omp_offload.failed30: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP149]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT31]] +// CHECK20: omp_offload.cont31: +// CHECK20-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 +// CHECK20-NEXT: store i32 [[TMP159]], i32* [[NN_CASTED32]], align 4 +// CHECK20-NEXT: [[TMP160:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 +// CHECK20-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32* +// CHECK20-NEXT: store i32 [[TMP160]], i32* [[TMP162]], align 4 +// CHECK20-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32* +// CHECK20-NEXT: store i32 [[TMP160]], i32* [[TMP164]], align 4 +// CHECK20-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP165]], align 4 +// CHECK20-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 +// CHECK20-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] +// CHECK20: omp_offload.failed36: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP160]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT37]] +// CHECK20: omp_offload.cont37: +// CHECK20-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) +// CHECK20-NEXT: ret i32 [[TMP170]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] +// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK20: omp_offload.failed.i: +// CHECK20-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25 +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 +// CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK20: .omp_outlined..1.exit: +// CHECK20-NEXT: ret i32 0 +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 +// CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK20-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK20-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK20-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK20-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK20-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK20-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK20-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK20-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK20-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK20-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK20-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK20-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK20-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK20-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK20-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK20-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK20-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK20-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK20-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..17 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z6bazzzziPi +// CHECK20-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP5]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 +// CHECK20-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK20-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..20 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3bari +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP8]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i32 40, i1 false) +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK20-NEXT: store double* [[A]], double** [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK20-NEXT: store i32 2, i32* [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK20-NEXT: store i32 2, i32* [[TMP24]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 +// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 +// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 +// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK20-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] +// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] +// CHECK20-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK20-NEXT: ret i32 [[ADD3]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP31]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP24]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..23 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK20-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK20-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK20-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..26 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..29 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK20-SAME: () #[[ATTR4]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK20-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK25-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK25-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK25-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK25-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK25-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK25-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK25-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK25-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[F:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK25-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double +// CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 +// CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float +// CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 +// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double +// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 +// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK26-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 +// CHECK26-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK26-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] +// CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 +// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 +// CHECK26-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 +// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 +// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK26-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 +// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 +// CHECK26-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 +// CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 +// CHECK26-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK26-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[F:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 +// CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 +// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 +// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 +// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 +// CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK26-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] +// CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK27-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK27-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK27-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK27-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK27-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK27-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK27-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK27-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK27-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK27-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK27-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK27-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK27-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK27-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK27-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK27-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK27-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK27-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 +// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double +// CHECK28-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK28-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float +// CHECK28-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 +// CHECK28-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double +// CHECK28-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 +// CHECK28-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float +// CHECK28-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 +// CHECK28-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK28-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 +// CHECK28-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 +// CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] +// CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 +// CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 +// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 +// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 +// CHECK28-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 +// CHECK28-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 +// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 +// CHECK28-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK28-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 +// CHECK28-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 +// CHECK28-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 +// CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 +// CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 +// CHECK28-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[F:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 +// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 +// CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 +// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 +// CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4 +// CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 +// CHECK28-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] +// CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 +// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_distribute_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_codegen.cpp @@ -3909,7 +3909,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -3934,7 +3934,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3997,7 +3997,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -4012,7 +4012,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4080,7 +4080,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -4103,7 +4103,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4177,7 +4177,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -4224,7 +4224,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4368,7 +4368,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -4410,7 +4410,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4534,7 +4534,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4561,7 +4561,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4650,7 +4650,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -4676,7 +4676,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4756,8 +4756,856 @@ // CHECK9-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK10: omp.dispatch.cond: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK10: omp.dispatch.body: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK10-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK10-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK10-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !13 +// CHECK10-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK10-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK10-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK10-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK10-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !13 +// CHECK10-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK10-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !13 +// CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !13 +// CHECK10-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK10-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !13 +// CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !13 +// CHECK10-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK10-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK10-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK10-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !13 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK10-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK10: omp.dispatch.inc: +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK10-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK10-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK10: omp.dispatch.end: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK10-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK10-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK10-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK10-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK10-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK10-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK10-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK10-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK10-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK10-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK10-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK10-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK10-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK10-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK10-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK10-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK10-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK10-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK10-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK10-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK10-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK10-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK10-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -4780,7 +5628,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4843,7 +5691,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -4858,7 +5706,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4926,7 +5774,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4947,7 +5795,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5020,7 +5868,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -5063,7 +5911,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5205,7 +6053,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5243,7 +6091,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5365,7 +6213,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5390,7 +6238,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5478,7 +6326,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5502,7 +6350,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5580,3 +6428,10898 @@ // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK11-NEXT: ret void // +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK12: omp.dispatch.cond: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK12: omp.dispatch.body: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK12-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK12-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK12-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK12-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK12-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK12-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK12-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !14 +// CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !14 +// CHECK12-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK12-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK12-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK12-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !14 +// CHECK12-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK12-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !14 +// CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK12-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK12-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK12-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK12-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK12-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK12: omp.dispatch.inc: +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK12-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK12-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK12: omp.dispatch.end: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK12-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK12-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK12-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK12-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK12-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK12-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK12-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK12-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK12-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK12-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK12-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK12-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK12-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK12-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK12-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK12-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK12-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK12-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK12-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK12-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK12-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK12-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A_CASTED23:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 +// CHECK17-NEXT: [[_TMP32:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* +// CHECK17-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 +// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 +// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK17-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK17-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 +// CHECK17-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) +// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) +// CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) +// CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 +// CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK17-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 +// CHECK17-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* +// CHECK17-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 +// CHECK17-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 +// CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 +// CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 +// CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP65]], align 8 +// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 +// CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK17-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 +// CHECK17-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK17-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* +// CHECK17-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 +// CHECK17-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 +// CHECK17-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 +// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 +// CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 +// CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 +// CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK17-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 +// CHECK17-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] +// CHECK17: omp_offload.failed20: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT21]] +// CHECK17: omp_offload.cont21: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK17-NEXT: [[TMP90:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32* +// CHECK17-NEXT: store i32 [[TMP90]], i32* [[CONV24]], align 4 +// CHECK17-NEXT: [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8 +// CHECK17-NEXT: [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK17-NEXT: [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32* +// CHECK17-NEXT: store i32 [[TMP92]], i32* [[CONV26]], align 4 +// CHECK17-NEXT: [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8 +// CHECK17-NEXT: [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20 +// CHECK17-NEXT: br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]] +// CHECK17: omp_if.then28: +// CHECK17-NEXT: [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK17-NEXT: [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK17-NEXT: [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8 +// CHECK17-NEXT: [[TMP98:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP98]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.10 to i8*), i64 80, i1 false) +// CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i64* +// CHECK17-NEXT: store i64 [[TMP91]], i64* [[TMP100]], align 8 +// CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* +// CHECK17-NEXT: store i64 [[TMP91]], i64* [[TMP102]], align 8 +// CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP103]], align 8 +// CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8 +// CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8 +// CHECK17-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP108]], align 8 +// CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 +// CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP112]], align 8 +// CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP113]], align 8 +// CHECK17-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to float** +// CHECK17-NEXT: store float* [[VLA]], float** [[TMP115]], align 8 +// CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** +// CHECK17-NEXT: store float* [[VLA]], float** [[TMP117]], align 8 +// CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK17-NEXT: store i64 [[TMP95]], i64* [[TMP118]], align 8 +// CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3 +// CHECK17-NEXT: store i8* null, i8** [[TMP119]], align 8 +// CHECK17-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to [5 x [10 x double]]** +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP121]], align 8 +// CHECK17-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8 +// CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4 +// CHECK17-NEXT: store i8* null, i8** [[TMP124]], align 8 +// CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5 +// CHECK17-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* +// CHECK17-NEXT: store i64 5, i64* [[TMP126]], align 8 +// CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5 +// CHECK17-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* +// CHECK17-NEXT: store i64 5, i64* [[TMP128]], align 8 +// CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5 +// CHECK17-NEXT: store i8* null, i8** [[TMP129]], align 8 +// CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6 +// CHECK17-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP131]], align 8 +// CHECK17-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6 +// CHECK17-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP133]], align 8 +// CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6 +// CHECK17-NEXT: store i8* null, i8** [[TMP134]], align 8 +// CHECK17-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7 +// CHECK17-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to double** +// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP136]], align 8 +// CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7 +// CHECK17-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** +// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 +// CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK17-NEXT: store i64 [[TMP97]], i64* [[TMP139]], align 8 +// CHECK17-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7 +// CHECK17-NEXT: store i8* null, i8** [[TMP140]], align 8 +// CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8 +// CHECK17-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to %struct.TT** +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP142]], align 8 +// CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8 +// CHECK17-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 +// CHECK17-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8 +// CHECK17-NEXT: store i8* null, i8** [[TMP145]], align 8 +// CHECK17-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9 +// CHECK17-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* +// CHECK17-NEXT: store i64 [[TMP93]], i64* [[TMP147]], align 8 +// CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9 +// CHECK17-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* +// CHECK17-NEXT: store i64 [[TMP93]], i64* [[TMP149]], align 8 +// CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9 +// CHECK17-NEXT: store i8* null, i8** [[TMP150]], align 8 +// CHECK17-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP153:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK17-NEXT: [[TMP154:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP151]], i8** [[TMP152]], i64* [[TMP153]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP155:%.*]] = icmp ne i32 [[TMP154]], 0 +// CHECK17-NEXT: br i1 [[TMP155]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK17: omp_offload.failed33: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK17: omp_offload.cont34: +// CHECK17-NEXT: br label [[OMP_IF_END36:%.*]] +// CHECK17: omp_if.else35: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END36]] +// CHECK17: omp_if.end36: +// CHECK17-NEXT: [[TMP156:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP157:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP157]]) +// CHECK17-NEXT: ret i32 [[TMP156]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK17: cond.true: +// CHECK17-NEXT: br label [[COND_END:%.*]] +// CHECK17: cond.false: +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: br label [[COND_END]] +// CHECK17: cond.end: +// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK17: omp.inner.for.cond: +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK17: omp.inner.for.body: +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK17: omp.body.continue: +// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK17: omp.inner.for.inc: +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK17: omp.inner.for.end: +// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK17: omp.loop.exit: +// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 +// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] +// CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] +// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK17: omp_offload.failed.i: +// CHECK17-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21 +// CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* +// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !21 +// CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !21 +// CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK17-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* +// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !21 +// CHECK17-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !21 +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK17: .omp_outlined..1.exit: +// CHECK17-NEXT: ret i32 0 +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 +// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK17: cond.true: +// CHECK17-NEXT: br label [[COND_END:%.*]] +// CHECK17: cond.false: +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: br label [[COND_END]] +// CHECK17: cond.end: +// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK17: omp.inner.for.cond: +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK17: omp.inner.for.body: +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK17-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4 +// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK17: omp.body.continue: +// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK17: omp.inner.for.inc: +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK17: omp.inner.for.end: +// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK17: omp.loop.exit: +// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK17: cond.true: +// CHECK17-NEXT: br label [[COND_END:%.*]] +// CHECK17: cond.false: +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: br label [[COND_END]] +// CHECK17: cond.end: +// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK17: omp.inner.for.cond: +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK17: omp.inner.for.body: +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK17: omp.body.continue: +// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK17: omp.inner.for.inc: +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK17: omp.inner.for.end: +// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK17: omp.loop.exit: +// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK17: cond.true: +// CHECK17-NEXT: br label [[COND_END:%.*]] +// CHECK17: cond.false: +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: br label [[COND_END]] +// CHECK17: cond.end: +// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK17: omp.inner.for.cond: +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK17: omp.inner.for.body: +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK17: omp.body.continue: +// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK17: omp.inner.for.inc: +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK17: omp.inner.for.end: +// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK17: omp.loop.exit: +// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK17: omp.dispatch.cond: +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK17: cond.true: +// CHECK17-NEXT: br label [[COND_END:%.*]] +// CHECK17: cond.false: +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: br label [[COND_END]] +// CHECK17: cond.end: +// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK17: omp.dispatch.body: +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK17: omp.inner.for.cond: +// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK17: omp.inner.for.body: +// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK17-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !22 +// CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !22 +// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !22 +// CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !22 +// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !22 +// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !22 +// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !22 +// CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !22 +// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK17: omp.body.continue: +// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK17: omp.inner.for.inc: +// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK17: omp.inner.for.end: +// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK17: omp.dispatch.inc: +// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK17: omp.dispatch.end: +// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3bari +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP8]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i64 40, i1 false) +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK17-NEXT: store double* [[A]], double** [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK17-NEXT: store i64 2, i64* [[TMP22]], align 8 +// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* +// CHECK17-NEXT: store i64 2, i64* [[TMP24]], align 8 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 +// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 +// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 +// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 +// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK17-NEXT: store i8* null, i8** [[TMP36]], align 8 +// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK17-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK17-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] +// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK17-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] +// CHECK17-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK17-NEXT: ret i32 [[ADD4]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK17-NEXT: store i8 [[TMP6]], i8* [[CONV3]], align 1 +// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK17-NEXT: store i64 [[TMP7]], i64* [[TMP25]], align 8 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK17-NEXT: store i64 [[TMP7]], i64* [[TMP27]], align 8 +// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8 +// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK17-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK17-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] +// CHECK17-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK17-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK17-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK17-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK17-NEXT: [[ADD8:%.*]] = add i32 [[TMP40]], 1 +// CHECK17-NEXT: [[TMP41:%.*]] = zext i32 [[ADD8]] to i64 +// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) +// CHECK17-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK17-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP44]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK17: omp_if.then: +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK17: omp_if.else: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK17-NEXT: br label [[OMP_IF_END]] +// CHECK17: omp_if.end: +// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP24]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK17: cond.true: +// CHECK17-NEXT: br label [[COND_END:%.*]] +// CHECK17: cond.false: +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: br label [[COND_END]] +// CHECK17: cond.end: +// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK17: omp.inner.for.cond: +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK17: omp.inner.for.body: +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK17-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK17-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK17-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK17-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK17-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK17: omp.body.continue: +// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK17: omp.inner.for.inc: +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK17: omp.inner.for.end: +// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK17: omp.loop.exit: +// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK17-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK17-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK17-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK17-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK17: omp.precond.then: +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK17-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK17-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK17: cond.true: +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK17-NEXT: br label [[COND_END:%.*]] +// CHECK17: cond.false: +// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: br label [[COND_END]] +// CHECK17: cond.end: +// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK17: omp.inner.for.cond: +// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK17-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK17-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK17: omp.inner.for.body: +// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK17-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4 +// CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK17-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK17-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK17-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK17: omp.body.continue: +// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK17: omp.inner.for.inc: +// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK17-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK17: omp.inner.for.end: +// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK17: omp.loop.exit: +// CHECK17-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK17-NEXT: br label [[OMP_PRECOND_END]] +// CHECK17: omp.precond.end: +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK17: cond.true: +// CHECK17-NEXT: br label [[COND_END:%.*]] +// CHECK17: cond.false: +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: br label [[COND_END]] +// CHECK17: cond.end: +// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK17: omp.inner.for.cond: +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK17: omp.inner.for.body: +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK17: omp.body.continue: +// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK17: omp.inner.for.inc: +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK17: omp.inner.for.end: +// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK17: omp.loop.exit: +// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK17-SAME: () #[[ATTR4]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK17-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A_CASTED23:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 +// CHECK18-NEXT: [[_TMP32:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +// CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 +// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* +// CHECK18-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* +// CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* +// CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* +// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* +// CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 +// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 +// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 +// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK18-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 +// CHECK18-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK18-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* +// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 +// CHECK18-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) +// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* +// CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) +// CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) +// CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) +// CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 +// CHECK18-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) +// CHECK18-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 +// CHECK18-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] +// CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* +// CHECK18-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 +// CHECK18-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 +// CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* +// CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 +// CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* +// CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 +// CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP65]], align 8 +// CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 +// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK18-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 +// CHECK18-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* +// CHECK18-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 +// CHECK18-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 +// CHECK18-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* +// CHECK18-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 +// CHECK18-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 +// CHECK18-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* +// CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 +// CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* +// CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 +// CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP79]], align 8 +// CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* +// CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 +// CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* +// CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 +// CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP84]], align 8 +// CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 +// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK18-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 +// CHECK18-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] +// CHECK18: omp_offload.failed20: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT21]] +// CHECK18: omp_offload.cont21: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK18-NEXT: [[TMP90:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32* +// CHECK18-NEXT: store i32 [[TMP90]], i32* [[CONV24]], align 4 +// CHECK18-NEXT: [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8 +// CHECK18-NEXT: [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 +// CHECK18-NEXT: [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32* +// CHECK18-NEXT: store i32 [[TMP92]], i32* [[CONV26]], align 4 +// CHECK18-NEXT: [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8 +// CHECK18-NEXT: [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20 +// CHECK18-NEXT: br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]] +// CHECK18: omp_if.then28: +// CHECK18-NEXT: [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4 +// CHECK18-NEXT: [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]] +// CHECK18-NEXT: [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8 +// CHECK18-NEXT: [[TMP98:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP98]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.10 to i8*), i64 80, i1 false) +// CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i64* +// CHECK18-NEXT: store i64 [[TMP91]], i64* [[TMP100]], align 8 +// CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* +// CHECK18-NEXT: store i64 [[TMP91]], i64* [[TMP102]], align 8 +// CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP103]], align 8 +// CHECK18-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8 +// CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8 +// CHECK18-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP108]], align 8 +// CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 +// CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP112]], align 8 +// CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP113]], align 8 +// CHECK18-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to float** +// CHECK18-NEXT: store float* [[VLA]], float** [[TMP115]], align 8 +// CHECK18-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** +// CHECK18-NEXT: store float* [[VLA]], float** [[TMP117]], align 8 +// CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK18-NEXT: store i64 [[TMP95]], i64* [[TMP118]], align 8 +// CHECK18-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3 +// CHECK18-NEXT: store i8* null, i8** [[TMP119]], align 8 +// CHECK18-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to [5 x [10 x double]]** +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP121]], align 8 +// CHECK18-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8 +// CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4 +// CHECK18-NEXT: store i8* null, i8** [[TMP124]], align 8 +// CHECK18-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5 +// CHECK18-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* +// CHECK18-NEXT: store i64 5, i64* [[TMP126]], align 8 +// CHECK18-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5 +// CHECK18-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* +// CHECK18-NEXT: store i64 5, i64* [[TMP128]], align 8 +// CHECK18-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5 +// CHECK18-NEXT: store i8* null, i8** [[TMP129]], align 8 +// CHECK18-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6 +// CHECK18-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP131]], align 8 +// CHECK18-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6 +// CHECK18-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP133]], align 8 +// CHECK18-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6 +// CHECK18-NEXT: store i8* null, i8** [[TMP134]], align 8 +// CHECK18-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7 +// CHECK18-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to double** +// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP136]], align 8 +// CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7 +// CHECK18-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** +// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 +// CHECK18-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK18-NEXT: store i64 [[TMP97]], i64* [[TMP139]], align 8 +// CHECK18-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7 +// CHECK18-NEXT: store i8* null, i8** [[TMP140]], align 8 +// CHECK18-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8 +// CHECK18-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to %struct.TT** +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP142]], align 8 +// CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8 +// CHECK18-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 +// CHECK18-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8 +// CHECK18-NEXT: store i8* null, i8** [[TMP145]], align 8 +// CHECK18-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9 +// CHECK18-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* +// CHECK18-NEXT: store i64 [[TMP93]], i64* [[TMP147]], align 8 +// CHECK18-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9 +// CHECK18-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* +// CHECK18-NEXT: store i64 [[TMP93]], i64* [[TMP149]], align 8 +// CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9 +// CHECK18-NEXT: store i8* null, i8** [[TMP150]], align 8 +// CHECK18-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP153:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK18-NEXT: [[TMP154:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP151]], i8** [[TMP152]], i64* [[TMP153]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP155:%.*]] = icmp ne i32 [[TMP154]], 0 +// CHECK18-NEXT: br i1 [[TMP155]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK18: omp_offload.failed33: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK18: omp_offload.cont34: +// CHECK18-NEXT: br label [[OMP_IF_END36:%.*]] +// CHECK18: omp_if.else35: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END36]] +// CHECK18: omp_if.end36: +// CHECK18-NEXT: [[TMP156:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP157:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP157]]) +// CHECK18-NEXT: ret i32 [[TMP156]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK18-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 +// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 +// CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 +// CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 +// CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 +// CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 +// CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 +// CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 +// CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 +// CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 +// CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 +// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 +// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 +// CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 +// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 +// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] +// CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] +// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK18: omp_offload.failed.i: +// CHECK18-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* +// CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21 +// CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* +// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !21 +// CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !21 +// CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK18-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* +// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !21 +// CHECK18-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !21 +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK18: .omp_outlined..1.exit: +// CHECK18-NEXT: ret i32 0 +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 +// CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK18: omp.dispatch.cond: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK18: omp.dispatch.body: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK18-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK18-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !22 +// CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !22 +// CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK18-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK18-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK18-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !22 +// CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !22 +// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !22 +// CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !22 +// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !22 +// CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !22 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK18: omp.dispatch.inc: +// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK18-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK18: omp.dispatch.end: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3bari +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP8]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i64 40, i1 false) +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK18-NEXT: store double* [[A]], double** [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK18-NEXT: store i64 2, i64* [[TMP22]], align 8 +// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* +// CHECK18-NEXT: store i64 2, i64* [[TMP24]], align 8 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP25]], align 8 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 +// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 +// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 +// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 +// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK18-NEXT: store i8* null, i8** [[TMP36]], align 8 +// CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK18-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK18-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] +// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK18-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] +// CHECK18-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK18-NEXT: ret i32 [[ADD4]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK18-NEXT: store i8 [[TMP6]], i8* [[CONV3]], align 1 +// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 +// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* +// CHECK18-NEXT: store i64 [[TMP7]], i64* [[TMP25]], align 8 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* +// CHECK18-NEXT: store i64 [[TMP7]], i64* [[TMP27]], align 8 +// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK18-NEXT: store i8* null, i8** [[TMP28]], align 8 +// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8 +// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 +// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] +// CHECK18-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK18-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK18-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: [[ADD8:%.*]] = add i32 [[TMP40]], 1 +// CHECK18-NEXT: [[TMP41:%.*]] = zext i32 [[ADD8]] to i64 +// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) +// CHECK18-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK18-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP44]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK18: omp_if.then: +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* +// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 +// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK18: omp_if.else: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK18-NEXT: br label [[OMP_IF_END]] +// CHECK18: omp_if.end: +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP24]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK18-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK18-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK18-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK18-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK18-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK18-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK18-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK18-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK18-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK18-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK18: omp.precond.then: +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK18-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK18-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK18-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK18-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK18-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK18-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK18-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK18-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK18-NEXT: br label [[OMP_PRECOND_END]] +// CHECK18: omp.precond.end: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK18-SAME: () #[[ATTR4]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK18-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED19:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 +// CHECK19-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 +// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 +// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK19-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 +// CHECK19-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) +// CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* +// CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) +// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) +// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 +// CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]]) +// CHECK19-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] +// CHECK19-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK19-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 +// CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* +// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 +// CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 +// CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP63]], align 4 +// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 +// CHECK19-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 +// CHECK19-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* +// CHECK19-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 +// CHECK19-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 +// CHECK19-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 +// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 +// CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 +// CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 +// CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK19-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK19-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK19: omp_offload.failed16: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK19: omp_offload.cont17: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK19-NEXT: [[TMP88:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP88]], i32* [[A_CASTED19]], align 4 +// CHECK19-NEXT: [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4 +// CHECK19-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK19-NEXT: store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK19-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK19-NEXT: [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20 +// CHECK19-NEXT: br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]] +// CHECK19: omp_if.then22: +// CHECK19-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK19-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 +// CHECK19-NEXT: [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK19-NEXT: [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8 +// CHECK19-NEXT: [[TMP97:%.*]] = sext i32 [[TMP96]] to i64 +// CHECK19-NEXT: [[TMP98:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP98]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.10 to i8*), i32 80, i1 false) +// CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* +// CHECK19-NEXT: store i32 [[TMP89]], i32* [[TMP100]], align 4 +// CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* +// CHECK19-NEXT: store i32 [[TMP89]], i32* [[TMP102]], align 4 +// CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP103]], align 4 +// CHECK19-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4 +// CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4 +// CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP108]], align 4 +// CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 +// CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP112]], align 4 +// CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP113]], align 4 +// CHECK19-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to float** +// CHECK19-NEXT: store float* [[VLA]], float** [[TMP115]], align 4 +// CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** +// CHECK19-NEXT: store float* [[VLA]], float** [[TMP117]], align 4 +// CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK19-NEXT: store i64 [[TMP94]], i64* [[TMP118]], align 4 +// CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3 +// CHECK19-NEXT: store i8* null, i8** [[TMP119]], align 4 +// CHECK19-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to [5 x [10 x double]]** +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP121]], align 4 +// CHECK19-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4 +// CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4 +// CHECK19-NEXT: store i8* null, i8** [[TMP124]], align 4 +// CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5 +// CHECK19-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* +// CHECK19-NEXT: store i32 5, i32* [[TMP126]], align 4 +// CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5 +// CHECK19-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* +// CHECK19-NEXT: store i32 5, i32* [[TMP128]], align 4 +// CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5 +// CHECK19-NEXT: store i8* null, i8** [[TMP129]], align 4 +// CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6 +// CHECK19-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP131]], align 4 +// CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6 +// CHECK19-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP133]], align 4 +// CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6 +// CHECK19-NEXT: store i8* null, i8** [[TMP134]], align 4 +// CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7 +// CHECK19-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to double** +// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP136]], align 4 +// CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7 +// CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** +// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 +// CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK19-NEXT: store i64 [[TMP97]], i64* [[TMP139]], align 4 +// CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7 +// CHECK19-NEXT: store i8* null, i8** [[TMP140]], align 4 +// CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8 +// CHECK19-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to %struct.TT** +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP142]], align 4 +// CHECK19-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8 +// CHECK19-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 +// CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8 +// CHECK19-NEXT: store i8* null, i8** [[TMP145]], align 4 +// CHECK19-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9 +// CHECK19-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* +// CHECK19-NEXT: store i32 [[TMP91]], i32* [[TMP147]], align 4 +// CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9 +// CHECK19-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK19-NEXT: store i32 [[TMP91]], i32* [[TMP149]], align 4 +// CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9 +// CHECK19-NEXT: store i8* null, i8** [[TMP150]], align 4 +// CHECK19-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP153:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK19-NEXT: [[TMP154:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP151]], i8** [[TMP152]], i64* [[TMP153]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP155:%.*]] = icmp ne i32 [[TMP154]], 0 +// CHECK19-NEXT: br i1 [[TMP155]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] +// CHECK19: omp_offload.failed27: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT28]] +// CHECK19: omp_offload.cont28: +// CHECK19-NEXT: br label [[OMP_IF_END30:%.*]] +// CHECK19: omp_if.else29: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END30]] +// CHECK19: omp_if.end30: +// CHECK19-NEXT: [[TMP156:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP157:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP157]]) +// CHECK19-NEXT: ret i32 [[TMP156]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK19: cond.true: +// CHECK19-NEXT: br label [[COND_END:%.*]] +// CHECK19: cond.false: +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: br label [[COND_END]] +// CHECK19: cond.end: +// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK19: omp.inner.for.cond: +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK19: omp.inner.for.body: +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK19: omp.body.continue: +// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK19: omp.inner.for.inc: +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK19: omp.inner.for.end: +// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK19: omp.loop.exit: +// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] +// CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] +// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK19: omp_offload.failed.i: +// CHECK19-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !22 +// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22 +// CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22 +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK19: .omp_outlined..1.exit: +// CHECK19-NEXT: ret i32 0 +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 +// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK19: cond.true: +// CHECK19-NEXT: br label [[COND_END:%.*]] +// CHECK19: cond.false: +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: br label [[COND_END]] +// CHECK19: cond.end: +// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK19: omp.inner.for.cond: +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK19: omp.inner.for.body: +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK19: omp.body.continue: +// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK19: omp.inner.for.inc: +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK19: omp.inner.for.end: +// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK19: omp.loop.exit: +// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK19: cond.true: +// CHECK19-NEXT: br label [[COND_END:%.*]] +// CHECK19: cond.false: +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: br label [[COND_END]] +// CHECK19: cond.end: +// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK19: omp.inner.for.cond: +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK19: omp.inner.for.body: +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK19: omp.body.continue: +// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK19: omp.inner.for.inc: +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK19: omp.inner.for.end: +// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK19: omp.loop.exit: +// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK19: cond.true: +// CHECK19-NEXT: br label [[COND_END:%.*]] +// CHECK19: cond.false: +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: br label [[COND_END]] +// CHECK19: cond.end: +// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK19: omp.inner.for.cond: +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK19: omp.inner.for.body: +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK19: omp.body.continue: +// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK19: omp.inner.for.inc: +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK19: omp.inner.for.end: +// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK19: omp.loop.exit: +// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK19: omp.dispatch.cond: +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK19: cond.true: +// CHECK19-NEXT: br label [[COND_END:%.*]] +// CHECK19: cond.false: +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: br label [[COND_END]] +// CHECK19: cond.end: +// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK19: omp.dispatch.body: +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK19: omp.inner.for.cond: +// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK19: omp.inner.for.body: +// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK19-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !23 +// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !23 +// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !23 +// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !23 +// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK19: omp.body.continue: +// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK19: omp.inner.for.inc: +// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK19: omp.inner.for.end: +// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK19: omp.dispatch.inc: +// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK19: omp.dispatch.end: +// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3bari +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP8]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i32 40, i1 false) +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK19-NEXT: store double* [[A]], double** [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK19-NEXT: store i32 2, i32* [[TMP22]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK19-NEXT: store i32 2, i32* [[TMP24]], align 4 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 +// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 +// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 +// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK19-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK19-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] +// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK19-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] +// CHECK19-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK19-NEXT: ret i32 [[ADD3]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK19-NEXT: store i8 [[TMP6]], i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK19-NEXT: store i32 [[TMP7]], i32* [[TMP25]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK19-NEXT: store i32 [[TMP7]], i32* [[TMP27]], align 4 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK19-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4 +// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] +// CHECK19-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK19-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK19-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK19-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK19-NEXT: [[ADD6:%.*]] = add i32 [[TMP40]], 1 +// CHECK19-NEXT: [[TMP41:%.*]] = zext i32 [[ADD6]] to i64 +// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) +// CHECK19-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK19-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP44]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK19: omp_if.then: +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK19: omp_if.else: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK19-NEXT: br label [[OMP_IF_END]] +// CHECK19: omp_if.end: +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP24]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK19: cond.true: +// CHECK19-NEXT: br label [[COND_END:%.*]] +// CHECK19: cond.false: +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: br label [[COND_END]] +// CHECK19: cond.end: +// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK19: omp.inner.for.cond: +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK19: omp.inner.for.body: +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK19-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK19-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK19-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK19-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK19-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK19: omp.body.continue: +// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK19: omp.inner.for.inc: +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK19: omp.inner.for.end: +// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK19: omp.loop.exit: +// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK19-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK19-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK19-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK19-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK19: omp.precond.then: +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK19-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK19-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK19: cond.true: +// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK19-NEXT: br label [[COND_END:%.*]] +// CHECK19: cond.false: +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: br label [[COND_END]] +// CHECK19: cond.end: +// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK19: omp.inner.for.cond: +// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK19-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK19-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK19: omp.inner.for.body: +// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK19-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK19-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK19-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK19-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK19: omp.body.continue: +// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK19: omp.inner.for.inc: +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK19-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK19: omp.inner.for.end: +// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK19: omp.loop.exit: +// CHECK19-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK19-NEXT: br label [[OMP_PRECOND_END]] +// CHECK19: omp.precond.end: +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK19: cond.true: +// CHECK19-NEXT: br label [[COND_END:%.*]] +// CHECK19: cond.false: +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: br label [[COND_END]] +// CHECK19: cond.end: +// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK19: omp.inner.for.cond: +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK19: omp.inner.for.body: +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK19: omp.body.continue: +// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK19: omp.inner.for.inc: +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK19: omp.inner.for.end: +// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK19: omp.loop.exit: +// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK19-SAME: () #[[ATTR4]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK19-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED19:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 +// CHECK20-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* +// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 +// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 +// CHECK20-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) +// CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* +// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 +// CHECK20-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) +// CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* +// CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) +// CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* +// CHECK20-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) +// CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* +// CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) +// CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 +// CHECK20-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]]) +// CHECK20-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] +// CHECK20-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* +// CHECK20-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 +// CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 +// CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* +// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 +// CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* +// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 +// CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP63]], align 4 +// CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 +// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK20-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 +// CHECK20-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 +// CHECK20-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 +// CHECK20-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* +// CHECK20-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 +// CHECK20-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 +// CHECK20-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* +// CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 +// CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* +// CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 +// CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP77]], align 4 +// CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* +// CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 +// CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* +// CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 +// CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP82]], align 4 +// CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK20-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 +// CHECK20-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] +// CHECK20: omp_offload.failed16: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT17]] +// CHECK20: omp_offload.cont17: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK20-NEXT: [[TMP88:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP88]], i32* [[A_CASTED19]], align 4 +// CHECK20-NEXT: [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4 +// CHECK20-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 +// CHECK20-NEXT: store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK20-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 +// CHECK20-NEXT: [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20 +// CHECK20-NEXT: br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]] +// CHECK20: omp_if.then22: +// CHECK20-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK20-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 +// CHECK20-NEXT: [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]] +// CHECK20-NEXT: [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8 +// CHECK20-NEXT: [[TMP97:%.*]] = sext i32 [[TMP96]] to i64 +// CHECK20-NEXT: [[TMP98:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP98]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.10 to i8*), i32 80, i1 false) +// CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* +// CHECK20-NEXT: store i32 [[TMP89]], i32* [[TMP100]], align 4 +// CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* +// CHECK20-NEXT: store i32 [[TMP89]], i32* [[TMP102]], align 4 +// CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP103]], align 4 +// CHECK20-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4 +// CHECK20-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4 +// CHECK20-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP108]], align 4 +// CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 +// CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP112]], align 4 +// CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP113]], align 4 +// CHECK20-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to float** +// CHECK20-NEXT: store float* [[VLA]], float** [[TMP115]], align 4 +// CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** +// CHECK20-NEXT: store float* [[VLA]], float** [[TMP117]], align 4 +// CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK20-NEXT: store i64 [[TMP94]], i64* [[TMP118]], align 4 +// CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP119]], align 4 +// CHECK20-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to [5 x [10 x double]]** +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP121]], align 4 +// CHECK20-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4 +// CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4 +// CHECK20-NEXT: store i8* null, i8** [[TMP124]], align 4 +// CHECK20-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5 +// CHECK20-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* +// CHECK20-NEXT: store i32 5, i32* [[TMP126]], align 4 +// CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5 +// CHECK20-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* +// CHECK20-NEXT: store i32 5, i32* [[TMP128]], align 4 +// CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5 +// CHECK20-NEXT: store i8* null, i8** [[TMP129]], align 4 +// CHECK20-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6 +// CHECK20-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP131]], align 4 +// CHECK20-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6 +// CHECK20-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP133]], align 4 +// CHECK20-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6 +// CHECK20-NEXT: store i8* null, i8** [[TMP134]], align 4 +// CHECK20-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7 +// CHECK20-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to double** +// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP136]], align 4 +// CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7 +// CHECK20-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** +// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 +// CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK20-NEXT: store i64 [[TMP97]], i64* [[TMP139]], align 4 +// CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7 +// CHECK20-NEXT: store i8* null, i8** [[TMP140]], align 4 +// CHECK20-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8 +// CHECK20-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to %struct.TT** +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP142]], align 4 +// CHECK20-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8 +// CHECK20-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 +// CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8 +// CHECK20-NEXT: store i8* null, i8** [[TMP145]], align 4 +// CHECK20-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9 +// CHECK20-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* +// CHECK20-NEXT: store i32 [[TMP91]], i32* [[TMP147]], align 4 +// CHECK20-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9 +// CHECK20-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* +// CHECK20-NEXT: store i32 [[TMP91]], i32* [[TMP149]], align 4 +// CHECK20-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9 +// CHECK20-NEXT: store i8* null, i8** [[TMP150]], align 4 +// CHECK20-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP153:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK20-NEXT: [[TMP154:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP151]], i8** [[TMP152]], i64* [[TMP153]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP155:%.*]] = icmp ne i32 [[TMP154]], 0 +// CHECK20-NEXT: br i1 [[TMP155]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] +// CHECK20: omp_offload.failed27: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT28]] +// CHECK20: omp_offload.cont28: +// CHECK20-NEXT: br label [[OMP_IF_END30:%.*]] +// CHECK20: omp_if.else29: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END30]] +// CHECK20: omp_if.end30: +// CHECK20-NEXT: [[TMP156:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP157:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP157]]) +// CHECK20-NEXT: ret i32 [[TMP156]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 +// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 +// CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 +// CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 +// CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 +// CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 +// CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 +// CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 +// CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 +// CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 +// CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 +// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 +// CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 +// CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* +// CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* +// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] +// CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] +// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK20: omp_offload.failed.i: +// CHECK20-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 +// CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* +// CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !22 +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22 +// CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22 +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] +// CHECK20: .omp_outlined..1.exit: +// CHECK20-NEXT: ret i32 0 +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 +// CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK20: omp.dispatch.cond: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK20: omp.dispatch.body: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK20-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !23 +// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !23 +// CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK20-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK20-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !23 +// CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !23 +// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK20: omp.dispatch.inc: +// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK20-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK20: omp.dispatch.end: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3bari +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP8]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 +// CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* +// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i32 40, i1 false) +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** +// CHECK20-NEXT: store double* [[A]], double** [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK20-NEXT: store i32 2, i32* [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* +// CHECK20-NEXT: store i32 2, i32* [[TMP24]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** +// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 +// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** +// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 +// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 +// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 +// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK20-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 +// CHECK20-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] +// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 +// CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] +// CHECK20-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK20-NEXT: ret i32 [[ADD3]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP6]], i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* +// CHECK20-NEXT: store i32 [[TMP7]], i32* [[TMP25]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* +// CHECK20-NEXT: store i32 [[TMP7]], i32* [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK20-NEXT: store i8* null, i8** [[TMP28]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4 +// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4 +// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] +// CHECK20-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK20-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK20-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: [[ADD6:%.*]] = add i32 [[TMP40]], 1 +// CHECK20-NEXT: [[TMP41:%.*]] = zext i32 [[ADD6]] to i64 +// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) +// CHECK20-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 +// CHECK20-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP44]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK20: omp_if.then: +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) +// CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) +// CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 +// CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK20: omp_if.else: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK20-NEXT: br label [[OMP_IF_END]] +// CHECK20: omp_if.end: +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP24]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK20-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK20-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK20-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK20-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK20-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK20-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK20-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK20: omp.precond.then: +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK20-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK20-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK20-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK20-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK20-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK20-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK20-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK20-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK20-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK20-NEXT: br label [[OMP_PRECOND_END]] +// CHECK20: omp.precond.end: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..18 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK20-SAME: () #[[ATTR4]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK20-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK25-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK25-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK25-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK25: omp.dispatch.cond: +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK25: omp.dispatch.body: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK25-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK25-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK25-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK25-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !13 +// CHECK25-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !13 +// CHECK25-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK25-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK25-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK25-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !13 +// CHECK25-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !13 +// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !13 +// CHECK25-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK25-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !13 +// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK25-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !13 +// CHECK25-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK25-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK25-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK25-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !13 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK25-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK25: omp.dispatch.inc: +// CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK25-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK25-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK25: omp.dispatch.end: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK25-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK25-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK25-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK25-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK25-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK25-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK25: omp.precond.then: +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK25-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK25-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK25-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK25-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK25-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK25-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK25-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK25-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK25-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4 +// CHECK25-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2 +// CHECK25-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK25-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK25-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK25-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK25-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK25-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK25-NEXT: br label [[OMP_PRECOND_END]] +// CHECK25: omp.precond.end: +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK25-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK25-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK25-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK25-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK25-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK25-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK25-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK25: cond.true: +// CHECK25-NEXT: br label [[COND_END:%.*]] +// CHECK25: cond.false: +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: br label [[COND_END]] +// CHECK25: cond.end: +// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK25-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK25: omp.loop.exit: +// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK25-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK26-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK26-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK26-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 +// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK26: omp.dispatch.cond: +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK26: omp.dispatch.body: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK26-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double +// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 +// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float +// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double +// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 +// CHECK26-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float +// CHECK26-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK26-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !13 +// CHECK26-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !13 +// CHECK26-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK26-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] +// CHECK26-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 +// CHECK26-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !13 +// CHECK26-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !13 +// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !13 +// CHECK26-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK26-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !13 +// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK26-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !13 +// CHECK26-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK26-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 +// CHECK26-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 +// CHECK26-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !13 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK26-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK26: omp.dispatch.inc: +// CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK26-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK26-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK26: omp.dispatch.end: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK26-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK26-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK26-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK26-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK26-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK26-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK26: omp.precond.then: +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK26-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK26-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK26-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK26-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK26-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK26-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK26-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 +// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK26-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK26-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4 +// CHECK26-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2 +// CHECK26-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK26-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK26-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK26-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK26-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK26-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK26-NEXT: br label [[OMP_PRECOND_END]] +// CHECK26: omp.precond.end: +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK26-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD5]], double* [[A]], align 8 +// CHECK26-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 +// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK26-NEXT: store double [[INC]], double* [[A6]], align 8 +// CHECK26-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK26-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK26-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK26-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK26: cond.true: +// CHECK26-NEXT: br label [[COND_END:%.*]] +// CHECK26: cond.false: +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: br label [[COND_END]] +// CHECK26: cond.end: +// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK26-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK26: omp.loop.exit: +// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK26-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK27-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK27-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK27-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK27: omp.dispatch.cond: +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK27: omp.dispatch.body: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK27-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK27-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK27-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK27-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK27-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK27-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK27-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK27-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK27-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !14 +// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !14 +// CHECK27-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK27-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK27-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK27-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !14 +// CHECK27-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !14 +// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK27-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK27-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK27-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK27-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK27-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK27-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK27: omp.dispatch.inc: +// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK27-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK27-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK27: omp.dispatch.end: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK27-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK27-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK27-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK27-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK27-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK27-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK27: omp.precond.then: +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK27-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK27-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK27-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK27-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK27-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK27-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK27-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 +// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK27-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 +// CHECK27-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK27-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK27-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK27-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK27-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK27-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK27-NEXT: br label [[OMP_PRECOND_END]] +// CHECK27: omp.precond.end: +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK27-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK27-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK27-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK27-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK27-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK27-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK27-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK27-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK27: cond.true: +// CHECK27-NEXT: br label [[COND_END:%.*]] +// CHECK27: cond.false: +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: br label [[COND_END]] +// CHECK27: cond.end: +// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK27: omp.loop.exit: +// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK27-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 +// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK28-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 +// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK28-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 +// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) +// CHECK28-NEXT: br label [[OMP_DISPATCH_COND:%.*]] +// CHECK28: omp.dispatch.cond: +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK28: omp.dispatch.body: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK28-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK28-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK28-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK28-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK28-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK28-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double +// CHECK28-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK28-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK28-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !14 +// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !14 +// CHECK28-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK28-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] +// CHECK28-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 +// CHECK28-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !14 +// CHECK28-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !14 +// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 +// CHECK28-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK28-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 +// CHECK28-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK28-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK28-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK28-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_DISPATCH_INC:%.*]] +// CHECK28: omp.dispatch.inc: +// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK28-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK28-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[OMP_DISPATCH_COND]] +// CHECK28: omp.dispatch.end: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 +// CHECK28-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK28-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK28-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK28-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK28-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK28-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK28: omp.precond.then: +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK28-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK28-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK28-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK28-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK28-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK28-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK28-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 +// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK28-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 +// CHECK28-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK28-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK28-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK28-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK28-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK28-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK28-NEXT: br label [[OMP_PRECOND_END]] +// CHECK28: omp.precond.end: +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK28-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK28-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD4]], double* [[A]], align 4 +// CHECK28-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 +// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK28-NEXT: store double [[INC]], double* [[A5]], align 4 +// CHECK28-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK28-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK28-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK28-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK28: cond.true: +// CHECK28-NEXT: br label [[COND_END:%.*]] +// CHECK28: cond.false: +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: br label [[COND_END]] +// CHECK28: cond.end: +// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK28: omp.loop.exit: +// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK28-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp @@ -1878,7 +1878,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK10-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -1906,7 +1906,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1999,7 +1999,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2116,7 +2116,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK10-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -2137,7 +2137,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2233,7 +2233,7 @@ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2339,8 +2339,470 @@ // CHECK10-NEXT: ret void // // +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 +// CHECK11-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) +// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK11-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK11-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK11-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK11-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK11-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK11-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK11-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) +// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK11-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK11: .cancel.exit: +// CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK11: .cancel.continue: +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: cancel.exit: +// CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK11-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: br label [[CANCEL_CONT]] +// CHECK11: cancel.cont: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 +// CHECK11-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK11: omp.precond.then: +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK11-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK11-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK11-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK11: cond.true: +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: br label [[COND_END:%.*]] +// CHECK11: cond.false: +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: br label [[COND_END]] +// CHECK11: cond.end: +// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK11: omp.inner.for.cond: +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK11-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 +// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK11: omp.body.continue: +// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK11: omp.inner.for.inc: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK11: omp.inner.for.end: +// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK11: omp.loop.exit: +// CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK11-NEXT: br label [[OMP_PRECOND_END]] +// CHECK11: omp.precond.end: +// CHECK11-NEXT: ret void +// +// // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK12-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -2364,7 +2826,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2453,7 +2915,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2566,7 +3028,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK12-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -2585,7 +3047,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2677,7 +3139,7 @@ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2778,3 +3240,443 @@ // CHECK12: omp.precond.end: // CHECK12-NEXT: ret void // +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 +// CHECK13-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) +// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], [1000 x i32]* [[TMP1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK13: omp.precond.then: +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]]) +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) +// CHECK13-NEXT: br label [[OMP_PRECOND_END]] +// CHECK13: omp.precond.end: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK13: omp.precond.then: +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK13-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) +// CHECK13-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK13-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] +// CHECK13: .cancel.exit: +// CHECK13-NEXT: br label [[CANCEL_EXIT:%.*]] +// CHECK13: .cancel.continue: +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK13-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK13-NEXT: br label [[OMP_PRECOND_END]] +// CHECK13: cancel.exit: +// CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK13-NEXT: br label [[CANCEL_CONT:%.*]] +// CHECK13: omp.precond.end: +// CHECK13-NEXT: br label [[CANCEL_CONT]] +// CHECK13: cancel.cont: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 +// CHECK13-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK13: omp.precond.then: +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK13-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK13-NEXT: br label [[OMP_PRECOND_END]] +// CHECK13: omp.precond.end: +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK13: omp.precond.then: +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK13: cond.true: +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: br label [[COND_END:%.*]] +// CHECK13: cond.false: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: br label [[COND_END]] +// CHECK13: cond.end: +// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 +// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK13: omp.loop.exit: +// CHECK13-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK13-NEXT: br label [[OMP_PRECOND_END]] +// CHECK13: omp.precond.end: +// CHECK13-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -2721,7 +2721,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -2753,7 +2753,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2803,17 +2803,17 @@ // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2865,14 +2865,14 @@ // CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -2880,17 +2880,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -2898,22 +2898,22 @@ // CHECK13-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2971,17 +2971,17 @@ // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done6: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3040,14 +3040,14 @@ // CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -3055,17 +3055,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -3092,7 +3092,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3141,18 +3141,18 @@ // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: // CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3202,14 +3202,14 @@ // CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -3217,7 +3217,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -3225,12 +3225,12 @@ // CHECK13-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3288,18 +3288,18 @@ // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done6: // CHECK13-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK13-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -3356,14 +3356,14 @@ // CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -3371,17 +3371,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -3394,7 +3394,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -3403,7 +3403,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3412,7 +3412,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -3432,7 +3432,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3441,7 +3441,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -3459,8 +3459,747 @@ // CHECK13-NEXT: ret void // // +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 +// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK14-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK14-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK14: omp.arraycpy.body: +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK14: omp.arraycpy.done4: +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done11: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK14-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK14-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK14: omp.arraycpy.body: +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK14: omp.arraycpy.done6: +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK14-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK14-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] +// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done15: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK14-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK14-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK14-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK14: omp.arraycpy.body: +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK14: omp.arraycpy.done4: +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 +// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done11: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK14-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK14-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK14-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK14: omp.arraycpy.body: +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK14: omp.arraycpy.done6: +// CHECK14-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK14-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 +// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK14-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* +// CHECK14-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done15: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK14-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK14-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK14-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK14-NEXT: ret void +// +// // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3488,7 +4227,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3536,17 +4275,17 @@ // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3594,14 +4333,14 @@ // CHECK15-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done8: @@ -3609,17 +4348,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3627,22 +4366,22 @@ // CHECK15-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3696,17 +4435,17 @@ // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3763,14 +4502,14 @@ // CHECK15-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done11: @@ -3778,17 +4517,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3813,7 +4552,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3861,18 +4600,18 @@ // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: // CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3919,14 +4658,14 @@ // CHECK15-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -3934,7 +4673,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3942,12 +4681,12 @@ // CHECK15-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4002,18 +4741,18 @@ // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: // CHECK15-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -4068,14 +4807,14 @@ // CHECK15-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: @@ -4083,17 +4822,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -4106,7 +4845,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -4115,7 +4854,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4124,7 +4863,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -4144,7 +4883,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4153,7 +4892,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4171,8 +4910,720 @@ // CHECK15-NEXT: ret void // // +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 +// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK16-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK16-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK16: omp.arraycpy.body: +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK16: omp.arraycpy.done3: +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done8: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK16-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK16-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK16: omp.arraycpy.body: +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK16: omp.arraycpy.done3: +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] +// CHECK16-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] +// CHECK16-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* +// CHECK16-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] +// CHECK16-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK16-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done11: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK16-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK16-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK16: omp.arraycpy.body: +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK16: omp.arraycpy.done4: +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done10: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK16-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK16-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK16: omp.arraycpy.body: +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK16: omp.arraycpy.done4: +// CHECK16-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] +// CHECK16-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] +// CHECK16-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK16-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK16-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done12: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK16-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK16-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK16-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK16-NEXT: ret void +// +// // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK17-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -4206,7 +5657,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4293,7 +5744,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4370,7 +5821,7 @@ // CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp @@ -1937,7 +1937,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1964,12 +1964,12 @@ // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2013,14 +2013,14 @@ // CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done3: @@ -2028,17 +2028,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2075,12 +2075,12 @@ // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2139,14 +2139,14 @@ // CHECK13-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done8: @@ -2154,12 +2154,12 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // @@ -2171,7 +2171,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2200,12 +2200,12 @@ // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2250,14 +2250,14 @@ // CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done5: @@ -2265,17 +2265,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2314,12 +2314,12 @@ // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2376,14 +2376,14 @@ // CHECK13-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done9: @@ -2391,17 +2391,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2414,7 +2414,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2423,7 +2423,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2435,7 +2435,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2443,6 +2443,520 @@ // CHECK13-NEXT: ret void // // +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 +// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK14-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK14: arrayctor.loop: +// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK14: arrayctor.cont: +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK14-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done3: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK14-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK14: arrayctor.loop: +// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK14: arrayctor.cont: +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK14-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* +// CHECK14-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 +// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] +// CHECK14-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK14-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done8: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 +// CHECK14-SAME: () #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK14: arrayctor.loop: +// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK14: arrayctor.cont: +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done5: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK14-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK14: arrayctor.loop: +// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK14: arrayctor.cont: +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK14-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK14-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* +// CHECK14-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK14-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done9: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK14-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: @@ -2451,7 +2965,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2478,12 +2992,12 @@ // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2525,14 +3039,14 @@ // CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done3: @@ -2540,17 +3054,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2585,12 +3099,12 @@ // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2647,14 +3161,14 @@ // CHECK15-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: @@ -2662,12 +3176,12 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // @@ -2679,7 +3193,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2708,12 +3222,12 @@ // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2756,14 +3270,14 @@ // CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done5: @@ -2771,17 +3285,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2818,12 +3332,12 @@ // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2878,14 +3392,14 @@ // CHECK15-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done7: @@ -2893,17 +3407,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2916,7 +3430,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2925,7 +3439,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2937,7 +3451,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2945,6 +3459,508 @@ // CHECK15-NEXT: ret void // // +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 +// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK16-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK16: arrayctor.loop: +// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK16: arrayctor.cont: +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK16-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done3: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK16-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK16: arrayctor.loop: +// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK16: arrayctor.cont: +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK16-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* +// CHECK16-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 +// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] +// CHECK16-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK16-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done6: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 +// CHECK16-SAME: () #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK16: arrayctor.loop: +// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK16: arrayctor.cont: +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done5: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK16: arrayctor.loop: +// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK16: arrayctor.cont: +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK16-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* +// CHECK16-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done7: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK16-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -2953,7 +3969,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3020,7 +4036,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3093,7 +4109,7 @@ // CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp @@ -1835,7 +1835,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK9-SAME: (i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -1871,7 +1871,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1986,7 +1986,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2121,7 +2121,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK9-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -2142,7 +2142,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2250,7 +2250,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2368,8 +2368,542 @@ // CHECK9-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 +// CHECK10-SAME: (i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) +// CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32]* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I4]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0 +// CHECK10-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ] +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 +// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32]* [[TMP0]]) +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 +// CHECK10-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK10: .omp.final.then: +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK10-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1 +// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4 +// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK10: .omp.final.done: +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I4]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0 +// CHECK10-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ] +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32 +// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]]) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP12]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP13]], [[TMP14]] +// CHECK10-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[I7]], align 4 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK10-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK10: .omp.final.then: +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0 +// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 +// CHECK10-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1 +// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] +// CHECK10-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4 +// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK10: .omp.final.done: +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK10-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK10: .omp.linear.pu: +// CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK10: .omp.linear.pu.done: +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 +// CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !12 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK10-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK10: .omp.final.then: +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB7:%.*]] = sub nsw i32 [[TMP27]], 0 +// CHECK10-NEXT: [[DIV8:%.*]] = sdiv i32 [[SUB7]], 1 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV8]], 1 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[I3]], align 4 +// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK10: .omp.final.done: +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 +// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK10: omp.precond.then: +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 +// CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK10: cond.true: +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: br label [[COND_END:%.*]] +// CHECK10: cond.false: +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: br label [[COND_END]] +// CHECK10: cond.end: +// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK10: omp.inner.for.cond: +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK10: omp.inner.for.body: +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !16 +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK10: omp.body.continue: +// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK10: omp.inner.for.inc: +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK10: omp.inner.for.end: +// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK10: omp.loop.exit: +// CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK10: .omp.final.then: +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK10-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK10-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1 +// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK10-NEXT: store i32 [[ADD13]], i32* [[I5]], align 4 +// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK10: .omp.final.done: +// CHECK10-NEXT: br label [[OMP_PRECOND_END]] +// CHECK10: omp.precond.end: +// CHECK10-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK11-SAME: (i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -2399,7 +2933,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2508,7 +3042,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2638,7 +3172,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK11-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -2657,7 +3191,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2761,7 +3295,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2874,3 +3408,1114 @@ // CHECK11: omp.precond.end: // CHECK11-NEXT: ret void // +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 +// CHECK12-SAME: (i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) +// CHECK12-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[I_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I_CASTED]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], i32 [[TMP7]], [1000 x i32]* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i32 8) ] +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK12-NEXT: store i32 [[TMP16]], i32* [[I_CASTED]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I_CASTED]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], i32 [[TMP19]], [1000 x i32]* [[TMP0]]) +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK12-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK12: .omp.final.then: +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK12-NEXT: [[DIV8:%.*]] = sdiv i32 [[SUB7]], 1 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV8]], 1 +// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD9]], i32* [[I_ADDR]], align 4 +// CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK12: .omp.final.done: +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i32 8) ] +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]]) +// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP12]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP13]], [[TMP14]] +// CHECK12-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] +// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[I4]], align 4 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP21]] +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK12-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK12: .omp.final.then: +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i32 [[TMP27]], 0 +// CHECK12-NEXT: [[DIV10:%.*]] = sdiv i32 [[SUB9]], 1 +// CHECK12-NEXT: [[MUL11:%.*]] = mul nsw i32 [[DIV10]], 1 +// CHECK12-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]] +// CHECK12-NEXT: store i32 [[ADD12]], i32* [[I_ADDR]], align 4 +// CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK12: .omp.final.done: +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK12-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] +// CHECK12: .omp.linear.pu: +// CHECK12-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] +// CHECK12: .omp.linear.pu.done: +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 +// CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]), !llvm.access.group !13 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK12-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK12: .omp.final.then: +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV7]], 1 +// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[I3]], align 4 +// CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK12: .omp.final.done: +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 +// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 +// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] +// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK12: omp.precond.then: +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] +// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK12: cond.true: +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: br label [[COND_END:%.*]] +// CHECK12: cond.false: +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: br label [[COND_END]] +// CHECK12: cond.end: +// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK12: omp.inner.for.cond: +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK12: omp.inner.for.body: +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK12: omp.body.continue: +// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK12: omp.inner.for.inc: +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK12: omp.inner.for.end: +// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK12: omp.loop.exit: +// CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 +// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK12-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK12: .omp.final.then: +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK12-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 +// CHECK12-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 1 +// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] +// CHECK12-NEXT: store i32 [[ADD11]], i32* [[I3]], align 4 +// CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK12: .omp.final.done: +// CHECK12-NEXT: br label [[OMP_PRECOND_END]] +// CHECK12: omp.precond.end: +// CHECK12-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_Z16target_teams_funPi +// CHECK13-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 +// CHECK13-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I23:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_IV26:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I27:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK13-NEXT: store i32 1000, i32* [[N]], align 4 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 +// CHECK13-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 +// CHECK13-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK13-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK13-NEXT: [[DIV4:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK13-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV4]], 1 +// CHECK13-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[I6]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK13-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK13: simd.if.then: +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 +// CHECK13-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ] +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK13-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[N]], align 4 +// CHECK13-NEXT: store i32 [[TMP9]], i32* [[DOTLINEAR_STEP]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK13-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[I7]], align 4 +// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK13-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK13-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP15]], 0 +// CHECK13-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 +// CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK13-NEXT: store i32 [[ADD14]], i32* [[I]], align 4 +// CHECK13-NEXT: br label [[SIMD_IF_END]] +// CHECK13: simd.if.end: +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 +// CHECK13-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK13-NEXT: [[SUB18:%.*]] = sub nsw i32 [[TMP17]], 0 +// CHECK13-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 1 +// CHECK13-NEXT: [[SUB20:%.*]] = sub nsw i32 [[DIV19]], 1 +// CHECK13-NEXT: store i32 [[SUB20]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK13-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB22]], align 4 +// CHECK13-NEXT: store i32 0, i32* [[I23]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK13-NEXT: [[CMP24:%.*]] = icmp slt i32 0, [[TMP19]] +// CHECK13-NEXT: br i1 [[CMP24]], label [[SIMD_IF_THEN25:%.*]], label [[SIMD_IF_END44:%.*]] +// CHECK13: simd.if.then25: +// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK13-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV26]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND28:%.*]] +// CHECK13: omp.inner.for.cond28: +// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !5 +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !5 +// CHECK13-NEXT: [[CMP29:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] +// CHECK13-NEXT: br i1 [[CMP29]], label [[OMP_INNER_FOR_BODY30:%.*]], label [[OMP_INNER_FOR_END39:%.*]] +// CHECK13: omp.inner.for.body30: +// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !5 +// CHECK13-NEXT: [[MUL31:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK13-NEXT: [[ADD32:%.*]] = add nsw i32 0, [[MUL31]] +// CHECK13-NEXT: store i32 [[ADD32]], i32* [[I27]], align 4, !llvm.access.group !5 +// CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !5 +// CHECK13-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 0 +// CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !5 +// CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[I27]], align 4, !llvm.access.group !5 +// CHECK13-NEXT: [[IDXPROM34:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK13-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM34]] +// CHECK13-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX35]], align 4, !llvm.access.group !5 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE36:%.*]] +// CHECK13: omp.body.continue36: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC37:%.*]] +// CHECK13: omp.inner.for.inc37: +// CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !5 +// CHECK13-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK13-NEXT: store i32 [[ADD38]], i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !5 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND28]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK13: omp.inner.for.end39: +// CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK13-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK13-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 +// CHECK13-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 +// CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] +// CHECK13-NEXT: store i32 [[ADD43]], i32* [[I27]], align 4 +// CHECK13-NEXT: br label [[SIMD_IF_END44]] +// CHECK13: simd.if.end44: +// CHECK13-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 +// CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX45]], align 4 +// CHECK13-NEXT: ret i32 [[TMP29]] +// +// +// CHECK14-LABEL: define {{[^@]+}}@_Z16target_teams_funPi +// CHECK14-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 +// CHECK14-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I23:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IV26:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I27:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 +// CHECK14-NEXT: store i32 1000, i32* [[N]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 +// CHECK14-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 +// CHECK14-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK14-NEXT: [[DIV4:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK14-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV4]], 1 +// CHECK14-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[I6]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK14: simd.if.then: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 +// CHECK14-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ] +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START]], align 4 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[N]], align 4 +// CHECK14-NEXT: store i32 [[TMP9]], i32* [[DOTLINEAR_STEP]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I7]], align 4 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK14-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK14-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP15]], 0 +// CHECK14-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK14-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 +// CHECK14-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK14-NEXT: store i32 [[ADD14]], i32* [[I]], align 4 +// CHECK14-NEXT: br label [[SIMD_IF_END]] +// CHECK14: simd.if.end: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 +// CHECK14-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK14-NEXT: [[SUB18:%.*]] = sub nsw i32 [[TMP17]], 0 +// CHECK14-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 1 +// CHECK14-NEXT: [[SUB20:%.*]] = sub nsw i32 [[DIV19]], 1 +// CHECK14-NEXT: store i32 [[SUB20]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK14-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB22]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[I23]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK14-NEXT: [[CMP24:%.*]] = icmp slt i32 0, [[TMP19]] +// CHECK14-NEXT: br i1 [[CMP24]], label [[SIMD_IF_THEN25:%.*]], label [[SIMD_IF_END44:%.*]] +// CHECK14: simd.if.then25: +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK14-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV26]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND28:%.*]] +// CHECK14: omp.inner.for.cond28: +// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !5 +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !5 +// CHECK14-NEXT: [[CMP29:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] +// CHECK14-NEXT: br i1 [[CMP29]], label [[OMP_INNER_FOR_BODY30:%.*]], label [[OMP_INNER_FOR_END39:%.*]] +// CHECK14: omp.inner.for.body30: +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !5 +// CHECK14-NEXT: [[MUL31:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK14-NEXT: [[ADD32:%.*]] = add nsw i32 0, [[MUL31]] +// CHECK14-NEXT: store i32 [[ADD32]], i32* [[I27]], align 4, !llvm.access.group !5 +// CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !5 +// CHECK14-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 0 +// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !5 +// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[I27]], align 4, !llvm.access.group !5 +// CHECK14-NEXT: [[IDXPROM34:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK14-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM34]] +// CHECK14-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX35]], align 4, !llvm.access.group !5 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE36:%.*]] +// CHECK14: omp.body.continue36: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC37:%.*]] +// CHECK14: omp.inner.for.inc37: +// CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !5 +// CHECK14-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK14-NEXT: store i32 [[ADD38]], i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !5 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND28]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK14: omp.inner.for.end39: +// CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK14-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK14-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 +// CHECK14-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 +// CHECK14-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] +// CHECK14-NEXT: store i32 [[ADD43]], i32* [[I27]], align 4 +// CHECK14-NEXT: br label [[SIMD_IF_END44]] +// CHECK14: simd.if.end44: +// CHECK14-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 +// CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX45]], align 4 +// CHECK14-NEXT: ret i32 [[TMP29]] +// +// +// CHECK15-LABEL: define {{[^@]+}}@_Z16target_teams_funPi +// CHECK15-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 +// CHECK15-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I23:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_IV26:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I27:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK15-NEXT: store i32 1000, i32* [[N]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 +// CHECK15-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 +// CHECK15-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK15-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK15-NEXT: [[DIV4:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK15-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV4]], 1 +// CHECK15-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[I6]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK15-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK15: simd.if.then: +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK15-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 +// CHECK15-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i32 8) ] +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK15-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[N]], align 4 +// CHECK15-NEXT: store i32 [[TMP9]], i32* [[DOTLINEAR_STEP]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK15-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK15-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I7]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK15-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK15-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP15]], 0 +// CHECK15-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 +// CHECK15-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK15-NEXT: store i32 [[ADD14]], i32* [[I]], align 4 +// CHECK15-NEXT: br label [[SIMD_IF_END]] +// CHECK15: simd.if.end: +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 +// CHECK15-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK15-NEXT: [[SUB18:%.*]] = sub nsw i32 [[TMP17]], 0 +// CHECK15-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 1 +// CHECK15-NEXT: [[SUB20:%.*]] = sub nsw i32 [[DIV19]], 1 +// CHECK15-NEXT: store i32 [[SUB20]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK15-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB22]], align 4 +// CHECK15-NEXT: store i32 0, i32* [[I23]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK15-NEXT: [[CMP24:%.*]] = icmp slt i32 0, [[TMP19]] +// CHECK15-NEXT: br i1 [[CMP24]], label [[SIMD_IF_THEN25:%.*]], label [[SIMD_IF_END43:%.*]] +// CHECK15: simd.if.then25: +// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK15-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV26]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND28:%.*]] +// CHECK15: omp.inner.for.cond28: +// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[CMP29:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] +// CHECK15-NEXT: br i1 [[CMP29]], label [[OMP_INNER_FOR_BODY30:%.*]], label [[OMP_INNER_FOR_END38:%.*]] +// CHECK15: omp.inner.for.body30: +// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[MUL31:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK15-NEXT: [[ADD32:%.*]] = add nsw i32 0, [[MUL31]] +// CHECK15-NEXT: store i32 [[ADD32]], i32* [[I27]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[TMP24:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 0 +// CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[I27]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP26]] +// CHECK15-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX34]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE35:%.*]] +// CHECK15: omp.body.continue35: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC36:%.*]] +// CHECK15: omp.inner.for.inc36: +// CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[ADD37:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK15-NEXT: store i32 [[ADD37]], i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND28]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK15: omp.inner.for.end38: +// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK15-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK15-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 +// CHECK15-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 +// CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] +// CHECK15-NEXT: store i32 [[ADD42]], i32* [[I27]], align 4 +// CHECK15-NEXT: br label [[SIMD_IF_END43]] +// CHECK15: simd.if.end43: +// CHECK15-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX44]], align 4 +// CHECK15-NEXT: ret i32 [[TMP29]] +// +// +// CHECK16-LABEL: define {{[^@]+}}@_Z16target_teams_funPi +// CHECK16-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 +// CHECK16-NEXT: [[TE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TH:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I7:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I23:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV26:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I27:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 +// CHECK16-NEXT: store i32 1000, i32* [[N]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 +// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 +// CHECK16-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 +// CHECK16-NEXT: store i32 128, i32* [[TH]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 +// CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 +// CHECK16-NEXT: [[DIV4:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK16-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV4]], 1 +// CHECK16-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[I6]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK16: simd.if.then: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 +// CHECK16-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i32 8) ] +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[N]], align 4 +// CHECK16-NEXT: store i32 [[TMP9]], i32* [[DOTLINEAR_STEP]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK16-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I7]], align 4 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP13]] +// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK16-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK16-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP15]], 0 +// CHECK16-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 +// CHECK16-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 +// CHECK16-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK16-NEXT: store i32 [[ADD14]], i32* [[I]], align 4 +// CHECK16-NEXT: br label [[SIMD_IF_END]] +// CHECK16: simd.if.end: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 +// CHECK16-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK16-NEXT: [[SUB18:%.*]] = sub nsw i32 [[TMP17]], 0 +// CHECK16-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 1 +// CHECK16-NEXT: [[SUB20:%.*]] = sub nsw i32 [[DIV19]], 1 +// CHECK16-NEXT: store i32 [[SUB20]], i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_17]], align 4 +// CHECK16-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB22]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[I23]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK16-NEXT: [[CMP24:%.*]] = icmp slt i32 0, [[TMP19]] +// CHECK16-NEXT: br i1 [[CMP24]], label [[SIMD_IF_THEN25:%.*]], label [[SIMD_IF_END43:%.*]] +// CHECK16: simd.if.then25: +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK16-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV26]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND28:%.*]] +// CHECK16: omp.inner.for.cond28: +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[CMP29:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] +// CHECK16-NEXT: br i1 [[CMP29]], label [[OMP_INNER_FOR_BODY30:%.*]], label [[OMP_INNER_FOR_END38:%.*]] +// CHECK16: omp.inner.for.body30: +// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[MUL31:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK16-NEXT: [[ADD32:%.*]] = add nsw i32 0, [[MUL31]] +// CHECK16-NEXT: store i32 [[ADD32]], i32* [[I27]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[TMP24:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 0 +// CHECK16-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[I27]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP26]] +// CHECK16-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX34]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE35:%.*]] +// CHECK16: omp.body.continue35: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC36:%.*]] +// CHECK16: omp.inner.for.inc36: +// CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[ADD37:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK16-NEXT: store i32 [[ADD37]], i32* [[DOTOMP_IV26]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND28]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK16: omp.inner.for.end38: +// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 +// CHECK16-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK16-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 +// CHECK16-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 +// CHECK16-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] +// CHECK16-NEXT: store i32 [[ADD42]], i32* [[I27]], align 4 +// CHECK16-NEXT: br label [[SIMD_IF_END43]] +// CHECK16: simd.if.end43: +// CHECK16-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX44]], align 4 +// CHECK16-NEXT: ret i32 [[TMP29]] +// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -3571,7 +3571,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -3603,7 +3603,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3653,17 +3653,17 @@ // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3722,14 +3722,14 @@ // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -3737,17 +3737,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -3755,22 +3755,22 @@ // CHECK13-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3828,17 +3828,17 @@ // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done6: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3904,14 +3904,14 @@ // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -3919,17 +3919,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -3956,7 +3956,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4005,18 +4005,18 @@ // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: // CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4073,14 +4073,14 @@ // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -4088,7 +4088,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -4096,12 +4096,12 @@ // CHECK13-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4159,18 +4159,18 @@ // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done6: // CHECK13-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK13-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -4234,14 +4234,14 @@ // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -4249,17 +4249,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -4272,7 +4272,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -4281,7 +4281,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4290,7 +4290,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -4310,7 +4310,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4319,7 +4319,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -4337,8 +4337,775 @@ // CHECK13-NEXT: ret void // // +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 +// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK14-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK14-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK14: omp.arraycpy.body: +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK14: omp.arraycpy.done4: +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 +// CHECK14-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK14: .omp.final.then: +// CHECK14-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK14: .omp.final.done: +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done11: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK14-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK14-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK14: omp.arraycpy.body: +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK14: omp.arraycpy.done6: +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK14-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK14-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* +// CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10 +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] +// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK14-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK14: .omp.final.then: +// CHECK14-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK14: .omp.final.done: +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done15: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK14-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK14-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK14-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK14-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK14: omp.arraycpy.body: +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK14: omp.arraycpy.done4: +// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* +// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) +// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 +// CHECK14-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK14: .omp.final.then: +// CHECK14-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK14: .omp.final.done: +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done11: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 +// CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK14-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK14-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 +// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* +// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* +// CHECK14-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK14-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK14: omp.arraycpy.body: +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK14: omp.arraycpy.done6: +// CHECK14-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] +// CHECK14-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK14-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* +// CHECK14-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false), !llvm.access.group !18 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK14-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK14: .omp.final.then: +// CHECK14-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK14: .omp.final.done: +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done15: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK14-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 +// CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK14-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK14-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 +// CHECK14-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK14-NEXT: ret void +// +// // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -4366,7 +5133,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4414,17 +5181,17 @@ // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -4479,14 +5246,14 @@ // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done8: @@ -4494,17 +5261,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -4512,22 +5279,22 @@ // CHECK15-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4581,17 +5348,17 @@ // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -4655,14 +5422,14 @@ // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done11: @@ -4670,17 +5437,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -4705,7 +5472,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4753,18 +5520,18 @@ // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: // CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4818,14 +5585,14 @@ // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -4833,7 +5600,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4841,12 +5608,12 @@ // CHECK15-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4901,18 +5668,18 @@ // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: // CHECK15-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -4974,14 +5741,14 @@ // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: @@ -4989,17 +5756,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -5012,7 +5779,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -5021,7 +5788,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5030,7 +5797,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -5050,7 +5817,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5059,7 +5826,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -5077,8 +5844,748 @@ // CHECK15-NEXT: ret void // // +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 +// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK16-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK16-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK16: omp.arraycpy.body: +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK16: omp.arraycpy.done3: +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]), !llvm.access.group !7 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK16-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK16: .omp.final.then: +// CHECK16-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK16: .omp.final.done: +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done8: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN2StC1Ev +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN2StD1Ev +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK16-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* +// CHECK16-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* +// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK16: omp.arraycpy.body: +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] +// CHECK16: omp.arraycpy.done3: +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] +// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] +// CHECK16-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] +// CHECK16-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* +// CHECK16-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !11 +// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] +// CHECK16-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK16-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK16-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK16: .omp.final.then: +// CHECK16-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK16: .omp.final.done: +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done11: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 +// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK16-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK16-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK16-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK16: omp.arraycpy.body: +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK16: omp.arraycpy.done4: +// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]), !llvm.access.group !16 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) +// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK16-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK16: .omp.final.then: +// CHECK16-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK16: .omp.final.done: +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done10: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 +// CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 +// CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 +// CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK16-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 +// CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* +// CHECK16-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* +// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK16: omp.arraycpy.body: +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] +// CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] +// CHECK16: omp.arraycpy.done4: +// CHECK16-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] +// CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] +// CHECK16-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] +// CHECK16-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* +// CHECK16-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false), !llvm.access.group !19 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK16-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK16-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK16: .omp.final.then: +// CHECK16-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK16: .omp.final.done: +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done12: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN2StC2Ev +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 +// CHECK16-NEXT: store i32 0, i32* [[B]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN2StD2Ev +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 +// CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float +// CHECK16-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] +// CHECK16-NEXT: store float [[ADD]], float* [[F]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 +// CHECK16-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 +// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK16-NEXT: ret void +// +// // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK17-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -5112,7 +6619,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5206,7 +6713,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5283,7 +6790,7 @@ // CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !9 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9 +// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp @@ -2901,7 +2901,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2928,12 +2928,12 @@ // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2984,14 +2984,14 @@ // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done3: @@ -2999,17 +2999,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3046,12 +3046,12 @@ // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3117,14 +3117,14 @@ // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done8: @@ -3132,12 +3132,12 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // @@ -3149,7 +3149,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3178,12 +3178,12 @@ // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -3235,14 +3235,14 @@ // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done5: @@ -3250,17 +3250,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3299,12 +3299,12 @@ // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -3368,14 +3368,14 @@ // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done9: @@ -3383,17 +3383,17 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3406,7 +3406,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3415,7 +3415,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3427,7 +3427,7 @@ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3435,6 +3435,548 @@ // CHECK13-NEXT: ret void // // +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 +// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK14-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK14: arrayctor.loop: +// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK14: arrayctor.cont: +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK14-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK14: .omp.final.then: +// CHECK14-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK14: .omp.final.done: +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK14-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done3: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK14-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK14: arrayctor.loop: +// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 +// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK14: arrayctor.cont: +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK14-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* +// CHECK14-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !10 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] +// CHECK14-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK14-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK14-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK14: .omp.final.then: +// CHECK14-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK14: .omp.final.done: +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done8: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 +// CHECK14-SAME: () #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK14: arrayctor.loop: +// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK14: arrayctor.cont: +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK14-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK14-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK14: .omp.final.then: +// CHECK14-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK14: .omp.final.done: +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done5: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK14-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK14-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK14: arrayctor.loop: +// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 +// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK14: arrayctor.cont: +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK14: cond.true: +// CHECK14-NEXT: br label [[COND_END:%.*]] +// CHECK14: cond.false: +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: br label [[COND_END]] +// CHECK14: cond.end: +// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK14: omp.inner.for.cond: +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK14-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK14: omp.inner.for.cond.cleanup: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK14: omp.inner.for.body: +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK14-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* +// CHECK14-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !18 +// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK14: omp.body.continue: +// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK14: omp.inner.for.inc: +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK14-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK14: omp.inner.for.end: +// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK14: omp.loop.exit: +// CHECK14-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK14-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 +// CHECK14-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK14: .omp.final.then: +// CHECK14-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK14: .omp.final.done: +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 +// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK14: arraydestroy.body: +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] +// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK14: arraydestroy.done9: +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK14-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK14-NEXT: ret void +// +// +// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-NEXT: entry: +// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK14-NEXT: ret void +// +// // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: @@ -3443,7 +3985,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3470,12 +4012,12 @@ // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3524,14 +4066,14 @@ // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done3: @@ -3539,17 +4081,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3584,12 +4126,12 @@ // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3653,14 +4195,14 @@ // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: @@ -3668,12 +4210,12 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // @@ -3685,7 +4227,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3714,12 +4256,12 @@ // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -3769,14 +4311,14 @@ // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done5: @@ -3784,17 +4326,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3831,12 +4373,12 @@ // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -3898,14 +4440,14 @@ // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done7: @@ -3913,17 +4455,17 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3936,7 +4478,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3945,7 +4487,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3957,7 +4499,7 @@ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3965,6 +4507,536 @@ // CHECK15-NEXT: ret void // // +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 +// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK16-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK16: arrayctor.loop: +// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK16: arrayctor.cont: +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !7 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK16-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK16: .omp.final.then: +// CHECK16-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK16: .omp.final.done: +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK16-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done3: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK16-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK16: arrayctor.loop: +// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 +// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK16: arrayctor.cont: +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK16-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* +// CHECK16-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !11 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] +// CHECK16-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK16-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK16-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK16: .omp.final.then: +// CHECK16-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK16: .omp.final.done: +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done6: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 +// CHECK16-SAME: () #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK16: arrayctor.loop: +// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK16: arrayctor.cont: +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !16 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK16-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK16: .omp.final.then: +// CHECK16-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK16: .omp.final.done: +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done5: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 +// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK16: arrayctor.loop: +// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 +// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK16: arrayctor.cont: +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 +// CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK16: cond.true: +// CHECK16-NEXT: br label [[COND_END:%.*]] +// CHECK16: cond.false: +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: br label [[COND_END]] +// CHECK16: cond.end: +// CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK16: omp.inner.for.cond: +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK16: omp.inner.for.cond.cleanup: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK16: omp.inner.for.body: +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] +// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK16-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* +// CHECK16-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !19 +// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK16: omp.body.continue: +// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK16: omp.inner.for.inc: +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK16: omp.inner.for.end: +// CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK16: omp.loop.exit: +// CHECK16-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK16-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 +// CHECK16-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK16: .omp.final.then: +// CHECK16-NEXT: store i32 2, i32* [[I]], align 4 +// CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK16: .omp.final.done: +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 +// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK16: arraydestroy.body: +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK16: arraydestroy.done7: +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float +// CHECK16-NEXT: store float [[CONV]], float* [[F]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 +// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 +// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 +// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK16-NEXT: ret void +// +// +// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-NEXT: entry: +// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 +// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 +// CHECK16-NEXT: ret void +// +// // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -3973,7 +5045,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4047,7 +5119,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4120,7 +5192,7 @@ // CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !9 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9 +// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp @@ -9896,7 +9896,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -9921,7 +9921,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9991,7 +9991,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -10006,7 +10006,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10081,7 +10081,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10104,7 +10104,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10185,7 +10185,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -10224,7 +10224,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10356,7 +10356,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -10398,7 +10398,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10538,7 +10538,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -10565,7 +10565,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10661,7 +10661,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10687,7 +10687,7 @@ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10774,8 +10774,887 @@ // CHECK17-NEXT: ret void // // +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 +// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK18-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK18-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21 +// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK18-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK18-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0 +// CHECK18-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK18-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double +// CHECK18-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK18-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK18-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK18-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[CONV11:%.*]] = fpext float [[TMP18]] to double +// CHECK18-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK18-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK18-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 +// CHECK18-NEXT: [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 +// CHECK18-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK18-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]] +// CHECK18-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3 +// CHECK18-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 +// CHECK18-NEXT: [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00 +// CHECK18-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 +// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24 +// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1 +// CHECK18-NEXT: store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24 +// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24 +// CHECK18-NEXT: [[CONV21:%.*]] = sext i8 [[TMP23]] to i32 +// CHECK18-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK18-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK18-NEXT: store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK18-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) +// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK18-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK18-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK18-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK18-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK18-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK18: omp.precond.then: +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK18-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK18-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK18-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK18-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27 +// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27 +// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27 +// CHECK18-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK18-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK18-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK18-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK18-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]] +// CHECK18-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 +// CHECK18-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 +// CHECK18-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 +// CHECK18-NEXT: [[MUL26:%.*]] = mul i32 [[DIV25]], 1 +// CHECK18-NEXT: [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]] +// CHECK18-NEXT: store i32 [[ADD27]], i32* [[I8]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: br label [[OMP_PRECOND_END]] +// CHECK18: omp.precond.end: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 +// CHECK18-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30 +// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK18-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !30 +// CHECK18-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !30 +// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK18-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !30 +// CHECK18-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK18-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] +// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK18-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !30 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK18-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK18: cond.true: +// CHECK18-NEXT: br label [[COND_END:%.*]] +// CHECK18: cond.false: +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: br label [[COND_END]] +// CHECK18: cond.end: +// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK18: omp.inner.for.cond: +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK18: omp.inner.for.body: +// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33 +// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33 +// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK18: omp.body.continue: +// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK18: omp.inner.for.inc: +// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK18: omp.inner.for.end: +// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK18: omp.loop.exit: +// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK18-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK18: .omp.final.then: +// CHECK18-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK18: .omp.final.done: +// CHECK18-NEXT: ret void +// +// // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -10798,7 +11677,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10868,7 +11747,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -10883,7 +11762,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10958,7 +11837,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10979,7 +11858,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11059,7 +11938,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -11096,7 +11975,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11227,7 +12106,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -11265,7 +12144,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11403,7 +12282,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -11428,7 +12307,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11523,7 +12402,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11547,7 +12426,7 @@ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11633,8 +12512,867 @@ // CHECK19-NEXT: ret void // // +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 +// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK20-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19 +// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK20-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22 +// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK20-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK20-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double +// CHECK20-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK20-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float +// CHECK20-NEXT: store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK20-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double +// CHECK20-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 +// CHECK20-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float +// CHECK20-NEXT: store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25 +// CHECK20-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25 +// CHECK20-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK20-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]] +// CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3 +// CHECK20-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25 +// CHECK20-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 +// CHECK20-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25 +// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 +// CHECK20-NEXT: store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 +// CHECK20-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 +// CHECK20-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 +// CHECK20-NEXT: store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK20-NEXT: store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) +// CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK20-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK20-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK20-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK20-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK20-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK20: omp.precond.then: +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK20-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK20-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK20-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK20-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK20-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28 +// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28 +// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28 +// CHECK20-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK20-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK20-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK20-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK20-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK20-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]] +// CHECK20-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1 +// CHECK20-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1 +// CHECK20-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1 +// CHECK20-NEXT: [[MUL24:%.*]] = mul i32 [[DIV23]], 1 +// CHECK20-NEXT: [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]] +// CHECK20-NEXT: store i32 [[ADD25]], i32* [[I6]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: br label [[OMP_PRECOND_END]] +// CHECK20: omp.precond.end: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double +// CHECK20-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 +// CHECK20-NEXT: store double [[INC]], double* [[A5]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] +// CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK20-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !31 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK20-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK20: cond.true: +// CHECK20-NEXT: br label [[COND_END:%.*]] +// CHECK20: cond.false: +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: br label [[COND_END]] +// CHECK20: cond.end: +// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK20: omp.inner.for.cond: +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK20: omp.inner.for.body: +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34 +// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34 +// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK20: omp.body.continue: +// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK20: omp.inner.for.inc: +// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK20: omp.inner.for.end: +// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK20: omp.loop.exit: +// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK20: .omp.final.then: +// CHECK20-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK20: .omp.final.done: +// CHECK20-NEXT: ret void +// +// // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK21-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -11659,7 +13397,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11729,7 +13467,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK21-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -11744,7 +13482,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11819,7 +13557,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -11842,7 +13580,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11923,7 +13661,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK21-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -11962,7 +13700,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12094,7 +13832,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -12136,7 +13874,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12276,7 +14014,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK21-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -12313,7 +14051,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12454,7 +14192,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -12480,7 +14218,7 @@ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12567,8 +14305,942 @@ // CHECK21-NEXT: ret void // // +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 +// CHECK22-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 +// CHECK22-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK22-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK22-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK22-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK22-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK22-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18 +// CHECK22-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK22-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK22-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK22-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK22-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 +// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21 +// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21 +// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21 +// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK22-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK22-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK22-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK22-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK22-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK22-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 +// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 +// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 +// CHECK22-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 +// CHECK22-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 +// CHECK22-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 +// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 +// CHECK22-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0 +// CHECK22-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK22-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK22-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 +// CHECK22-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double +// CHECK22-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 +// CHECK22-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float +// CHECK22-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 +// CHECK22-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[CONV11:%.*]] = fpext float [[TMP18]] to double +// CHECK22-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 +// CHECK22-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float +// CHECK22-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 +// CHECK22-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2 +// CHECK22-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 +// CHECK22-NEXT: [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00 +// CHECK22-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 +// CHECK22-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK22-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]] +// CHECK22-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3 +// CHECK22-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 +// CHECK22-NEXT: [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00 +// CHECK22-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 +// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK22-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24 +// CHECK22-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1 +// CHECK22-NEXT: store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24 +// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK22-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24 +// CHECK22-NEXT: [[CONV21:%.*]] = sext i8 [[TMP23]] to i32 +// CHECK22-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 +// CHECK22-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 +// CHECK22-NEXT: store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK22-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) +// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK22-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 +// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK22-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK22-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 +// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* +// CHECK22-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 +// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I8:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 +// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK22-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK22-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK22-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 +// CHECK22-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 +// CHECK22-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK22-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 +// CHECK22-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK22-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK22-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK22: omp.precond.then: +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK22-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK22-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 +// CHECK22-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] +// CHECK22-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK22-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK22-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK22-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27 +// CHECK22-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 +// CHECK22-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 +// CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27 +// CHECK22-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27 +// CHECK22-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK22-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 +// CHECK22-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 +// CHECK22-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27 +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK22-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 +// CHECK22-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK22-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK22-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK22-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK22-NEXT: [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]] +// CHECK22-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 +// CHECK22-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 +// CHECK22-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 +// CHECK22-NEXT: [[MUL26:%.*]] = mul i32 [[DIV25]], 1 +// CHECK22-NEXT: [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]] +// CHECK22-NEXT: store i32 [[ADD27]], i32* [[I8]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: br label [[OMP_PRECOND_END]] +// CHECK22: omp.precond.end: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 +// CHECK22-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4 +// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK22-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 +// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 +// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK22-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1 +// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 +// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK22: omp_if.then: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 +// CHECK22-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK22-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30 +// CHECK22-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double +// CHECK22-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00 +// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK22-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !30 +// CHECK22-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK22-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !30 +// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 +// CHECK22-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !30 +// CHECK22-NEXT: [[CONV8:%.*]] = fptosi double [[INC]] to i16 +// CHECK22-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]] +// CHECK22-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK22-NEXT: store i16 [[CONV8]], i16* [[ARRAYIDX9]], align 2, !llvm.access.group !30 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK22-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK22: omp_if.else: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND11:%.*]] +// CHECK22: omp.inner.for.cond11: +// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK22-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]] +// CHECK22: omp.inner.for.body13: +// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] +// CHECK22-NEXT: store i32 [[ADD15]], i32* [[I]], align 4 +// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double +// CHECK22-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00 +// CHECK22-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK22-NEXT: store double [[ADD17]], double* [[A18]], align 8 +// CHECK22-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK22-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8 +// CHECK22-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00 +// CHECK22-NEXT: store double [[INC20]], double* [[A19]], align 8 +// CHECK22-NEXT: [[CONV21:%.*]] = fptosi double [[INC20]] to i16 +// CHECK22-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK22-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP22]] +// CHECK22-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX22]], i64 1 +// CHECK22-NEXT: store i16 [[CONV21]], i16* [[ARRAYIDX23]], align 2 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE24:%.*]] +// CHECK22: omp.body.continue24: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC25:%.*]] +// CHECK22: omp.inner.for.inc25: +// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK22-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP33:![0-9]+]] +// CHECK22: omp.inner.for.end27: +// CHECK22-NEXT: br label [[OMP_IF_END]] +// CHECK22: omp_if.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK22-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 +// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* +// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 +// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK22-NEXT: ret void +// +// +// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK22-NEXT: entry: +// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 +// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* +// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK22: cond.true: +// CHECK22-NEXT: br label [[COND_END:%.*]] +// CHECK22: cond.false: +// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: br label [[COND_END]] +// CHECK22: cond.end: +// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK22-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK22: omp.inner.for.cond: +// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK22: omp.inner.for.body: +// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !35 +// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 +// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 +// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !35 +// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 +// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK22-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK22: omp.body.continue: +// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK22: omp.inner.for.inc: +// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK22-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] +// CHECK22: omp.inner.for.end: +// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK22: omp.loop.exit: +// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK22-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK22-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK22: .omp.final.then: +// CHECK22-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK22: .omp.final.done: +// CHECK22-NEXT: ret void +// +// // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK23-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -12591,7 +15263,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12661,7 +15333,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK23-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -12676,7 +15348,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12751,7 +15423,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -12772,7 +15444,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12852,7 +15524,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK23-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -12889,7 +15561,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13020,7 +15692,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -13058,7 +15730,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13196,7 +15868,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK23-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -13231,7 +15903,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13371,7 +16043,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -13395,7 +16067,7 @@ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13480,3 +16152,5181 @@ // CHECK23: .omp.final.done: // CHECK23-NEXT: ret void // +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 +// CHECK24-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK24-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK24-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 +// CHECK24-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 +// CHECK24-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK24-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19 +// CHECK24-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 +// CHECK24-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 +// CHECK24-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK24-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +// CHECK24-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 +// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 +// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22 +// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 +// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK24-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK24-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 +// CHECK24-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK24-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK24-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK24-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK24-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 +// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 +// CHECK24-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 +// CHECK24-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 +// CHECK24-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 +// CHECK24-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 +// CHECK24-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0 +// CHECK24-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK24-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 +// CHECK24-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double +// CHECK24-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 +// CHECK24-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float +// CHECK24-NEXT: store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 +// CHECK24-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double +// CHECK24-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 +// CHECK24-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float +// CHECK24-NEXT: store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 +// CHECK24-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 +// CHECK24-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25 +// CHECK24-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 +// CHECK24-NEXT: store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25 +// CHECK24-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK24-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]] +// CHECK24-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3 +// CHECK24-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25 +// CHECK24-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 +// CHECK24-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25 +// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 +// CHECK24-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 +// CHECK24-NEXT: store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 +// CHECK24-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 +// CHECK24-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 +// CHECK24-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 +// CHECK24-NEXT: store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK24-NEXT: store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) +// CHECK24-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK24-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK24-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK24-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 +// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* +// CHECK24-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I6:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 +// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK24-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] +// CHECK24-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 +// CHECK24-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 +// CHECK24-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK24-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 +// CHECK24-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK24-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK24-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK24: omp.precond.then: +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK24-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] +// CHECK24-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 +// CHECK24-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] +// CHECK24-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 +// CHECK24-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] +// CHECK24-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK24-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28 +// CHECK24-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 +// CHECK24-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK24-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 +// CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28 +// CHECK24-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28 +// CHECK24-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 +// CHECK24-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 +// CHECK24-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 +// CHECK24-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28 +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK24-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 +// CHECK24-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) +// CHECK24-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK24-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK24-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK24-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK24-NEXT: [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]] +// CHECK24-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1 +// CHECK24-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1 +// CHECK24-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1 +// CHECK24-NEXT: [[MUL24:%.*]] = mul i32 [[DIV23]], 1 +// CHECK24-NEXT: [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]] +// CHECK24-NEXT: store i32 [[ADD25]], i32* [[I6]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: br label [[OMP_PRECOND_END]] +// CHECK24: omp.precond.end: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 +// CHECK24-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK24-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* +// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 +// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK24-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1 +// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 +// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK24: omp_if.then: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK24-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double +// CHECK24-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 +// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK24-NEXT: store double [[ADD5]], double* [[A]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK24-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 +// CHECK24-NEXT: store double [[INC]], double* [[A6]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 +// CHECK24-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]] +// CHECK24-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK24-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !31 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK24-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK24: omp_if.else: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] +// CHECK24: omp.inner.for.cond10: +// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// CHECK24-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END26:%.*]] +// CHECK24: omp.inner.for.body12: +// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP19]], 1 +// CHECK24-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK24-NEXT: store i32 [[ADD14]], i32* [[I]], align 4 +// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV15:%.*]] = sitofp i32 [[TMP20]] to double +// CHECK24-NEXT: [[ADD16:%.*]] = fadd double [[CONV15]], 1.500000e+00 +// CHECK24-NEXT: [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK24-NEXT: store double [[ADD16]], double* [[A17]], align 4 +// CHECK24-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK24-NEXT: [[TMP21:%.*]] = load double, double* [[A18]], align 4 +// CHECK24-NEXT: [[INC19:%.*]] = fadd double [[TMP21]], 1.000000e+00 +// CHECK24-NEXT: store double [[INC19]], double* [[A18]], align 4 +// CHECK24-NEXT: [[CONV20:%.*]] = fptosi double [[INC19]] to i16 +// CHECK24-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP22]] +// CHECK24-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX21]], i32 1 +// CHECK24-NEXT: store i16 [[CONV20]], i16* [[ARRAYIDX22]], align 2 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE23:%.*]] +// CHECK24: omp.body.continue23: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC24:%.*]] +// CHECK24: omp.inner.for.inc24: +// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK24-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK24: omp.inner.for.end26: +// CHECK24-NEXT: br label [[OMP_IF_END]] +// CHECK24: omp_if.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) +// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK24-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* +// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 +// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) +// CHECK24-NEXT: ret void +// +// +// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK24-NEXT: entry: +// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 +// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* +// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 +// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 +// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK24: cond.true: +// CHECK24-NEXT: br label [[COND_END:%.*]] +// CHECK24: cond.false: +// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: br label [[COND_END]] +// CHECK24: cond.end: +// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 +// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK24: omp.inner.for.cond: +// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK24: omp.inner.for.body: +// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 +// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !36 +// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 +// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 +// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 +// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !36 +// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 +// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK24: omp.body.continue: +// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK24: omp.inner.for.inc: +// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK24-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 +// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK24: omp.inner.for.end: +// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK24: omp.loop.exit: +// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 +// CHECK24-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +// CHECK24-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK24: .omp.final.then: +// CHECK24-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK24: .omp.final.done: +// CHECK24-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK25-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK25-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK25-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A8:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A9:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I40:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I58:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK25-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK25-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK25-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 +// CHECK25-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK25-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 +// CHECK25-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK25-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 +// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 +// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4 +// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] +// CHECK25: omp.inner.for.cond10: +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 +// CHECK25-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK25-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK25: omp.inner.for.body12: +// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK25-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK25-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK25-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4 +// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[A8]], align 4 +// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK25-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK25: omp.body.continue16: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK25: omp.inner.for.inc17: +// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK25-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK25: omp.inner.for.end19: +// CHECK25-NEXT: store i32 10, i32* [[A]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 +// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK25-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] +// CHECK25: omp.inner.for.cond25: +// CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] +// CHECK25-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] +// CHECK25: omp.inner.for.body27: +// CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK25-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] +// CHECK25-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK25-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 +// CHECK25-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK25-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 +// CHECK25-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] +// CHECK25: omp.body.continue32: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] +// CHECK25: omp.inner.for.inc33: +// CHECK25-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1 +// CHECK25-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK25: omp.inner.for.end35: +// CHECK25-NEXT: store i32 10, i32* [[I24]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 +// CHECK25-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 +// CHECK25-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] +// CHECK25: omp.inner.for.cond41: +// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]] +// CHECK25-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] +// CHECK25: omp.inner.for.body43: +// CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1 +// CHECK25-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] +// CHECK25-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK25-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK25-NEXT: [[CONV47:%.*]] = sext i16 [[TMP31]] to i32 +// CHECK25-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 +// CHECK25-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 +// CHECK25-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] +// CHECK25: omp.body.continue50: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] +// CHECK25: omp.inner.for.inc51: +// CHECK25-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK25-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK25: omp.inner.for.end53: +// CHECK25-NEXT: store i32 10, i32* [[I40]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 +// CHECK25-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 +// CHECK25-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4 +// CHECK25-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0 +// CHECK25-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] +// CHECK25: omp.inner.for.cond59: +// CHECK25-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]] +// CHECK25-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] +// CHECK25: omp.inner.for.body61: +// CHECK25-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK25-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] +// CHECK25-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1 +// CHECK25-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double +// CHECK25-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 +// CHECK25-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float +// CHECK25-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 +// CHECK25-NEXT: [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[CONV69:%.*]] = fpext float [[TMP39]] to double +// CHECK25-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 +// CHECK25-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float +// CHECK25-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 +// CHECK25-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]] +// CHECK25-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]] +// CHECK25-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3 +// CHECK25-NEXT: [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00 +// CHECK25-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1 +// CHECK25-NEXT: store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK25-NEXT: [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: [[CONV79:%.*]] = sext i8 [[TMP44]] to i32 +// CHECK25-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 +// CHECK25-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 +// CHECK25-NEXT: store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] +// CHECK25: omp.body.continue82: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] +// CHECK25: omp.inner.for.inc83: +// CHECK25-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1 +// CHECK25-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK25: omp.inner.for.end85: +// CHECK25-NEXT: store i32 10, i32* [[I58]], align 4 +// CHECK25-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP47]]) +// CHECK25-NEXT: ret i32 [[TMP46]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z3bari +// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK25-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK25-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK25-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: ret i32 [[TMP8]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK25-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK25-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK25-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK25-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK25-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK25-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK25-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18 +// CHECK25-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double +// CHECK25-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD3]], double* [[A]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP10:%.*]] = load double, double* [[A4]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 +// CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8, !llvm.access.group !18 +// CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK25-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]] +// CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK25-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] +// CHECK25-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i64 1 +// CHECK25-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2 +// CHECK25-NEXT: [[CONV10:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4 +// CHECK25-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]] +// CHECK25-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) +// CHECK25-NEXT: ret i32 [[ADD11]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK25-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK25-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] +// CHECK25-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 +// CHECK25-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK25-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// CHECK25-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK25-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK25: simd.if.then: +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 +// CHECK25-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] +// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 +// CHECK25-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] +// CHECK25-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK25-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21 +// CHECK25-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK25-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK25-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 +// CHECK25-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !21 +// CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !21 +// CHECK25-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK25-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK25-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 +// CHECK25-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !21 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK25-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 +// CHECK25-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK25-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] +// CHECK25-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK25-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 +// CHECK25-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 +// CHECK25-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 +// CHECK25-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] +// CHECK25-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 +// CHECK25-NEXT: br label [[SIMD_IF_END]] +// CHECK25: simd.if.end: +// CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: ret i32 [[TMP21]] +// +// +// CHECK25-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK25-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK25-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK25: omp.inner.for.cond: +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK25: omp.inner.for.body: +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK25-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK25-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK25-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK25-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK25: omp.body.continue: +// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK25: omp.inner.for.inc: +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK25-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK25: omp.inner.for.end: +// CHECK25-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK25-NEXT: ret i32 [[TMP8]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK26-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK26-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK26-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A8:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A9:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I40:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I58:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK26-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK26-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK26-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 +// CHECK26-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// CHECK26-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK26-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 +// CHECK26-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK26-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 +// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 +// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4 +// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] +// CHECK26: omp.inner.for.cond10: +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 +// CHECK26-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK26-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK26: omp.inner.for.body12: +// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK26-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK26-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK26-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4 +// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[A8]], align 4 +// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK26-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK26: omp.body.continue16: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK26: omp.inner.for.inc17: +// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK26-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK26: omp.inner.for.end19: +// CHECK26-NEXT: store i32 10, i32* [[A]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 +// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK26-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] +// CHECK26: omp.inner.for.cond25: +// CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] +// CHECK26-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] +// CHECK26: omp.inner.for.body27: +// CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK26-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] +// CHECK26-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK26-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 +// CHECK26-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK26-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 +// CHECK26-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !9 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] +// CHECK26: omp.body.continue32: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] +// CHECK26: omp.inner.for.inc33: +// CHECK26-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1 +// CHECK26-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK26: omp.inner.for.end35: +// CHECK26-NEXT: store i32 10, i32* [[I24]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 +// CHECK26-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 +// CHECK26-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] +// CHECK26: omp.inner.for.cond41: +// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]] +// CHECK26-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] +// CHECK26: omp.inner.for.body43: +// CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1 +// CHECK26-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] +// CHECK26-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK26-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK26-NEXT: [[CONV47:%.*]] = sext i16 [[TMP31]] to i32 +// CHECK26-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 +// CHECK26-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 +// CHECK26-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !12 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] +// CHECK26: omp.body.continue50: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] +// CHECK26: omp.inner.for.inc51: +// CHECK26-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK26-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK26: omp.inner.for.end53: +// CHECK26-NEXT: store i32 10, i32* [[I40]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 +// CHECK26-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 +// CHECK26-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4 +// CHECK26-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0 +// CHECK26-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] +// CHECK26: omp.inner.for.cond59: +// CHECK26-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]] +// CHECK26-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] +// CHECK26: omp.inner.for.body61: +// CHECK26-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK26-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] +// CHECK26-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1 +// CHECK26-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double +// CHECK26-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 +// CHECK26-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float +// CHECK26-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 +// CHECK26-NEXT: [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[CONV69:%.*]] = fpext float [[TMP39]] to double +// CHECK26-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 +// CHECK26-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float +// CHECK26-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 +// CHECK26-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]] +// CHECK26-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]] +// CHECK26-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3 +// CHECK26-NEXT: [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00 +// CHECK26-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1 +// CHECK26-NEXT: store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK26-NEXT: [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: [[CONV79:%.*]] = sext i8 [[TMP44]] to i32 +// CHECK26-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 +// CHECK26-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 +// CHECK26-NEXT: store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !15 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] +// CHECK26: omp.body.continue82: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] +// CHECK26: omp.inner.for.inc83: +// CHECK26-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1 +// CHECK26-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK26: omp.inner.for.end85: +// CHECK26-NEXT: store i32 10, i32* [[I58]], align 4 +// CHECK26-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP47]]) +// CHECK26-NEXT: ret i32 [[TMP46]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z3bari +// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK26-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK26-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK26-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: ret i32 [[TMP8]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK26-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK26-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK26-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK26-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK26-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK26-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK26-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18 +// CHECK26-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double +// CHECK26-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD3]], double* [[A]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK26-NEXT: [[TMP10:%.*]] = load double, double* [[A4]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 +// CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8, !llvm.access.group !18 +// CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK26-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]] +// CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK26-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] +// CHECK26-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i64 1 +// CHECK26-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2 +// CHECK26-NEXT: [[CONV10:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4 +// CHECK26-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]] +// CHECK26-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) +// CHECK26-NEXT: ret i32 [[ADD11]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK26-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK26-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] +// CHECK26-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 +// CHECK26-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK26-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// CHECK26-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK26-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK26-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK26: simd.if.then: +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 +// CHECK26-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] +// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 +// CHECK26-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] +// CHECK26-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK26-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21 +// CHECK26-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK26-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK26-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 +// CHECK26-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !21 +// CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !21 +// CHECK26-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK26-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK26-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 +// CHECK26-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !21 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK26-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 +// CHECK26-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK26-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] +// CHECK26-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK26-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 +// CHECK26-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 +// CHECK26-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 +// CHECK26-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] +// CHECK26-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 +// CHECK26-NEXT: br label [[SIMD_IF_END]] +// CHECK26: simd.if.end: +// CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: ret i32 [[TMP21]] +// +// +// CHECK26-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK26-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK26-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK26: omp.inner.for.cond: +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK26: omp.inner.for.body: +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK26-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK26-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK26-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK26-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK26: omp.body.continue: +// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK26: omp.inner.for.inc: +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK26-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK26: omp.inner.for.end: +// CHECK26-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK26-NEXT: ret i32 [[TMP8]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK27-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK27-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK27-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A8:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A9:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I40:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I58:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK27-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK27-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK27-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 +// CHECK27-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK27-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 +// CHECK27-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4 +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] +// CHECK27: omp.inner.for.cond10: +// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 +// CHECK27-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK27-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK27: omp.inner.for.body12: +// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK27-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK27-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK27-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4 +// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[A8]], align 4 +// CHECK27-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK27-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK27: omp.body.continue16: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK27: omp.inner.for.inc17: +// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK27-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK27-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK27: omp.inner.for.end19: +// CHECK27-NEXT: store i32 10, i32* [[A]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 +// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK27-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] +// CHECK27: omp.inner.for.cond25: +// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK27-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] +// CHECK27: omp.inner.for.body27: +// CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK27-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] +// CHECK27-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK27-NEXT: [[CONV:%.*]] = sext i16 [[TMP22]] to i32 +// CHECK27-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK27-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 +// CHECK27-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] +// CHECK27: omp.body.continue32: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] +// CHECK27: omp.inner.for.inc33: +// CHECK27-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK27-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK27: omp.inner.for.end35: +// CHECK27-NEXT: store i32 10, i32* [[I24]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 +// CHECK27-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 +// CHECK27-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] +// CHECK27: omp.inner.for.cond41: +// CHECK27-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]] +// CHECK27-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] +// CHECK27: omp.inner.for.body43: +// CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1 +// CHECK27-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] +// CHECK27-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK27-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK27-NEXT: [[CONV47:%.*]] = sext i16 [[TMP29]] to i32 +// CHECK27-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 +// CHECK27-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 +// CHECK27-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] +// CHECK27: omp.body.continue50: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] +// CHECK27: omp.inner.for.inc51: +// CHECK27-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK27-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK27: omp.inner.for.end53: +// CHECK27-NEXT: store i32 10, i32* [[I40]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 +// CHECK27-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 +// CHECK27-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4 +// CHECK27-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0 +// CHECK27-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] +// CHECK27: omp.inner.for.cond59: +// CHECK27-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] +// CHECK27-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] +// CHECK27: omp.inner.for.body61: +// CHECK27-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1 +// CHECK27-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] +// CHECK27-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK27-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double +// CHECK27-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 +// CHECK27-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float +// CHECK27-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 +// CHECK27-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[CONV69:%.*]] = fpext float [[TMP37]] to double +// CHECK27-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 +// CHECK27-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float +// CHECK27-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 +// CHECK27-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK27-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]] +// CHECK27-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3 +// CHECK27-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00 +// CHECK27-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 +// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1 +// CHECK27-NEXT: store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK27-NEXT: [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[CONV79:%.*]] = sext i8 [[TMP42]] to i32 +// CHECK27-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 +// CHECK27-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 +// CHECK27-NEXT: store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] +// CHECK27: omp.body.continue82: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] +// CHECK27: omp.inner.for.inc83: +// CHECK27-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1 +// CHECK27-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK27: omp.inner.for.end85: +// CHECK27-NEXT: store i32 10, i32* [[I58]], align 4 +// CHECK27-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK27-NEXT: ret i32 [[TMP44]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z3bari +// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK27-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK27-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: ret i32 [[TMP8]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK27-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK27-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK27-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK27-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// CHECK27-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD3]], double* [[A]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP9:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// CHECK27-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK27-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]] +// CHECK27-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK27-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK27-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] +// CHECK27-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i32 1 +// CHECK27-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2 +// CHECK27-NEXT: [[CONV10:%.*]] = sext i16 [[TMP13]] to i32 +// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4 +// CHECK27-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]] +// CHECK27-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) +// CHECK27-NEXT: ret i32 [[ADD11]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK27-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK27-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] +// CHECK27-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 +// CHECK27-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK27-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// CHECK27-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK27-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK27-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK27: simd.if.then: +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 +// CHECK27-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] +// CHECK27-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 +// CHECK27-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] +// CHECK27-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK27-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22 +// CHECK27-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK27-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK27-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 +// CHECK27-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !22 +// CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !22 +// CHECK27-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 +// CHECK27-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !22 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK27-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 +// CHECK27-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK27-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] +// CHECK27-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK27-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 +// CHECK27-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 +// CHECK27-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 +// CHECK27-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] +// CHECK27-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 +// CHECK27-NEXT: br label [[SIMD_IF_END]] +// CHECK27: simd.if.end: +// CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: ret i32 [[TMP21]] +// +// +// CHECK27-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK27-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK27-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK27: omp.inner.for.cond: +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK27: omp.inner.for.body: +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK27-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK27-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK27-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK27: omp.body.continue: +// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK27: omp.inner.for.inc: +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK27-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK27: omp.inner.for.end: +// CHECK27-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK27-NEXT: ret i32 [[TMP8]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK28-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK28-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK28-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A8:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A9:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I40:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I58:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK28-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK28-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK28-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 +// CHECK28-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK28-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 +// CHECK28-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4 +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] +// CHECK28: omp.inner.for.cond10: +// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 +// CHECK28-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK28-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK28: omp.inner.for.body12: +// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK28-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK28-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK28-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4 +// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[A8]], align 4 +// CHECK28-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK28-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK28: omp.body.continue16: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK28: omp.inner.for.inc17: +// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK28-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK28-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK28: omp.inner.for.end19: +// CHECK28-NEXT: store i32 10, i32* [[A]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 +// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK28-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] +// CHECK28: omp.inner.for.cond25: +// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK28-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] +// CHECK28: omp.inner.for.body27: +// CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK28-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] +// CHECK28-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK28-NEXT: [[CONV:%.*]] = sext i16 [[TMP22]] to i32 +// CHECK28-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK28-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 +// CHECK28-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] +// CHECK28: omp.body.continue32: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] +// CHECK28: omp.inner.for.inc33: +// CHECK28-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK28-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK28: omp.inner.for.end35: +// CHECK28-NEXT: store i32 10, i32* [[I24]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 +// CHECK28-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 +// CHECK28-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] +// CHECK28: omp.inner.for.cond41: +// CHECK28-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]] +// CHECK28-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] +// CHECK28: omp.inner.for.body43: +// CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1 +// CHECK28-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] +// CHECK28-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK28-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK28-NEXT: [[CONV47:%.*]] = sext i16 [[TMP29]] to i32 +// CHECK28-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 +// CHECK28-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 +// CHECK28-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] +// CHECK28: omp.body.continue50: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] +// CHECK28: omp.inner.for.inc51: +// CHECK28-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK28-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK28: omp.inner.for.end53: +// CHECK28-NEXT: store i32 10, i32* [[I40]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 +// CHECK28-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 +// CHECK28-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4 +// CHECK28-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0 +// CHECK28-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] +// CHECK28: omp.inner.for.cond59: +// CHECK28-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] +// CHECK28-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] +// CHECK28: omp.inner.for.body61: +// CHECK28-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1 +// CHECK28-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] +// CHECK28-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK28-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double +// CHECK28-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 +// CHECK28-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float +// CHECK28-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 +// CHECK28-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[CONV69:%.*]] = fpext float [[TMP37]] to double +// CHECK28-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 +// CHECK28-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float +// CHECK28-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 +// CHECK28-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK28-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]] +// CHECK28-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3 +// CHECK28-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00 +// CHECK28-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 +// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1 +// CHECK28-NEXT: store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK28-NEXT: [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[CONV79:%.*]] = sext i8 [[TMP42]] to i32 +// CHECK28-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 +// CHECK28-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 +// CHECK28-NEXT: store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] +// CHECK28: omp.body.continue82: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] +// CHECK28: omp.inner.for.inc83: +// CHECK28-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1 +// CHECK28-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK28: omp.inner.for.end85: +// CHECK28-NEXT: store i32 10, i32* [[I58]], align 4 +// CHECK28-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK28-NEXT: ret i32 [[TMP44]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z3bari +// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK28-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK28-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: ret i32 [[TMP8]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK28-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK28-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK28-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK28-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// CHECK28-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD3]], double* [[A]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK28-NEXT: [[TMP9:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// CHECK28-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK28-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]] +// CHECK28-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK28-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK28-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] +// CHECK28-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i32 1 +// CHECK28-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2 +// CHECK28-NEXT: [[CONV10:%.*]] = sext i16 [[TMP13]] to i32 +// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4 +// CHECK28-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]] +// CHECK28-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) +// CHECK28-NEXT: ret i32 [[ADD11]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK28-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK28-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] +// CHECK28-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 +// CHECK28-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK28-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// CHECK28-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK28-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK28-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK28: simd.if.then: +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 +// CHECK28-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] +// CHECK28-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 +// CHECK28-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] +// CHECK28-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK28-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22 +// CHECK28-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK28-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK28-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 +// CHECK28-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !22 +// CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !22 +// CHECK28-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 +// CHECK28-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !22 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK28-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 +// CHECK28-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK28-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] +// CHECK28-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK28-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 +// CHECK28-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 +// CHECK28-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 +// CHECK28-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] +// CHECK28-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 +// CHECK28-NEXT: br label [[SIMD_IF_END]] +// CHECK28: simd.if.end: +// CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: ret i32 [[TMP21]] +// +// +// CHECK28-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK28-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK28: omp.inner.for.cond: +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK28: omp.inner.for.body: +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK28-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK28-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK28-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK28: omp.body.continue: +// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK28: omp.inner.for.inc: +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK28-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK28: omp.inner.for.end: +// CHECK28-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK28-NEXT: ret i32 [[TMP8]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A8:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A9:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I40:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I58:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 +// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 +// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 +// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK29-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 +// CHECK29-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 +// CHECK29-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 +// CHECK29-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4 +// CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] +// CHECK29: omp.inner.for.cond10: +// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK29-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 +// CHECK29-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK29-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK29: omp.inner.for.body12: +// CHECK29-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK29-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK29-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK29-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !7 +// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !7 +// CHECK29-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK29-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !7 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK29: omp.body.continue16: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK29: omp.inner.for.inc17: +// CHECK29-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK29-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK29-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK29: omp.inner.for.end19: +// CHECK29-NEXT: store i32 10, i32* [[A]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK29-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 +// CHECK29-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK29-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] +// CHECK29: omp.inner.for.cond25: +// CHECK29-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] +// CHECK29-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] +// CHECK29: omp.inner.for.body27: +// CHECK29-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK29-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] +// CHECK29-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 +// CHECK29-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK29-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 +// CHECK29-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] +// CHECK29: omp.body.continue32: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] +// CHECK29: omp.inner.for.inc33: +// CHECK29-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1 +// CHECK29-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK29: omp.inner.for.end35: +// CHECK29-NEXT: store i32 10, i32* [[I24]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 +// CHECK29-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 +// CHECK29-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 +// CHECK29-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] +// CHECK29: omp.inner.for.cond41: +// CHECK29-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]] +// CHECK29-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] +// CHECK29: omp.inner.for.body43: +// CHECK29-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1 +// CHECK29-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] +// CHECK29-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK29-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK29-NEXT: [[CONV47:%.*]] = sext i16 [[TMP31]] to i32 +// CHECK29-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 +// CHECK29-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 +// CHECK29-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] +// CHECK29: omp.body.continue50: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] +// CHECK29: omp.inner.for.inc51: +// CHECK29-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK29-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK29: omp.inner.for.end53: +// CHECK29-NEXT: store i32 10, i32* [[I40]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 +// CHECK29-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 +// CHECK29-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 +// CHECK29-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4 +// CHECK29-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0 +// CHECK29-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] +// CHECK29: omp.inner.for.cond59: +// CHECK29-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]] +// CHECK29-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] +// CHECK29: omp.inner.for.body61: +// CHECK29-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK29-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] +// CHECK29-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1 +// CHECK29-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// CHECK29-NEXT: [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double +// CHECK29-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 +// CHECK29-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float +// CHECK29-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 +// CHECK29-NEXT: [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[CONV69:%.*]] = fpext float [[TMP39]] to double +// CHECK29-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 +// CHECK29-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float +// CHECK29-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 +// CHECK29-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2 +// CHECK29-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 +// CHECK29-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00 +// CHECK29-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 +// CHECK29-NEXT: [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]] +// CHECK29-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]] +// CHECK29-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3 +// CHECK29-NEXT: [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 +// CHECK29-NEXT: [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00 +// CHECK29-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 +// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK29-NEXT: [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !16 +// CHECK29-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1 +// CHECK29-NEXT: store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !16 +// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK29-NEXT: [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !16 +// CHECK29-NEXT: [[CONV79:%.*]] = sext i8 [[TMP44]] to i32 +// CHECK29-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 +// CHECK29-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 +// CHECK29-NEXT: store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !16 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] +// CHECK29: omp.body.continue82: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] +// CHECK29: omp.inner.for.inc83: +// CHECK29-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1 +// CHECK29-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK29: omp.inner.for.end85: +// CHECK29-NEXT: store i32 10, i32* [[I58]], align 4 +// CHECK29-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP47]]) +// CHECK29-NEXT: ret i32 [[TMP46]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z3bari +// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: ret i32 [[TMP8]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK29-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 +// CHECK29-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK29-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK29-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK29-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK29: omp_if.then: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK29-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK29-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]] +// CHECK29-NEXT: store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 +// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double +// CHECK29-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK29-NEXT: store double [[ADD4]], double* [[A]], align 8, !llvm.access.group !19 +// CHECK29-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK29-NEXT: [[TMP12:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !19 +// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 +// CHECK29-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !19 +// CHECK29-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK29-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] +// CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK29-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !19 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK29-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK29-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK29: omp_if.else: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK29: omp.inner.for.cond9: +// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK29-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]] +// CHECK29: omp.inner.for.body11: +// CHECK29-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK29-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK29-NEXT: store i32 [[ADD13]], i32* [[I]], align 4 +// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4 +// CHECK29-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double +// CHECK29-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00 +// CHECK29-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK29-NEXT: store double [[ADD15]], double* [[A16]], align 8 +// CHECK29-NEXT: [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK29-NEXT: [[TMP19:%.*]] = load double, double* [[A17]], align 8 +// CHECK29-NEXT: [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+00 +// CHECK29-NEXT: store double [[INC18]], double* [[A17]], align 8 +// CHECK29-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i16 +// CHECK29-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]] +// CHECK29-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i64 1 +// CHECK29-NEXT: store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]] +// CHECK29: omp.body.continue22: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]] +// CHECK29: omp.inner.for.inc23: +// CHECK29-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK29-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK29: omp.inner.for.end25: +// CHECK29-NEXT: br label [[OMP_IF_END]] +// CHECK29: omp_if.end: +// CHECK29-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK29-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK29-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]] +// CHECK29-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1 +// CHECK29-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2 +// CHECK29-NEXT: [[CONV28:%.*]] = sext i16 [[TMP23]] to i32 +// CHECK29-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4 +// CHECK29-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]] +// CHECK29-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// CHECK29-NEXT: ret i32 [[ADD29]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK29-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] +// CHECK29-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// CHECK29-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 +// CHECK29-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK29-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// CHECK29-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK29-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK29-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK29-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK29: simd.if.then: +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 +// CHECK29-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] +// CHECK29-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 +// CHECK29-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] +// CHECK29-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK29-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK29-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK29-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 +// CHECK29-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK29-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !24 +// CHECK29-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK29-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK29-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 +// CHECK29-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !24 +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK29-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK29-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 +// CHECK29-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK29-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK29-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK29-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] +// CHECK29-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK29-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 +// CHECK29-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 +// CHECK29-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 +// CHECK29-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] +// CHECK29-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 +// CHECK29-NEXT: br label [[SIMD_IF_END]] +// CHECK29: simd.if.end: +// CHECK29-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: ret i32 [[TMP21]] +// +// +// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK29-NEXT: entry: +// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK29: omp.inner.for.cond: +// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK29: omp.inner.for.body: +// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK29-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !27 +// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK29-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK29-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !27 +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK29-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK29: omp.body.continue: +// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK29: omp.inner.for.inc: +// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK29-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK29: omp.inner.for.end: +// CHECK29-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK29-NEXT: ret i32 [[TMP8]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A8:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A9:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I40:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I58:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 +// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 +// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 +// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK30-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 +// CHECK30-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 +// CHECK30-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 +// CHECK30-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4 +// CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] +// CHECK30: omp.inner.for.cond10: +// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK30-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 +// CHECK30-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK30-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK30: omp.inner.for.body12: +// CHECK30-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK30-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK30-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK30-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !7 +// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !7 +// CHECK30-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK30-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !7 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK30: omp.body.continue16: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK30: omp.inner.for.inc17: +// CHECK30-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK30-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK30-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK30: omp.inner.for.end19: +// CHECK30-NEXT: store i32 10, i32* [[A]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK30-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 +// CHECK30-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK30-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] +// CHECK30: omp.inner.for.cond25: +// CHECK30-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] +// CHECK30-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] +// CHECK30: omp.inner.for.body27: +// CHECK30-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK30-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] +// CHECK30-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 +// CHECK30-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK30-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 +// CHECK30-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] +// CHECK30: omp.body.continue32: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] +// CHECK30: omp.inner.for.inc33: +// CHECK30-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1 +// CHECK30-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK30: omp.inner.for.end35: +// CHECK30-NEXT: store i32 10, i32* [[I24]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 +// CHECK30-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 +// CHECK30-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 +// CHECK30-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] +// CHECK30: omp.inner.for.cond41: +// CHECK30-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]] +// CHECK30-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] +// CHECK30: omp.inner.for.body43: +// CHECK30-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1 +// CHECK30-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] +// CHECK30-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK30-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK30-NEXT: [[CONV47:%.*]] = sext i16 [[TMP31]] to i32 +// CHECK30-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 +// CHECK30-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 +// CHECK30-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] +// CHECK30: omp.body.continue50: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] +// CHECK30: omp.inner.for.inc51: +// CHECK30-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK30-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK30: omp.inner.for.end53: +// CHECK30-NEXT: store i32 10, i32* [[I40]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 +// CHECK30-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 +// CHECK30-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 +// CHECK30-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4 +// CHECK30-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0 +// CHECK30-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] +// CHECK30: omp.inner.for.cond59: +// CHECK30-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]] +// CHECK30-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] +// CHECK30: omp.inner.for.body61: +// CHECK30-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK30-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] +// CHECK30-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1 +// CHECK30-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// CHECK30-NEXT: [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double +// CHECK30-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 +// CHECK30-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float +// CHECK30-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 +// CHECK30-NEXT: [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[CONV69:%.*]] = fpext float [[TMP39]] to double +// CHECK30-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 +// CHECK30-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float +// CHECK30-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 +// CHECK30-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2 +// CHECK30-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 +// CHECK30-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00 +// CHECK30-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 +// CHECK30-NEXT: [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]] +// CHECK30-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]] +// CHECK30-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3 +// CHECK30-NEXT: [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 +// CHECK30-NEXT: [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00 +// CHECK30-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 +// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK30-NEXT: [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !16 +// CHECK30-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1 +// CHECK30-NEXT: store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !16 +// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK30-NEXT: [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !16 +// CHECK30-NEXT: [[CONV79:%.*]] = sext i8 [[TMP44]] to i32 +// CHECK30-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 +// CHECK30-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 +// CHECK30-NEXT: store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !16 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] +// CHECK30: omp.body.continue82: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] +// CHECK30: omp.inner.for.inc83: +// CHECK30-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1 +// CHECK30-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK30: omp.inner.for.end85: +// CHECK30-NEXT: store i32 10, i32* [[I58]], align 4 +// CHECK30-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP47]]) +// CHECK30-NEXT: ret i32 [[TMP46]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z3bari +// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: ret i32 [[TMP8]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK30-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() +// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] +// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 +// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 +// CHECK30-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK30-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK30-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK30-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK30: omp_if.then: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK30-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK30-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]] +// CHECK30-NEXT: store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 +// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double +// CHECK30-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK30-NEXT: store double [[ADD4]], double* [[A]], align 8, !llvm.access.group !19 +// CHECK30-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK30-NEXT: [[TMP12:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !19 +// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 +// CHECK30-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !19 +// CHECK30-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK30-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] +// CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 +// CHECK30-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !19 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK30-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK30-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK30: omp_if.else: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK30: omp.inner.for.cond9: +// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK30-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]] +// CHECK30: omp.inner.for.body11: +// CHECK30-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK30-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK30-NEXT: store i32 [[ADD13]], i32* [[I]], align 4 +// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4 +// CHECK30-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double +// CHECK30-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00 +// CHECK30-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK30-NEXT: store double [[ADD15]], double* [[A16]], align 8 +// CHECK30-NEXT: [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK30-NEXT: [[TMP19:%.*]] = load double, double* [[A17]], align 8 +// CHECK30-NEXT: [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+00 +// CHECK30-NEXT: store double [[INC18]], double* [[A17]], align 8 +// CHECK30-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i16 +// CHECK30-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK30-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]] +// CHECK30-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i64 1 +// CHECK30-NEXT: store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]] +// CHECK30: omp.body.continue22: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]] +// CHECK30: omp.inner.for.inc23: +// CHECK30-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK30-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK30: omp.inner.for.end25: +// CHECK30-NEXT: br label [[OMP_IF_END]] +// CHECK30: omp_if.end: +// CHECK30-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK30-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK30-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]] +// CHECK30-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1 +// CHECK30-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2 +// CHECK30-NEXT: [[CONV28:%.*]] = sext i16 [[TMP23]] to i32 +// CHECK30-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4 +// CHECK30-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]] +// CHECK30-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 +// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// CHECK30-NEXT: ret i32 [[ADD29]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK30-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] +// CHECK30-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// CHECK30-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 +// CHECK30-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK30-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// CHECK30-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK30-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK30-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK30-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK30: simd.if.then: +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 +// CHECK30-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] +// CHECK30-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 +// CHECK30-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] +// CHECK30-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK30-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK30-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK30-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 +// CHECK30-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !24 +// CHECK30-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !24 +// CHECK30-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK30-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK30-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 +// CHECK30-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !24 +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK30-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK30-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 +// CHECK30-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK30-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK30-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK30-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] +// CHECK30-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK30-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 +// CHECK30-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 +// CHECK30-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 +// CHECK30-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] +// CHECK30-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 +// CHECK30-NEXT: br label [[SIMD_IF_END]] +// CHECK30: simd.if.end: +// CHECK30-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: ret i32 [[TMP21]] +// +// +// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK30-NEXT: entry: +// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK30: omp.inner.for.cond: +// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK30: omp.inner.for.body: +// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK30-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !27 +// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK30-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK30-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !27 +// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK30-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK30: omp.body.continue: +// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK30: omp.inner.for.inc: +// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK30-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK30: omp.inner.for.end: +// CHECK30-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK30-NEXT: ret i32 [[TMP8]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A8:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A9:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I40:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I58:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 +// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 +// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK31-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 +// CHECK31-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 +// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 +// CHECK31-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4 +// CHECK31-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] +// CHECK31: omp.inner.for.cond10: +// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 +// CHECK31-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK31-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK31: omp.inner.for.body12: +// CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK31-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK31-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK31-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !8 +// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !8 +// CHECK31-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK31-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !8 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK31: omp.body.continue16: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK31: omp.inner.for.inc17: +// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK31-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK31-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK31: omp.inner.for.end19: +// CHECK31-NEXT: store i32 10, i32* [[A]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK31-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 +// CHECK31-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK31-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] +// CHECK31: omp.inner.for.cond25: +// CHECK31-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK31-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] +// CHECK31: omp.inner.for.body27: +// CHECK31-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK31-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] +// CHECK31-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !11 +// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP22]] to i32 +// CHECK31-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK31-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 +// CHECK31-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !11 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] +// CHECK31: omp.body.continue32: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] +// CHECK31: omp.inner.for.inc33: +// CHECK31-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK31-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK31: omp.inner.for.end35: +// CHECK31-NEXT: store i32 10, i32* [[I24]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 +// CHECK31-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 +// CHECK31-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 +// CHECK31-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] +// CHECK31: omp.inner.for.cond41: +// CHECK31-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]] +// CHECK31-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] +// CHECK31: omp.inner.for.body43: +// CHECK31-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1 +// CHECK31-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] +// CHECK31-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK31-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !14 +// CHECK31-NEXT: [[CONV47:%.*]] = sext i16 [[TMP29]] to i32 +// CHECK31-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 +// CHECK31-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 +// CHECK31-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !14 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] +// CHECK31: omp.body.continue50: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] +// CHECK31: omp.inner.for.inc51: +// CHECK31-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK31-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK31: omp.inner.for.end53: +// CHECK31-NEXT: store i32 10, i32* [[I40]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 +// CHECK31-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 +// CHECK31-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 +// CHECK31-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4 +// CHECK31-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0 +// CHECK31-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] +// CHECK31: omp.inner.for.cond59: +// CHECK31-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] +// CHECK31-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] +// CHECK31: omp.inner.for.body61: +// CHECK31-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1 +// CHECK31-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] +// CHECK31-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK31-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK31-NEXT: [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double +// CHECK31-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 +// CHECK31-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float +// CHECK31-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 +// CHECK31-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[CONV69:%.*]] = fpext float [[TMP37]] to double +// CHECK31-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 +// CHECK31-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float +// CHECK31-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 +// CHECK31-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2 +// CHECK31-NEXT: [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !17 +// CHECK31-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00 +// CHECK31-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !17 +// CHECK31-NEXT: [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK31-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]] +// CHECK31-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3 +// CHECK31-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !17 +// CHECK31-NEXT: [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00 +// CHECK31-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !17 +// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK31-NEXT: [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1 +// CHECK31-NEXT: store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK31-NEXT: [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[CONV79:%.*]] = sext i8 [[TMP42]] to i32 +// CHECK31-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 +// CHECK31-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 +// CHECK31-NEXT: store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] +// CHECK31: omp.body.continue82: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] +// CHECK31: omp.inner.for.inc83: +// CHECK31-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1 +// CHECK31-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK31: omp.inner.for.end85: +// CHECK31-NEXT: store i32 10, i32* [[I58]], align 4 +// CHECK31-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK31-NEXT: ret i32 [[TMP44]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z3bari +// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: ret i32 [[TMP8]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK31-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 +// CHECK31-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK31-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK31-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK31-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK31: omp_if.then: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK31-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]] +// CHECK31-NEXT: store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double +// CHECK31-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK31-NEXT: store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK31-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK31-NEXT: store double [[INC]], double* [[A5]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK31-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] +// CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK31-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !20 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK31-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK31: omp_if.else: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK31: omp.inner.for.cond9: +// CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK31-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]] +// CHECK31: omp.inner.for.body11: +// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK31-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK31-NEXT: store i32 [[ADD13]], i32* [[I]], align 4 +// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 +// CHECK31-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double +// CHECK31-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00 +// CHECK31-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK31-NEXT: store double [[ADD15]], double* [[A16]], align 4 +// CHECK31-NEXT: [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK31-NEXT: [[TMP18:%.*]] = load double, double* [[A17]], align 4 +// CHECK31-NEXT: [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+00 +// CHECK31-NEXT: store double [[INC18]], double* [[A17]], align 4 +// CHECK31-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i16 +// CHECK31-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK31-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]] +// CHECK31-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i32 1 +// CHECK31-NEXT: store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]] +// CHECK31: omp.body.continue22: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]] +// CHECK31: omp.inner.for.inc23: +// CHECK31-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK31-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK31: omp.inner.for.end25: +// CHECK31-NEXT: br label [[OMP_IF_END]] +// CHECK31: omp_if.end: +// CHECK31-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK31-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK31-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]] +// CHECK31-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i32 1 +// CHECK31-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2 +// CHECK31-NEXT: [[CONV28:%.*]] = sext i16 [[TMP22]] to i32 +// CHECK31-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4 +// CHECK31-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]] +// CHECK31-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) +// CHECK31-NEXT: ret i32 [[ADD29]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK31-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] +// CHECK31-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// CHECK31-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 +// CHECK31-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK31-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// CHECK31-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK31-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK31-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK31-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK31: simd.if.then: +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 +// CHECK31-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] +// CHECK31-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 +// CHECK31-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] +// CHECK31-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK31-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK31-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK31-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 +// CHECK31-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK31-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !25 +// CHECK31-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK31-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK31-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 +// CHECK31-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !25 +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK31-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 +// CHECK31-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK31-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK31-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK31-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] +// CHECK31-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK31-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 +// CHECK31-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 +// CHECK31-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 +// CHECK31-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] +// CHECK31-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 +// CHECK31-NEXT: br label [[SIMD_IF_END]] +// CHECK31: simd.if.end: +// CHECK31-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: ret i32 [[TMP21]] +// +// +// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK31-NEXT: entry: +// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK31: omp.inner.for.cond: +// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK31: omp.inner.for.body: +// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK31-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !28 +// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK31-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK31-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !28 +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK31-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK31: omp.body.continue: +// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK31: omp.inner.for.inc: +// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK31-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK31: omp.inner.for.end: +// CHECK31-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK31-NEXT: ret i32 [[TMP8]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A8:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A9:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I24:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I40:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I58:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() +// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 +// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 +// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK32-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 +// CHECK32-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 +// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 +// CHECK32-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4 +// CHECK32-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] +// CHECK32: omp.inner.for.cond10: +// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 +// CHECK32-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK32-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] +// CHECK32: omp.inner.for.body12: +// CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK32-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK32-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] +// CHECK32-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !8 +// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !8 +// CHECK32-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK32-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !8 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] +// CHECK32: omp.body.continue16: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] +// CHECK32: omp.inner.for.inc17: +// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 +// CHECK32-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK32-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK32: omp.inner.for.end19: +// CHECK32-NEXT: store i32 10, i32* [[A]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 +// CHECK32-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 +// CHECK32-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 +// CHECK32-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] +// CHECK32: omp.inner.for.cond25: +// CHECK32-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] +// CHECK32-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] +// CHECK32: omp.inner.for.body27: +// CHECK32-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1 +// CHECK32-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] +// CHECK32-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !11 +// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP22]] to i32 +// CHECK32-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK32-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 +// CHECK32-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !11 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] +// CHECK32: omp.body.continue32: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] +// CHECK32: omp.inner.for.inc33: +// CHECK32-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK32-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK32: omp.inner.for.end35: +// CHECK32-NEXT: store i32 10, i32* [[I24]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 +// CHECK32-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 +// CHECK32-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 +// CHECK32-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] +// CHECK32: omp.inner.for.cond41: +// CHECK32-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]] +// CHECK32-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] +// CHECK32: omp.inner.for.body43: +// CHECK32-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1 +// CHECK32-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] +// CHECK32-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1 +// CHECK32-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !14 +// CHECK32-NEXT: [[CONV47:%.*]] = sext i16 [[TMP29]] to i32 +// CHECK32-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 +// CHECK32-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 +// CHECK32-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !14 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] +// CHECK32: omp.body.continue50: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] +// CHECK32: omp.inner.for.inc51: +// CHECK32-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1 +// CHECK32-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK32: omp.inner.for.end53: +// CHECK32-NEXT: store i32 10, i32* [[I40]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 +// CHECK32-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 +// CHECK32-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 +// CHECK32-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4 +// CHECK32-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0 +// CHECK32-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] +// CHECK32: omp.inner.for.cond59: +// CHECK32-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] +// CHECK32-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] +// CHECK32: omp.inner.for.body61: +// CHECK32-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1 +// CHECK32-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] +// CHECK32-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK32-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// CHECK32-NEXT: [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double +// CHECK32-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 +// CHECK32-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float +// CHECK32-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 +// CHECK32-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[CONV69:%.*]] = fpext float [[TMP37]] to double +// CHECK32-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 +// CHECK32-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float +// CHECK32-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 +// CHECK32-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2 +// CHECK32-NEXT: [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !17 +// CHECK32-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00 +// CHECK32-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !17 +// CHECK32-NEXT: [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK32-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]] +// CHECK32-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3 +// CHECK32-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !17 +// CHECK32-NEXT: [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00 +// CHECK32-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !17 +// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 +// CHECK32-NEXT: [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1 +// CHECK32-NEXT: store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 +// CHECK32-NEXT: [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[CONV79:%.*]] = sext i8 [[TMP42]] to i32 +// CHECK32-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 +// CHECK32-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 +// CHECK32-NEXT: store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] +// CHECK32: omp.body.continue82: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] +// CHECK32: omp.inner.for.inc83: +// CHECK32-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1 +// CHECK32-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK32: omp.inner.for.end85: +// CHECK32-NEXT: store i32 10, i32* [[I58]], align 4 +// CHECK32-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) +// CHECK32-NEXT: ret i32 [[TMP44]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z3bari +// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) +// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] +// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: ret i32 [[TMP8]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK32-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 +// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 +// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() +// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] +// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 +// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 +// CHECK32-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 +// CHECK32-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 +// CHECK32-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK32-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK32: omp_if.then: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK32-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]] +// CHECK32-NEXT: store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double +// CHECK32-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK32-NEXT: store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK32-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 +// CHECK32-NEXT: store double [[INC]], double* [[A5]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 +// CHECK32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] +// CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 +// CHECK32-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !20 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK32-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK32: omp_if.else: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] +// CHECK32: omp.inner.for.cond9: +// CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK32-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]] +// CHECK32: omp.inner.for.body11: +// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK32-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK32-NEXT: store i32 [[ADD13]], i32* [[I]], align 4 +// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 +// CHECK32-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double +// CHECK32-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00 +// CHECK32-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK32-NEXT: store double [[ADD15]], double* [[A16]], align 4 +// CHECK32-NEXT: [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK32-NEXT: [[TMP18:%.*]] = load double, double* [[A17]], align 4 +// CHECK32-NEXT: [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+00 +// CHECK32-NEXT: store double [[INC18]], double* [[A17]], align 4 +// CHECK32-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i16 +// CHECK32-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK32-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]] +// CHECK32-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i32 1 +// CHECK32-NEXT: store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]] +// CHECK32: omp.body.continue22: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]] +// CHECK32: omp.inner.for.inc23: +// CHECK32-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK32-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK32: omp.inner.for.end25: +// CHECK32-NEXT: br label [[OMP_IF_END]] +// CHECK32: omp_if.end: +// CHECK32-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK32-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK32-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]] +// CHECK32-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i32 1 +// CHECK32-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2 +// CHECK32-NEXT: [[CONV28:%.*]] = sext i16 [[TMP22]] to i32 +// CHECK32-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4 +// CHECK32-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]] +// CHECK32-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 +// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) +// CHECK32-NEXT: ret i32 [[ADD29]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I5:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK32-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] +// CHECK32-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// CHECK32-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 +// CHECK32-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 +// CHECK32-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// CHECK32-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK32-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK32-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 +// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// CHECK32-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] +// CHECK32: simd.if.then: +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 +// CHECK32-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] +// CHECK32-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 +// CHECK32-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] +// CHECK32-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK32-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 +// CHECK32-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 +// CHECK32-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !25 +// CHECK32-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !25 +// CHECK32-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 +// CHECK32-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 +// CHECK32-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 +// CHECK32-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !25 +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 +// CHECK32-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 +// CHECK32-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK32-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK32-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK32-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] +// CHECK32-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK32-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 +// CHECK32-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 +// CHECK32-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 +// CHECK32-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] +// CHECK32-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 +// CHECK32-NEXT: br label [[SIMD_IF_END]] +// CHECK32: simd.if.end: +// CHECK32-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: ret i32 [[TMP21]] +// +// +// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK32-NEXT: entry: +// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 +// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 +// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 +// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK32: omp.inner.for.cond: +// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] +// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK32: omp.inner.for.body: +// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 +// CHECK32-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !28 +// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 +// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK32-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 +// CHECK32-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !28 +// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK32-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK32: omp.body.continue: +// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK32: omp.inner.for.inc: +// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 +// CHECK32-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK32: omp.inner.for.end: +// CHECK32-NEXT: store i32 10, i32* [[I]], align 4 +// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK32-NEXT: ret i32 [[TMP8]] +// diff --git a/clang/test/OpenMP/target_teams_map_codegen.cpp b/clang/test/OpenMP/target_teams_map_codegen.cpp --- a/clang/test/OpenMP/target_teams_map_codegen.cpp +++ b/clang/test/OpenMP/target_teams_map_codegen.cpp @@ -2263,7 +2263,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2275,7 +2275,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -2298,7 +2298,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]], i64 [[Y:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2314,7 +2314,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -2327,7 +2327,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2381,7 +2381,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2415,7 +2415,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -2430,7 +2430,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2443,7 +2443,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -2458,7 +2458,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2471,7 +2471,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -2486,7 +2486,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2499,7 +2499,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK5-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -2512,7 +2512,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2594,7 +2594,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2629,7 +2629,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK5-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -2642,7 +2642,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2724,7 +2724,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2759,7 +2759,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72 -// CHECK5-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -2772,7 +2772,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2816,7 +2816,7 @@ // CHECK5-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK5-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) #[[ATTR6:[0-9]+]] +// CHECK5-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) #[[ATTR6:[0-9]+]] // CHECK5-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK5: atomic_cont: // CHECK5-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -2828,7 +2828,7 @@ // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK5-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK5-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) #[[ATTR6]] +// CHECK5-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) #[[ATTR6]] // CHECK5-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK5: atomic_exit: // CHECK5-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -2838,7 +2838,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.11 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2862,7 +2862,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74 -// CHECK5-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -2875,7 +2875,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2919,7 +2919,7 @@ // CHECK5-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK5-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) #[[ATTR6]] +// CHECK5-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) #[[ATTR6]] // CHECK5-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK5: atomic_cont: // CHECK5-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -2931,7 +2931,7 @@ // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK5-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK5-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) #[[ATTR6]] +// CHECK5-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) #[[ATTR6]] // CHECK5-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK5: atomic_exit: // CHECK5-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -2941,7 +2941,7 @@ // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.13 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2964,6 +2964,715 @@ // CHECK5-NEXT: ret void // // +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27 +// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[Y:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[X_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[X_CASTED]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[Y_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV1]], align 4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[Y_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP5]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]], i64 [[Y:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[X]], i64* [[X_ADDR]], align 8 +// CHECK6-NEXT: store i64 [[Y]], i64* [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[X_ADDR]] to i32* +// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[Y_ADDR]] to i32* +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[TMP0]], i32* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X1:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[Y2:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x i8*], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 +// CHECK6-NEXT: store i32 0, i32* [[X1]], align 4 +// CHECK6-NEXT: store i32 0, i32* [[Y2]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i32* [[X1]] to i8* +// CHECK6-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i32* [[Y2]] to i8* +// CHECK6-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 2, i64 16, i8* [[TMP8]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP9]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[X1]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[Y2]], align 4 +// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[TMP1]], align 4 +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[X1]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP14]] monotonic, align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[Y2]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP16]] monotonic, align 4 +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [2 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [2 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP5]], i64 0, i64 1 +// CHECK6-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to i32* +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 1 +// CHECK6-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to i32* +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK6-NEXT: store i32 [[ADD2]], i32* [[TMP17]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[X_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[X_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[X]], i64* [[X_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[X_ADDR]] to i32* +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[X_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[X_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[X]], i64* [[X_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[X_ADDR]] to i32* +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[X_CASTED]] to i32* +// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[X_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP2]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i64 [[X]], i64* [[X_ADDR]], align 8 +// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[X_ADDR]] to i32* +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 +// CHECK6-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 +// CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 +// CHECK6-NEXT: store [88 x i32]* [[Y]], [88 x i32]** [[Y_ADDR]], align 8 +// CHECK6-NEXT: store [99 x i32]* [[Z]], [99 x i32]** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [88 x i32]*, [88 x i32]** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [99 x i32]*, [99 x i32]** [[Z_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [88 x i32]*, [99 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), [88 x i32]* [[TMP0]], [99 x i32]* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 +// CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 +// CHECK6-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 +// CHECK6-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 +// CHECK6-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [88 x i32]* [[Y]], [88 x i32]** [[Y_ADDR]], align 8 +// CHECK6-NEXT: store [99 x i32]* [[Z]], [99 x i32]** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [88 x i32]*, [88 x i32]** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [99 x i32]*, [99 x i32]** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = bitcast [88 x i32]* [[Y1]] to i8* +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast [88 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 352, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], [99 x i32]* [[Z2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr i32, i32* [[ARRAY_BEGIN]], i64 99 +// CHECK6-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq i32* [[ARRAY_BEGIN]], [[TMP4]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] +// CHECK6: omp.arrayinit.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] +// CHECK6-NEXT: store i32 0, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] +// CHECK6: omp.arrayinit.done: +// CHECK6-NEXT: [[LHS_BEGIN:%.*]] = bitcast [99 x i32]* [[TMP1]] to i32* +// CHECK6-NEXT: [[RHS_BEGIN:%.*]] = bitcast [99 x i32]* [[Z2]] to i32* +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i32* [[RHS_BEGIN]] to i8* +// CHECK6-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 1, i64 8, i8* [[TMP9]], void (i8*, i8*)* @.omp.reduction.reduction_func.7, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP10]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr i32, i32* [[LHS_BEGIN]], i64 99 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i32* [[LHS_BEGIN]], [[TMP11]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi i32* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP11]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done6: +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr i32, i32* [[LHS_BEGIN]], i64 99 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq i32* [[LHS_BEGIN]], [[TMP14]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] +// CHECK6: omp.arraycpy.body8: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi i32* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi i32* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = atomicrmw add i32* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP15]] monotonic, align 4 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP14]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] +// CHECK6: omp.arraycpy.done14: +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr i32, i32* [[TMP11]], i64 99 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i32* [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done2: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 +// CHECK6-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 +// CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 +// CHECK6-NEXT: store [88 x i32]* [[Y]], [88 x i32]** [[Y_ADDR]], align 8 +// CHECK6-NEXT: store [99 x i32]* [[Z]], [99 x i32]** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [88 x i32]*, [88 x i32]** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [99 x i32]*, [99 x i32]** [[Z_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [88 x i32]*, [99 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [88 x i32]* [[TMP0]], [99 x i32]* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 +// CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 +// CHECK6-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 +// CHECK6-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 +// CHECK6-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store [88 x i32]* [[Y]], [88 x i32]** [[Y_ADDR]], align 8 +// CHECK6-NEXT: store [99 x i32]* [[Z]], [99 x i32]** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load [88 x i32]*, [88 x i32]** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load [99 x i32]*, [99 x i32]** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = bitcast [88 x i32]* [[Y1]] to i8* +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast [88 x i32]* [[TMP0]] to i8* +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 352, i1 false) +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], [99 x i32]* [[Z2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr i32, i32* [[ARRAY_BEGIN]], i64 99 +// CHECK6-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq i32* [[ARRAY_BEGIN]], [[TMP4]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] +// CHECK6: omp.arrayinit.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] +// CHECK6-NEXT: store i32 0, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] +// CHECK6: omp.arrayinit.done: +// CHECK6-NEXT: [[LHS_BEGIN:%.*]] = bitcast [99 x i32]* [[TMP1]] to i32* +// CHECK6-NEXT: [[RHS_BEGIN:%.*]] = bitcast [99 x i32]* [[Z2]] to i32* +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i32* [[RHS_BEGIN]] to i8* +// CHECK6-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 1, i64 8, i8* [[TMP9]], void (i8*, i8*)* @.omp.reduction.reduction_func.9, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP10]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr i32, i32* [[LHS_BEGIN]], i64 99 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i32* [[LHS_BEGIN]], [[TMP11]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi i32* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP11]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done6: +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr i32, i32* [[LHS_BEGIN]], i64 99 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq i32* [[LHS_BEGIN]], [[TMP14]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] +// CHECK6: omp.arraycpy.body8: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi i32* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi i32* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = atomicrmw add i32* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP15]] monotonic, align 4 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP14]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] +// CHECK6: omp.arraycpy.done14: +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr i32, i32* [[TMP11]], i64 99 +// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i32* [[TMP11]], [[TMP12]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK6: omp.arraycpy.body: +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] +// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] +// CHECK6: omp.arraycpy.done2: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72 +// CHECK6-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 +// CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 +// CHECK6-NEXT: store i128* [[Y]], i128** [[Y_ADDR]], align 8 +// CHECK6-NEXT: store i128* [[Z]], i128** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i128*, i128** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i128*, i128** [[Z_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i128*, i128*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i128* [[TMP0]], i128* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 +// CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 +// CHECK6-NEXT: [[Y1:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[X:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[Z2:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i128* [[Y]], i128** [[Y_ADDR]], align 8 +// CHECK6-NEXT: store i128* [[Z]], i128** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i128*, i128** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i128*, i128** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i128, i128* [[TMP0]], align 16 +// CHECK6-NEXT: store i128 [[TMP2]], i128* [[Y1]], align 16 +// CHECK6-NEXT: store i128 0, i128* [[Z2]], align 16 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP4:%.*]] = bitcast i128* [[Z2]] to i8* +// CHECK6-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i64 8, i8* [[TMP7]], void (i8*, i8*)* @.omp.reduction.reduction_func.11, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP8]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP9:%.*]] = load i128, i128* [[TMP1]], align 16 +// CHECK6-NEXT: [[TMP10:%.*]] = load i128, i128* [[Z2]], align 16 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: store i128 [[ADD]], i128* [[TMP1]], align 16 +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* +// CHECK6-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) #[[ATTR6:[0-9]+]] +// CHECK6-NEXT: br label [[ATOMIC_CONT:%.*]] +// CHECK6: atomic_cont: +// CHECK6-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 +// CHECK6-NEXT: store i128 [[TMP14]], i128* [[TMP]], align 16 +// CHECK6-NEXT: [[TMP15:%.*]] = load i128, i128* [[TMP]], align 16 +// CHECK6-NEXT: [[TMP16:%.*]] = load i128, i128* [[Z2]], align 16 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i128 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: store i128 [[ADD4]], i128* [[ATOMIC_TEMP3]], align 16 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* +// CHECK6-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) #[[ATTR6]] +// CHECK6-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] +// CHECK6: atomic_exit: +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.11 +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i128* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i128* +// CHECK6-NEXT: [[TMP12:%.*]] = load i128, i128* [[TMP11]], align 16 +// CHECK6-NEXT: [[TMP13:%.*]] = load i128, i128* [[TMP8]], align 16 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i128 [[ADD]], i128* [[TMP11]], align 16 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74 +// CHECK6-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 +// CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 +// CHECK6-NEXT: store i128* [[Y]], i128** [[Y_ADDR]], align 8 +// CHECK6-NEXT: store i128* [[Z]], i128** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i128*, i128** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i128*, i128** [[Z_ADDR]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i128*, i128*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i128* [[TMP0]], i128* [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..12 +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 +// CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 +// CHECK6-NEXT: [[Y1:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[X:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[Z2:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 +// CHECK6-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: [[TMP:%.*]] = alloca i128, align 16 +// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK6-NEXT: store i128* [[Y]], i128** [[Y_ADDR]], align 8 +// CHECK6-NEXT: store i128* [[Z]], i128** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load i128*, i128** [[Y_ADDR]], align 8 +// CHECK6-NEXT: [[TMP1:%.*]] = load i128*, i128** [[Z_ADDR]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i128, i128* [[TMP0]], align 16 +// CHECK6-NEXT: store i128 [[TMP2]], i128* [[Y1]], align 16 +// CHECK6-NEXT: store i128 0, i128* [[Z2]], align 16 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP4:%.*]] = bitcast i128* [[Z2]] to i8* +// CHECK6-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK6-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i64 8, i8* [[TMP7]], void (i8*, i8*)* @.omp.reduction.reduction_func.13, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: switch i32 [[TMP8]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .omp.reduction.case1: +// CHECK6-NEXT: [[TMP9:%.*]] = load i128, i128* [[TMP1]], align 16 +// CHECK6-NEXT: [[TMP10:%.*]] = load i128, i128* [[Z2]], align 16 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP9]], [[TMP10]] +// CHECK6-NEXT: store i128 [[ADD]], i128* [[TMP1]], align 16 +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.case2: +// CHECK6-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 +// CHECK6-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* +// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* +// CHECK6-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) #[[ATTR6]] +// CHECK6-NEXT: br label [[ATOMIC_CONT:%.*]] +// CHECK6: atomic_cont: +// CHECK6-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 +// CHECK6-NEXT: store i128 [[TMP14]], i128* [[TMP]], align 16 +// CHECK6-NEXT: [[TMP15:%.*]] = load i128, i128* [[TMP]], align 16 +// CHECK6-NEXT: [[TMP16:%.*]] = load i128, i128* [[Z2]], align 16 +// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i128 [[TMP15]], [[TMP16]] +// CHECK6-NEXT: store i128 [[ADD4]], i128* [[ATOMIC_TEMP3]], align 16 +// CHECK6-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* +// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* +// CHECK6-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* +// CHECK6-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) #[[ATTR6]] +// CHECK6-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] +// CHECK6: atomic_exit: +// CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK6: .omp.reduction.default: +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.13 +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 +// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i128* +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 +// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i128* +// CHECK6-NEXT: [[TMP12:%.*]] = load i128, i128* [[TMP11]], align 16 +// CHECK6-NEXT: [[TMP13:%.*]] = load i128, i128* [[TMP8]], align 16 +// CHECK6-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP12]], [[TMP13]] +// CHECK6-NEXT: store i128 [[ADD]], i128* [[TMP11]], align 16 +// CHECK6-NEXT: ret void +// +// // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: @@ -2972,7 +3681,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2984,7 +3693,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -3005,7 +3714,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3019,7 +3728,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -3032,7 +3741,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3086,7 +3795,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -3120,7 +3829,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -3134,7 +3843,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3146,7 +3855,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -3160,7 +3869,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3172,7 +3881,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -3186,7 +3895,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3198,7 +3907,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK7-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -3211,7 +3920,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3293,7 +4002,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -3328,7 +4037,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK7-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -3341,7 +4050,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3423,7 +4132,7 @@ // // // CHECK7-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -3456,3 +4165,496 @@ // CHECK7: omp.arraycpy.done2: // CHECK7-NEXT: ret void // +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27 +// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[Y:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[Y_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[Y_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP2]], i32* [[X_CASTED]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[X_CASTED]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: store i32 [[TMP4]], i32* [[Y_CASTED]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[Y_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP3]], i32 [[TMP5]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[X]], i32* [[X_ADDR]], align 4 +// CHECK8-NEXT: store i32 [[Y]], i32* [[Y_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[Y_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[TMP0]], i32* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X1:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[Y2:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x i8*], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[Y_ADDR]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[X1]], align 4 +// CHECK8-NEXT: store i32 0, i32* [[Y2]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i32* [[X1]] to i8* +// CHECK8-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 4 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i32* [[Y2]] to i8* +// CHECK8-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 4 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK8-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 2, i32 8, i8* [[TMP8]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: switch i32 [[TMP9]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK8-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK8-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK8-NEXT: ] +// CHECK8: .omp.reduction.case1: +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[X1]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[Y2]], align 4 +// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD3]], i32* [[TMP1]], align 4 +// CHECK8-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK8: .omp.reduction.case2: +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[X1]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP14]] monotonic, align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[Y2]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP16]] monotonic, align 4 +// CHECK8-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK8: .omp.reduction.default: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func +// CHECK8-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 +// CHECK8-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [2 x i8*]* +// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [2 x i8*]* +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP5]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to i32* +// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i32 0, i32 1 +// CHECK8-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to i32* +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP8]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP17]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP14]], align 4 +// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK8-NEXT: store i32 [[ADD2]], i32* [[TMP17]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[X_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[X_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[X]], i32* [[X_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[X_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[X_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[X]], i32* [[X_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[X]], i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[X_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 +// CHECK8-NEXT: store i32 [[TMP1]], i32* [[X_CASTED]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[X_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP2]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32 [[X]], i32* [[X_ADDR]], align 4 +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 +// CHECK8-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 +// CHECK8-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 +// CHECK8-NEXT: store [88 x i32]* [[Y]], [88 x i32]** [[Y_ADDR]], align 4 +// CHECK8-NEXT: store [99 x i32]* [[Z]], [99 x i32]** [[Z_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [88 x i32]*, [88 x i32]** [[Y_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [99 x i32]*, [99 x i32]** [[Z_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [88 x i32]*, [99 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), [88 x i32]* [[TMP0]], [99 x i32]* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 +// CHECK8-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 +// CHECK8-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 +// CHECK8-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 +// CHECK8-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 +// CHECK8-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [88 x i32]* [[Y]], [88 x i32]** [[Y_ADDR]], align 4 +// CHECK8-NEXT: store [99 x i32]* [[Z]], [99 x i32]** [[Z_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [88 x i32]*, [88 x i32]** [[Y_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [99 x i32]*, [99 x i32]** [[Z_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = bitcast [88 x i32]* [[Y1]] to i8* +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast [88 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 352, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], [99 x i32]* [[Z2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr i32, i32* [[ARRAY_BEGIN]], i32 99 +// CHECK8-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq i32* [[ARRAY_BEGIN]], [[TMP4]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] +// CHECK8: omp.arrayinit.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] +// CHECK8-NEXT: store i32 0, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] +// CHECK8: omp.arrayinit.done: +// CHECK8-NEXT: [[LHS_BEGIN:%.*]] = bitcast [99 x i32]* [[TMP1]] to i32* +// CHECK8-NEXT: [[RHS_BEGIN:%.*]] = bitcast [99 x i32]* [[Z2]] to i32* +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i32* [[RHS_BEGIN]] to i8* +// CHECK8-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK8-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 1, i32 4, i8* [[TMP9]], void (i8*, i8*)* @.omp.reduction.reduction_func.7, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: switch i32 [[TMP10]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK8-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK8-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK8-NEXT: ] +// CHECK8: .omp.reduction.case1: +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr i32, i32* [[LHS_BEGIN]], i32 99 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i32* [[LHS_BEGIN]], [[TMP11]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi i32* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP11]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done6: +// CHECK8-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK8: .omp.reduction.case2: +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr i32, i32* [[LHS_BEGIN]], i32 99 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq i32* [[LHS_BEGIN]], [[TMP14]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] +// CHECK8: omp.arraycpy.body8: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi i32* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi i32* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = atomicrmw add i32* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP15]] monotonic, align 4 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP14]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] +// CHECK8: omp.arraycpy.done14: +// CHECK8-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK8: .omp.reduction.default: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 +// CHECK8-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 +// CHECK8-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr i32, i32* [[TMP11]], i32 99 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i32* [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done2: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 +// CHECK8-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 +// CHECK8-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 +// CHECK8-NEXT: store [88 x i32]* [[Y]], [88 x i32]** [[Y_ADDR]], align 4 +// CHECK8-NEXT: store [99 x i32]* [[Z]], [99 x i32]** [[Z_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [88 x i32]*, [88 x i32]** [[Y_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [99 x i32]*, [99 x i32]** [[Z_ADDR]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [88 x i32]*, [99 x i32]*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [88 x i32]* [[TMP0]], [99 x i32]* [[TMP1]]) +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..8 +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 +// CHECK8-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 +// CHECK8-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 +// CHECK8-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 +// CHECK8-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 +// CHECK8-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 +// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK8-NEXT: store [88 x i32]* [[Y]], [88 x i32]** [[Y_ADDR]], align 4 +// CHECK8-NEXT: store [99 x i32]* [[Z]], [99 x i32]** [[Z_ADDR]], align 4 +// CHECK8-NEXT: [[TMP0:%.*]] = load [88 x i32]*, [88 x i32]** [[Y_ADDR]], align 4 +// CHECK8-NEXT: [[TMP1:%.*]] = load [99 x i32]*, [99 x i32]** [[Z_ADDR]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = bitcast [88 x i32]* [[Y1]] to i8* +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast [88 x i32]* [[TMP0]] to i8* +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 352, i1 false) +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], [99 x i32]* [[Z2]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr i32, i32* [[ARRAY_BEGIN]], i32 99 +// CHECK8-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq i32* [[ARRAY_BEGIN]], [[TMP4]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] +// CHECK8: omp.arrayinit.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] +// CHECK8-NEXT: store i32 0, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] +// CHECK8: omp.arrayinit.done: +// CHECK8-NEXT: [[LHS_BEGIN:%.*]] = bitcast [99 x i32]* [[TMP1]] to i32* +// CHECK8-NEXT: [[RHS_BEGIN:%.*]] = bitcast [99 x i32]* [[Z2]] to i32* +// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i32* [[RHS_BEGIN]] to i8* +// CHECK8-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 +// CHECK8-NEXT: [[TMP9:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* +// CHECK8-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 1, i32 4, i8* [[TMP9]], void (i8*, i8*)* @.omp.reduction.reduction_func.9, [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: switch i32 [[TMP10]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK8-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK8-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK8-NEXT: ] +// CHECK8: .omp.reduction.case1: +// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr i32, i32* [[LHS_BEGIN]], i32 99 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i32* [[LHS_BEGIN]], [[TMP11]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi i32* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP11]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done6: +// CHECK8-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK8: .omp.reduction.case2: +// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr i32, i32* [[LHS_BEGIN]], i32 99 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq i32* [[LHS_BEGIN]], [[TMP14]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] +// CHECK8: omp.arraycpy.body8: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi i32* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi i32* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = atomicrmw add i32* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP15]] monotonic, align 4 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP14]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] +// CHECK8: omp.arraycpy.done14: +// CHECK8-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) +// CHECK8-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK8: .omp.reduction.default: +// CHECK8-NEXT: ret void +// +// +// CHECK8-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 +// CHECK8-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK8-NEXT: entry: +// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 +// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 +// CHECK8-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 +// CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* +// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 +// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* +// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 +// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* +// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 +// CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 +// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* +// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr i32, i32* [[TMP11]], i32 99 +// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i32* [[TMP11]], [[TMP12]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// CHECK8: omp.arraycpy.body: +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] +// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] +// CHECK8: omp.arraycpy.done2: +// CHECK8-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp --- a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp @@ -1303,7 +1303,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -1316,7 +1316,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1326,7 +1326,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1339,7 +1339,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1349,7 +1349,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1373,7 +1373,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1394,7 +1394,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1406,7 +1406,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1430,7 +1430,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1440,7 +1440,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1470,7 +1470,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1490,8 +1490,196 @@ // CHECK9-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -1503,7 +1691,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1513,7 +1701,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1525,7 +1713,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1535,7 +1723,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1556,7 +1744,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1576,7 +1764,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1588,7 +1776,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1612,7 +1800,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1622,7 +1810,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1650,7 +1838,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1668,3 +1856,2716 @@ // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: ret void // +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3bari +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP6]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK17-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK17-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK17-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) +// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK17: omp_offload.failed7: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK17: omp_offload.cont8: +// CHECK17-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK17-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK17-NEXT: ret i32 [[CONV10]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) +// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK17: omp_offload.failed7: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK17: omp_offload.cont8: +// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK17-NEXT: ret i32 [[ADD9]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) +// CHECK17-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK17-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK17-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK17-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) +// CHECK17-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK17-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK17: omp_offload.failed3: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK17: omp_offload.cont4: +// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP30]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK17-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK17-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3bari +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP6]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK18-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK18-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK18-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) +// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK18: omp_offload.failed7: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK18: omp_offload.cont8: +// CHECK18-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK18-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK18-NEXT: ret i32 [[CONV10]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* +// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP7]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) +// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK18-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK18: omp_offload.failed7: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK18: omp_offload.cont8: +// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK18-NEXT: ret i32 [[ADD9]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) +// CHECK18-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK18-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK18-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK18-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) +// CHECK18-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK18-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK18: omp_offload.failed3: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK18: omp_offload.cont4: +// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP30]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK18-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK18-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK18-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3bari +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP6]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK19-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK19-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK19-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) +// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK19: omp_offload.failed6: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK19: omp_offload.cont7: +// CHECK19-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK19-NEXT: ret i32 [[CONV]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) +// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK19: omp_offload.failed6: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK19: omp_offload.cont7: +// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK19-NEXT: ret i32 [[ADD8]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) +// CHECK19-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK19-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK19-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK19-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) +// CHECK19-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK19-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK19: omp_offload.failed2: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK19: omp_offload.cont3: +// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP30]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK19-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK19-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK19-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3bari +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP6]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK20-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK20-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK20-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) +// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK20: omp_offload.failed6: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK20: omp_offload.cont7: +// CHECK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK20-NEXT: ret i32 [[CONV]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) +// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +// CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) +// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK20: omp_offload.failed6: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK20: omp_offload.cont7: +// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK20-NEXT: ret i32 [[ADD8]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) +// CHECK20-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK20-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK20-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK20-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) +// CHECK20-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK20-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK20: omp_offload.failed2: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK20: omp_offload.cont3: +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP30]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK20-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK20-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK20-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK25-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK26-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK27-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK28-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp --- a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp +++ b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp @@ -1345,7 +1345,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 @@ -1362,7 +1362,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1372,7 +1372,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1385,7 +1385,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1395,7 +1395,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1419,7 +1419,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1440,7 +1440,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1452,7 +1452,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1476,7 +1476,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1486,7 +1486,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1516,7 +1516,7 @@ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1536,8 +1536,200 @@ // CHECK9-NEXT: ret void // // +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK10-NEXT: ret void +// +// +// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK10-NEXT: entry: +// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK10-NEXT: ret void +// +// // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 @@ -1552,7 +1744,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1562,7 +1754,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1574,7 +1766,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1584,7 +1776,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1605,7 +1797,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1625,7 +1817,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1637,7 +1829,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1661,7 +1853,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1671,7 +1863,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1699,7 +1891,7 @@ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1717,3 +1909,2817 @@ // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: ret void // +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK12-NEXT: ret void +// +// +// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK12-NEXT: entry: +// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK12-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z3bari +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP6]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK17-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK17-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) +// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK17-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) +// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK17: omp_offload.failed7: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK17: omp_offload.cont8: +// CHECK17-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK17-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK17-NEXT: ret i32 [[CONV10]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 +// CHECK17-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) +// CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK17-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5]] to i32* +// CHECK17-NEXT: store i32 [[TMP23]], i32* [[CONV6]], align 4 +// CHECK17-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5]], align 8 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK17-NEXT: store i64 [[TMP24]], i64* [[TMP26]], align 8 +// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK17-NEXT: store i64 [[TMP24]], i64* [[TMP28]], align 8 +// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) +// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK17: omp_offload.failed10: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP24]]) #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK17: omp_offload.cont11: +// CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK17-NEXT: ret i32 [[ADD12]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK17-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) +// CHECK17-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK17-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK17: omp_offload.failed: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK17: omp_offload.cont: +// CHECK17-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK17-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK17-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK17-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) +// CHECK17-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK17-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK17: omp_offload.failed3: +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK17: omp_offload.cont4: +// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK17-NEXT: ret i32 [[TMP30]] +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK17-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK17-NEXT: ret void +// +// +// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK17-NEXT: entry: +// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK17-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z3bari +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP6]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK18-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK18-NEXT: store double* [[A]], double** [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 +// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) +// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 +// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK18-NEXT: store double* [[A3]], double** [[TMP29]], align 8 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) +// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] +// CHECK18: omp_offload.failed7: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] +// CHECK18: omp_offload.cont8: +// CHECK18-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 +// CHECK18-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK18-NEXT: ret i32 [[CONV10]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 +// CHECK18-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* +// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 +// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP7]], align 8 +// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64* +// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP9]], align 8 +// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* +// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP14]], align 8 +// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK18-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) +// CHECK18-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK18-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5]] to i32* +// CHECK18-NEXT: store i32 [[TMP23]], i32* [[CONV6]], align 4 +// CHECK18-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5]], align 8 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* +// CHECK18-NEXT: store i64 [[TMP24]], i64* [[TMP26]], align 8 +// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* +// CHECK18-NEXT: store i64 [[TMP24]], i64* [[TMP28]], align 8 +// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8 +// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) +// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] +// CHECK18: omp_offload.failed10: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP24]]) #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT11]] +// CHECK18: omp_offload.cont11: +// CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK18-NEXT: ret i32 [[ADD12]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK18-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) +// CHECK18-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK18-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK18: omp_offload.failed: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK18: omp_offload.cont: +// CHECK18-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK18-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* +// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 +// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* +// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 +// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 +// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 +// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* +// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 +// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 +// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* +// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 +// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* +// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 +// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 +// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK18-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK18-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) +// CHECK18-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK18-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] +// CHECK18: omp_offload.failed3: +// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] +// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT4]] +// CHECK18: omp_offload.cont4: +// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK18-NEXT: ret i32 [[TMP30]] +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK18-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK18-NEXT: ret void +// +// +// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK18-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK18-NEXT: entry: +// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK18-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z3bari +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP6]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK19-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK19-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) +// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK19-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) +// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK19: omp_offload.failed6: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK19: omp_offload.cont7: +// CHECK19-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK19-NEXT: ret i32 [[CONV]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 +// CHECK19-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) +// CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK19-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK19-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK19-NEXT: store i32 [[TMP24]], i32* [[TMP26]], align 4 +// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK19-NEXT: store i32 [[TMP24]], i32* [[TMP28]], align 4 +// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) +// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK19: omp_offload.failed8: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP24]]) #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK19: omp_offload.cont9: +// CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK19-NEXT: ret i32 [[ADD10]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) +// CHECK19-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK19-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK19: omp_offload.failed: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK19: omp_offload.cont: +// CHECK19-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK19-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK19-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK19-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) +// CHECK19-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK19-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK19: omp_offload.failed2: +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK19: omp_offload.cont3: +// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK19-NEXT: ret i32 [[TMP30]] +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK19-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK19-NEXT: ret void +// +// +// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK19-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK19-NEXT: entry: +// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK19-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z3bari +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] +// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] +// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP6]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei +// CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 1, i32* [[B]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] +// CHECK20-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** +// CHECK20-NEXT: store double* [[A]], double** [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP23]]) +// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 +// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** +// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 +// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** +// CHECK20-NEXT: store double* [[A2]], double** [[TMP29]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1024) +// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK20: omp_offload.failed6: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK20: omp_offload.cont7: +// CHECK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 +// CHECK20-NEXT: ret i32 [[CONV]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 +// CHECK20-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 +// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4 +// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32* +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4 +// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* +// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 +// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK20-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 2, i8** [[TMP16]], i8** [[TMP17]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP18]], i32 [[TMP19]]) +// CHECK20-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// CHECK20-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP22]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4]], align 4 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* +// CHECK20-NEXT: store i32 [[TMP24]], i32* [[TMP26]], align 4 +// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* +// CHECK20-NEXT: store i32 [[TMP24]], i32* [[TMP28]], align 4 +// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP29]], align 4 +// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 +// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP32]]) +// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 +// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] +// CHECK20: omp_offload.failed8: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP24]]) #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT9]] +// CHECK20: omp_offload.cont9: +// CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK20-NEXT: ret i32 [[ADD10]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i +// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 +// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 20) +// CHECK20-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK20-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK20: omp_offload.failed: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK20: omp_offload.cont: +// CHECK20-NEXT: store i16 1, i16* [[B]], align 2 +// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 +// CHECK20-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 +// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* +// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 +// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 +// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 +// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* +// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 +// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 +// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 +// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* +// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 +// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 +// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK20-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 +// CHECK20-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 +// CHECK20-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 1024) +// CHECK20-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK20-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] +// CHECK20: omp_offload.failed2: +// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] +// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT3]] +// CHECK20: omp_offload.cont3: +// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 +// CHECK20-NEXT: ret i32 [[TMP30]] +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK20-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 +// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK20-NEXT: ret void +// +// +// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg +// CHECK20-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK20-NEXT: entry: +// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) +// CHECK20-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK25-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK25-NEXT: ret void +// +// +// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK25-NEXT: entry: +// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK25-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* +// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 +// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK26-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2 +// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* +// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 +// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 +// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* +// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 +// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* +// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK27-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK27-NEXT: ret void +// +// +// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK27-NEXT: entry: +// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK27-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 +// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 +// CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 +// CHECK28-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* +// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 +// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) +// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 +// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* +// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* +// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 +// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 +// CHECK28-NEXT: ret void +// diff --git a/clang/test/OpenMP/teams_codegen.cpp b/clang/test/OpenMP/teams_codegen.cpp --- a/clang/test/OpenMP/teams_codegen.cpp +++ b/clang/test/OpenMP/teams_codegen.cpp @@ -2355,7 +2355,7 @@ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK25-SAME: (i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 @@ -2365,7 +2365,7 @@ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2379,7 +2379,7 @@ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK25-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK25-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 @@ -2388,7 +2388,7 @@ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2401,8 +2401,55 @@ // CHECK25-NEXT: ret void // // +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 +// CHECK26-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK26-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK26-NEXT: store i32 0, i32* [[TMP0]], align 4 +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 +// CHECK26-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 +// CHECK26-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) +// CHECK26-NEXT: ret void +// +// +// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK26-NEXT: entry: +// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 +// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK26-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 +// CHECK26-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 +// CHECK26-NEXT: store i8** null, i8*** [[TMP0]], align 8 +// CHECK26-NEXT: ret void +// +// // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK27-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 @@ -2411,7 +2458,7 @@ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2425,7 +2472,7 @@ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK27-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 // CHECK27-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 @@ -2434,7 +2481,7 @@ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2447,8 +2494,54 @@ // CHECK27-NEXT: ret void // // +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 +// CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK28-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 +// CHECK28-NEXT: store i32 0, i32* [[TMP0]], align 4 +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 +// CHECK28-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 +// CHECK28-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) +// CHECK28-NEXT: ret void +// +// +// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK28-NEXT: entry: +// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 +// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK28-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 +// CHECK28-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 +// CHECK28-NEXT: store i8** null, i8*** [[TMP0]], align 4 +// CHECK28-NEXT: ret void +// +// // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK33-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2468,7 +2561,7 @@ // // // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK33-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2482,7 +2575,7 @@ // // // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK33-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2501,7 +2594,7 @@ // // // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK33-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2514,8 +2607,75 @@ // CHECK33-NEXT: ret void // // +// CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 +// CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK34-NEXT: entry: +// CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK34-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 +// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK34-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* +// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]]) +// CHECK34-NEXT: ret void +// +// +// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK34-NEXT: entry: +// CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 +// CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK34-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 +// CHECK34-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 +// CHECK34-NEXT: store i32 0, i32* [[TMP0]], align 4 +// CHECK34-NEXT: ret void +// +// +// CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 +// CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK34-NEXT: entry: +// CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 +// CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 +// CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 +// CHECK34-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 +// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* +// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* +// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 +// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 +// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) +// CHECK34-NEXT: ret void +// +// +// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK34-NEXT: entry: +// CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 +// CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 +// CHECK34-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 +// CHECK34-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 +// CHECK34-NEXT: store i8** null, i8*** [[TMP0]], align 8 +// CHECK34-NEXT: ret void +// +// // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK35-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2532,7 +2692,7 @@ // // // CHECK35-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK35-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2546,7 +2706,7 @@ // // // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK35-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2563,7 +2723,7 @@ // // // CHECK35-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK35-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2576,6 +2736,68 @@ // CHECK35-NEXT: ret void // // +// CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 +// CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK36-NEXT: entry: +// CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK36-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) +// CHECK36-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK36-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK36-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 +// CHECK36-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK36-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK36-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK36-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) +// CHECK36-NEXT: ret void +// +// +// CHECK36-LABEL: define {{[^@]+}}@.omp_outlined. +// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK36-NEXT: entry: +// CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 +// CHECK36-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK36-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK36-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 +// CHECK36-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 +// CHECK36-NEXT: store i32 0, i32* [[TMP0]], align 4 +// CHECK36-NEXT: ret void +// +// +// CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 +// CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK36-NEXT: entry: +// CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 +// CHECK36-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) +// CHECK36-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 +// CHECK36-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 +// CHECK36-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 +// CHECK36-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// CHECK36-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 +// CHECK36-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK36-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) +// CHECK36-NEXT: ret void +// +// +// CHECK36-LABEL: define {{[^@]+}}@.omp_outlined..1 +// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK36-NEXT: entry: +// CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 +// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 +// CHECK36-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK36-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 +// CHECK36-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 +// CHECK36-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 +// CHECK36-NEXT: store i8** null, i8*** [[TMP0]], align 4 +// CHECK36-NEXT: ret void +// +// // CHECK41-LABEL: define {{[^@]+}}@_Z3foov // CHECK41-SAME: () #[[ATTR0:[0-9]+]] { // CHECK41-NEXT: entry: diff --git a/llvm/test/Transforms/SimplifyCFG/tautological-conditional-branch-convergent-noundef.ll b/llvm/test/Transforms/SimplifyCFG/tautological-conditional-branch-convergent-noundef.ll new file mode 100644 --- /dev/null +++ b/llvm/test/Transforms/SimplifyCFG/tautological-conditional-branch-convergent-noundef.ll @@ -0,0 +1,31 @@ +; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s + +define void @func(i32 %arg17) { +; CHECK-LABEL: @func( +; CHECK-LABEL: bb1: +; CHECK-NEXT: [[I:%.*]] = icmp eq i32 [[ARG17:%.*]], 0 +; CHECK-NEXT: br i1 [[I:%.*]], label [[BB2:%.*]], label [[BB3:%.*]] +; CHECK-LABEL: bb2: +; CHECK-NEXT: [[I2:%.*]] = call noundef double @one() +; CHECK-NEXT: br label [[BB3:%.*]] +; CHECK-LABEL: bb3: +; CHECK-NEXT: [[I3:%.*]] = phi double [ [[I2:%.*]], [[BB2:%.*]] ], [ undef, [[BB1:%.*]] ] +; CHECK-NEXT: [[I4:%.*]] = call double @two(double [[I3:%.*]], i1 [[I:%.*]]) +; CHECK-NEXT: ret void + +bb1: + %i1 = icmp eq i32 %arg17, 0 + br i1 %i1, label %bb2, label %bb3 + +bb2: ; preds = %bb1 + %i2 = call noundef double @one() + br label %bb3 + +bb3: ; preds = %bb2, %bb1 + %i3 = phi double [%i2, %bb2], [undef, %bb1] + %i4 = call double @two(double %i3, i1 %i1) + ret void +} + +declare double @one() +declare double @two(double, i1) convergent \ No newline at end of file