diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -440,17 +440,29 @@
 /// CheckForLiveRegDef - Return true and update live register vector if the
 /// specified register def of the specified SUnit clobbers any "live" registers.
 static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,
-                               std::vector<SUnit*> &LiveRegDefs,
+                               std::vector<SUnit *> &LiveRegDefs,
                                SmallSet<unsigned, 4> &RegAdded,
                                SmallVectorImpl<unsigned> &LRegs,
-                               const TargetRegisterInfo *TRI) {
+                               const TargetRegisterInfo *TRI,
+                               const SDNode *Node = nullptr) {
   bool Added = false;
   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
-    if (LiveRegDefs[*AI] && LiveRegDefs[*AI] != SU) {
-      if (RegAdded.insert(*AI).second) {
-        LRegs.push_back(*AI);
-        Added = true;
-      }
+    // Check if Ref is live.
+    if (!LiveRegDefs[*AI])
+      continue;
+
+    // Allow multiple uses of the same def.
+    if (LiveRegDefs[*AI] == SU)
+      continue;
+
+    // Allow multiple uses of same def
+    if (Node && LiveRegDefs[*AI]->getNode() == Node)
+      continue;
+
+    // Add Reg to the set of interfering live regs.
+    if (RegAdded.insert(*AI).second) {
+      LRegs.push_back(*AI);
+      Added = true;
     }
   }
   return Added;
@@ -502,6 +514,15 @@
       }
       continue;
     }
+
+    if (Node->getOpcode() == ISD::CopyToReg) {
+      Register Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
+      if (Reg.isPhysical()) {
+        SDNode *SrcNode = Node->getOperand(2).getNode();
+        CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI, SrcNode);
+      }
+    }
+
     if (!Node->isMachineOpcode())
       continue;
     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1294,11 +1294,11 @@
 
 /// CheckForLiveRegDef - Return true and update live register vector if the
 /// specified register def of the specified SUnit clobbers any "live" registers.
-static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,
-                               SUnit **LiveRegDefs,
+static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs,
                                SmallSet<unsigned, 4> &RegAdded,
                                SmallVectorImpl<unsigned> &LRegs,
-                               const TargetRegisterInfo *TRI) {
+                               const TargetRegisterInfo *TRI,
+                               const SDNode *Node = nullptr) {
   for (MCRegAliasIterator AliasI(Reg, TRI, true); AliasI.isValid(); ++AliasI) {
 
     // Check if Ref is live.
@@ -1307,6 +1307,10 @@
     // Allow multiple uses of the same def.
     if (LiveRegDefs[*AliasI] == SU) continue;
 
+    // Allow multiple uses of same def
+    if (Node && LiveRegDefs[*AliasI]->getNode() == Node)
+      continue;
+
     // Add Reg to the set of interfering live regs.
     if (RegAdded.insert(*AliasI).second) {
       LRegs.push_back(*AliasI);
@@ -1387,6 +1391,15 @@
       continue;
     }
 
+    if (Node->getOpcode() == ISD::CopyToReg) {
+      Register Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
+      if (Reg.isPhysical()) {
+        SDNode *SrcNode = Node->getOperand(2).getNode();
+        CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI,
+                           SrcNode);
+      }
+    }
+
     if (!Node->isMachineOpcode())
       continue;
     // If we're in the middle of scheduling a call, don't begin scheduling
diff --git a/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll b/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx90a -O3 -pre-RA-sched=source < %s | FileCheck -check-prefix=RRLIST %s
+; RUN: llc -march=amdgcn -mcpu=gfx90a -O3 -pre-RA-sched=fast < %s | FileCheck -check-prefix=FAST %s
+
+
+define protected amdgpu_kernel void @sccClobber(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %e, ptr addrspace(1) %f, ptr addrspace(1) %pout.coerce) {
+; RRLIST-LABEL: sccClobber:
+; RRLIST:       ; %bb.0: ; %entry
+; RRLIST-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x24
+; RRLIST-NEXT:    v_mov_b32_e32 v2, 0
+; RRLIST-NEXT:    s_waitcnt lgkmcnt(0)
+; RRLIST-NEXT:    s_load_dword s16, s[8:9], 0x0
+; RRLIST-NEXT:    s_load_dwordx2 s[2:3], s[6:7], 0x0
+; RRLIST-NEXT:    s_load_dwordx2 s[12:13], s[4:5], 0x0
+; RRLIST-NEXT:    s_load_dwordx2 s[14:15], s[0:1], 0x44
+; RRLIST-NEXT:    s_load_dword s17, s[10:11], 0x0
+; RRLIST-NEXT:    s_waitcnt lgkmcnt(0)
+; RRLIST-NEXT:    s_min_i32 s4, s16, 0
+; RRLIST-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
+; RRLIST-NEXT:    v_cmp_lt_i64_e32 vcc, s[12:13], v[0:1]
+; RRLIST-NEXT:    s_and_b64 s[0:1], vcc, exec
+; RRLIST-NEXT:    s_cselect_b32 s0, s16, s17
+; RRLIST-NEXT:    s_cmp_eq_u64 s[12:13], s[2:3]
+; RRLIST-NEXT:    s_cselect_b32 s0, s4, s0
+; RRLIST-NEXT:    v_mov_b32_e32 v0, s0
+; RRLIST-NEXT:    global_store_dword v2, v0, s[14:15]
+; RRLIST-NEXT:    s_endpgm
+;
+; FAST-LABEL: sccClobber:
+; FAST:       ; %bb.0: ; %entry
+; FAST-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x24
+; FAST-NEXT:    v_mov_b32_e32 v2, 0
+; FAST-NEXT:    s_waitcnt lgkmcnt(0)
+; FAST-NEXT:    s_load_dword s16, s[8:9], 0x0
+; FAST-NEXT:    s_load_dwordx2 s[2:3], s[6:7], 0x0
+; FAST-NEXT:    s_load_dwordx2 s[12:13], s[4:5], 0x0
+; FAST-NEXT:    s_load_dwordx2 s[14:15], s[0:1], 0x44
+; FAST-NEXT:    s_load_dword s17, s[10:11], 0x0
+; FAST-NEXT:    s_waitcnt lgkmcnt(0)
+; FAST-NEXT:    s_min_i32 s4, s16, 0
+; FAST-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
+; FAST-NEXT:    v_cmp_lt_i64_e32 vcc, s[12:13], v[0:1]
+; FAST-NEXT:    s_and_b64 s[0:1], vcc, exec
+; FAST-NEXT:    s_cselect_b32 s0, s16, s17
+; FAST-NEXT:    s_cmp_eq_u64 s[12:13], s[2:3]
+; FAST-NEXT:    s_cselect_b32 s0, s4, s0
+; FAST-NEXT:    v_mov_b32_e32 v0, s0
+; FAST-NEXT:    global_store_dword v2, v0, s[14:15]
+; FAST-NEXT:    s_endpgm
+entry:
+  %i = load i64, ptr addrspace(1) %a, align 8
+  %i.1 = load i64, ptr addrspace(1) %b, align 8
+  %i.2 = load i32, ptr addrspace(1) %e, align 4
+  %i.3 = load i32, ptr addrspace(1) %f, align 4
+  %cmp7.1 = icmp eq i64 %i, %i.1
+  %call.1 = tail call noundef i32 @llvm.smin.i32(i32 noundef 0, i32 noundef %i.2)
+  %cmp8.1 = icmp slt i64 %i, %i.1
+  %cond.1 = select i1 %cmp8.1, i32 %i.2, i32 %i.3
+  %cond14.1 = select i1 %cmp7.1, i32 %call.1, i32 %cond.1
+  store i32 %cond14.1, ptr addrspace(1) %pout.coerce, align 4
+  ret void
+}
+
+declare i32 @llvm.smin.i32(i32, i32)
diff --git a/llvm/test/CodeGen/X86/comi b/llvm/test/CodeGen/X86/comi
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/comi
@@ -0,0 +1,89 @@
+ftrunc.ll
+vector-truncate-combine.ll
+fptoui-sat-scalar.ll
+sqrt-partial.ll
+swifterror.ll
+vector-constrained-fp-intrinsics.ll
+win-alloca-expander.ll
+avx512-cmp.ll
+cmov-into-branch.ll
+sse2-intrinsics-x86.ll
+fp-intrinsics.ll
+stack-folding-fp-avx1.ll
+vector-reduce-fmin-nnan.ll
+avx512-intrinsics.ll
+fast-isel-prolog-dbgloc.ll
+extractelement-fp.ll
+zext-demanded.ll
+compare_folding.ll
+fp-strict-scalar-fptoint.ll
+vec-strict-cmp-sub128.ll
+isint.ll
+stack-protector.ll
+fcmp-logic.ll
+fsxor-alignment.ll
+win64_params.ll
+fast-isel-cmp.ll
+sse2-intrinsics-fast-isel.ll
+fast-isel-select-cmov2.ll
+undef-label.ll
+avx512-vec-cmp.ll
+sse-intrinsics-x86.ll
+fp-strict-scalar-cmp-fp16.ll
+tailcall-msvc-conventions.ll
+2008-08-17-UComiCodeGenBug.ll
+is_fpclass.ll
+or-lea.ll
+tailcall-cgp-dup.ll
+cmov-double.ll
+fp-une-cmp.ll
+fpclamptosat.ll
+scalar-fp-to-i64.ll
+pseudo_cmov_lower2.ll
+pr44749.ll
+fp-stack-compare.ll
+fast-isel-select-cmp.ll
+fsetcc.ll
+stack-folding-fp-sse42.ll
+avx-cmp.ll
+select.ll
+movtopush64.ll
+bitcast-int-to-vector.ll
+vec-strict-fptoint-512.ll
+vec-strict-cmp-128-fp16.ll
+fast-isel-cmp-branch3.ll
+fast-isel-select-pseudo-cmov.ll
+pr51615.ll
+2008-10-24-FlippedCompare.ll
+statepoint-vreg.ll
+avx512-insert-extract.ll
+avx512fp16-intrinsics.ll
+vec-strict-fptoint-128.ll
+fast-isel-cmp-branch2.ll
+avx512fp16-arith.ll
+cmovcmov.ll
+fp-cvt.ll
+fptosi-sat-vector-128.ll
+inline-asm-fpstack.ll
+avx512-select.ll
+fp-strict-scalar-cmp.ll
+comi-flags.ll
+avx512-fsel.ll
+vec-strict-fptoint-256.ll
+half.ll
+brcond.ll
+avx512-calling-conv.ll
+fp80-strict-scalar.ll
+switch.ll
+fptoui-sat-vector-128.ll
+fptosi-sat-scalar.ll
+cmp.ll
+inline-asm-x-scalar.ll
+nontemporal-loads.ll
+vec-strict-cmp-128.ll
+compare-inf.ll
+isnan2.ll
+sse-intrinsics-fast-isel.ll
+vector-reduce-fmax-nnan.ll
+AMX/lat-combine-amx-bitcast.ll
+tail-opts.ll
diff --git a/llvm/test/CodeGen/X86/sse b/llvm/test/CodeGen/X86/sse
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/sse
@@ -0,0 +1,579 @@
+haddsub-shuf.ll
+vec_uint_to_fp.ll
+avx512-rotate.ll
+vshift_split.ll
+ftrunc.ll
+viabs.ll
+paddus.ll
+sdiv-exact.ll
+vector-reduce-smax.ll
+horizontal-reduce-smax.ll
+vselect-packss.ll
+avx512vbmi2vl-intrinsics-upgrade.ll
+avx-shift.ll
+smax.ll
+memcmp.ll
+vector-zext.ll
+oddshuffles.ll
+widen_conv-1.ll
+insertelement-shuffle.ll
+vector-fshr-128.ll
+vector-sext.ll
+vector-interleaved-load-i8-stride-2.ll
+horizontal-reduce-umax.ll
+vec_ctbits.ll
+vector-reduce-smin.ll
+vector-shift-shl-sub128.ll
+vec_set.ll
+avx2-intrinsics-x86.ll
+vector-popcnt-256.ll
+vector-idiv-udiv-128.ll
+vector-shuffle-512-v64.ll
+vector-compare-results.ll
+hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+smul_fix_sat.ll
+shuffle-vs-trunc-128.ll
+vsplit-and.ll
+avx-logic.ll
+omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
+vector-constrained-fp-intrinsics.ll
+combine-bitselect.ll
+prefer-avx256-lzcnt.ll
+vector-trunc-usat.ll
+avx512-intrinsics-upgrade.ll
+vec_uint_to_fp-fastmath.ll
+div-rem-pair-recomposition-unsigned.ll
+pr44976.ll
+avx2-shift.ll
+avx512f-vec-test-testn.ll
+vshift-3.ll
+vector-ext-logic.ll
+vector-interleaved-store-i32-stride-2.ll
+vector-trunc-ssat.ll
+vector-reduce-fmax.ll
+horizontal-reduce-smin.ll
+vector-reduce-add-zext.ll
+vec_setcc-2.ll
+fast-isel-bitcast-crash.ll
+combine-add.ll
+vector-reduce-umax.ll
+pr48215.ll
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+vector_splat-const-shift-of-constmasked.ll
+midpoint-int-vec-128.ll
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+vector-reduce-xor.ll
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