AArch64: don't try to fold NZCV spill into an operation

[t.p.northover]

Summary

Only mrs & msr can access the NZCV flags register, so don't try to create any instructions spilling it.

Bit of an ugly test-case I'm afraid, so I decided the best way to limit scope for things to change and invalidate it was going the MIR route.

[t.p.northover]

Ping.

[dmgreen]

Is this related with https://reviews.llvm.org/D127294? Can the NZCV check be pulled out before the if (MI.isFullCopy()) block?

[t.p.northover]

Yep, basically the same thing. Abandoning this since it's already fixed.

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
   // instead of
   //
   //   LDRXui %Temp, fi<#0>
   //   %0 = FMOV %Temp
   //
   if (MI.isCopy() && Ops.size() == 1 &&
       // Make sure we're only folding the explicit COPY defs/uses.
       (Ops[0] == 0 || Ops[0] == 1)) {
+
+    // NZCV only accessible by MRS/MSR, can't be spilled.
+    if (MI.getOperand(0).getReg() == AArch64::NZCV ||
+        MI.getOperand(1).getReg() == AArch64::NZCV)
+      return nullptr;
+
     bool IsSpill = Ops[0] == 0;
     bool IsFill = !IsSpill;
     const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
     const MachineRegisterInfo &MRI = MF.getRegInfo();
     MachineBasicBlock &MBB = *MI.getParent();
     const MachineOperand &DstMO = MI.getOperand(0);
     const MachineOperand &SrcMO = MI.getOperand(1);
     Register DstReg = DstMO.getReg();

llvm/test/CodeGen/AArch64/nospill-nzcv.mir

+# RUN: llc -mtriple=arm64-apple-ios -run-pass=greedy %s -o - | FileCheck %s
+# CHECK-NOT: STR{{.*}}$nzcv
+# CHECK-ONT: LDR{{.*}}$nzcv
+--- |
+  define internal fastcc i128 @__bid128_pow(i128 %bid_y.coerce, i32 %rnd_mode, i32* %pfpsf, i64 %0, i64 %add5868, i1 %cmp5876, i64 %add5958, i64 %conv1548, i64 %shr6016, i64 %mul6778, i64 %mul6777, i64 %conv6784, i64 %add6785, i64 %add6787, i64 %shr6788, i64 %shl6792, i1 %cmp7897, i64 %add12985, i64 %add3880) {
+    unreachable
+  }
+
+  declare void @__bid128_mul()
+...
+---
+name:            __bid128_pow
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr64 }
+  - { id: 1, class: gpr64 }
+  - { id: 2, class: gpr32 }
+  - { id: 3, class: gpr64 }
+  - { id: 4, class: gpr64 }
+  - { id: 5, class: gpr64 }
+  - { id: 6, class: gpr32 }
+  - { id: 7, class: gpr64 }
+  - { id: 8, class: gpr64 }
+  - { id: 9, class: gpr64common }
+  - { id: 10, class: gpr64 }
+  - { id: 11, class: gpr64 }
+  - { id: 12, class: gpr64 }
+  - { id: 13, class: gpr64 }
+  - { id: 14, class: gpr64 }
+  - { id: 15, class: gpr64 }
+  - { id: 16, class: gpr64 }
+  - { id: 17, class: gpr64 }
+  - { id: 18, class: gpr64sp }
+  - { id: 19, class: gpr32 }
+  - { id: 20, class: gpr64 }
+  - { id: 21, class: gpr64 }
+  - { id: 22, class: gpr32 }
+  - { id: 23, class: gpr32 }
+  - { id: 24, class: gpr64 }
+  - { id: 25, class: gpr64sp }
+  - { id: 26, class: gpr64common }
+  - { id: 27, class: gpr64 }
+  - { id: 28, class: gpr64sp }
+  - { id: 29, class: gpr64 }
+  - { id: 30, class: gpr64 }
+  - { id: 31, class: gpr64 }
+  - { id: 32, class: gpr64 }
+  - { id: 33, class: gpr64 }
+  - { id: 34, class: gpr64 }
+  - { id: 35, class: gpr64common }
+  - { id: 36, class: gpr64 }
+  - { id: 37, class: gpr64 }
+  - { id: 38, class: gpr64 }
+  - { id: 39, class: gpr64 }
+  - { id: 40, class: gpr32 }
+  - { id: 41, class: gpr32 }
+  - { id: 42, class: gpr64 }
+  - { id: 43, class: gpr64 }
+  - { id: 44, class: gpr32 }
+  - { id: 45, class: gpr64common }
+  - { id: 46, class: gpr64 }
+  - { id: 47, class: gpr32 }
+  - { id: 48, class: gpr64 }
+  - { id: 49, class: gpr32 }
+  - { id: 50, class: gpr64 }
+  - { id: 51, class: gpr64 }
+  - { id: 52, class: gpr64 }
+  - { id: 53, class: gpr32 }
+  - { id: 54, class: gpr64 }
+  - { id: 55, class: gpr64 }
+  - { id: 56, class: gpr64 }
+  - { id: 57, class: gpr64 }
+  - { id: 58, class: gpr64 }
+  - { id: 59, class: gpr32 }
+  - { id: 60, class: gpr32 }
+  - { id: 61, class: gpr64 }
+  - { id: 62, class: gpr64all }
+  - { id: 63, class: gpr64common }
+  - { id: 64, class: gpr64 }
+  - { id: 65, class: gpr64 }
+  - { id: 66, class: gpr32 }
+  - { id: 67, class: gpr32 }
+  - { id: 68, class: gpr64 }
+  - { id: 69, class: gpr64common }
+  - { id: 70, class: gpr64 }
+  - { id: 71, class: gpr64 }
+  - { id: 72, class: gpr64 }
+  - { id: 73, class: gpr64 }
+  - { id: 74, class: gpr64 }
+  - { id: 75, class: gpr64 }
+  - { id: 76, class: gpr32 }
+  - { id: 77, class: gpr32 }
+  - { id: 78, class: gpr64 }
+  - { id: 79, class: gpr64common }
+  - { id: 80, class: gpr64 }
+  - { id: 81, class: gpr32 }
+  - { id: 82, class: gpr64 }
+  - { id: 83, class: gpr64 }
+  - { id: 84, class: gpr64 }
+  - { id: 85, class: gpr32 }
+  - { id: 86, class: gpr64 }
+  - { id: 87, class: gpr32 }
+  - { id: 88, class: gpr64 }
+  - { id: 89, class: gpr32 }
+  - { id: 90, class: gpr64 }
+  - { id: 91, class: gpr64all }
+  - { id: 92, class: gpr64common }
+  - { id: 93, class: gpr64 }
+  - { id: 94, class: gpr64 }
+  - { id: 95, class: gpr64 }
+  - { id: 96, class: gpr64 }
+  - { id: 97, class: gpr64 }
+  - { id: 98, class: gpr64 }
+  - { id: 99, class: gpr64 }
+  - { id: 100, class: gpr64 }
+  - { id: 101, class: gpr64all }
+  - { id: 102, class: gpr64all }
+  - { id: 103, class: gpr64all }
+  - { id: 104, class: gpr64all }
+liveins:
+  - { reg: '$x0', virtual-reg: '%0' }
+  - { reg: '$x1', virtual-reg: '%1' }
+  - { reg: '$w2', virtual-reg: '%2' }
+  - { reg: '$x3', virtual-reg: '%3' }
+  - { reg: '$x4', virtual-reg: '%4' }
+  - { reg: '$x5', virtual-reg: '%5' }
+  - { reg: '$w6', virtual-reg: '%6' }
+  - { reg: '$x7', virtual-reg: '%7' }
+frameInfo:
+  maxAlignment:    8
+  adjustsStack:    true
+  hasCalls:        true
+  maxCallFrameSize: 0
+fixedStack:
+  - { id: 0, offset: 88, size: 8, alignment: 8, isImmutable: true }
+  - { id: 1, offset: 80, size: 8, alignment: 16, isImmutable: true }
+  - { id: 2, offset: 72, size: 1, alignment: 8, isImmutable: true }
+  - { id: 3, offset: 64, size: 8, alignment: 16, isImmutable: true }
+  - { id: 4, offset: 56, size: 8, alignment: 8, isImmutable: true }
+  - { id: 5, offset: 48, size: 8, alignment: 16, isImmutable: true }
+  - { id: 6, offset: 40, size: 8, alignment: 8, isImmutable: true }
+  - { id: 7, offset: 32, size: 8, alignment: 16, isImmutable: true }
+  - { id: 8, offset: 24, size: 8, alignment: 8, isImmutable: true }
+  - { id: 9, offset: 16, size: 8, alignment: 16, isImmutable: true }
+  - { id: 10, offset: 8, size: 8, alignment: 8, isImmutable: true }
+  - { id: 11, size: 8, alignment: 16, isImmutable: true }
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $x0, $x1, $w2, $x3, $x4, $x5, $w6, $x7
+  
+    %7:gpr64 = COPY $x7
+    %6:gpr32 = COPY $w6
+    %5:gpr64 = COPY $x5
+    %4:gpr64 = COPY $x4
+    %3:gpr64 = COPY $x3
+    %2:gpr32 = COPY $w2
+    %1:gpr64 = COPY $x1
+    %0:gpr64 = COPY $x0
+    dead $xzr = ADDSXrr undef %11:gpr64, undef %12:gpr64, implicit-def $nzcv
+    %14:gpr64 = ADCSXr undef %15:gpr64, $xzr, implicit-def $nzcv, implicit $nzcv
+    %16:gpr64 = COPY $nzcv
+    dead $xzr = SUBSXri undef %18:gpr64sp, 1, 0, implicit-def $nzcv
+    undef %37.sub_32:gpr64 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
+    %20:gpr64 = CSINCXr %4, %4, 9, implicit $nzcv
+    %9:gpr64common = LDRXui %fixed-stack.10, 0 :: (load (s64) from %fixed-stack.10)
+    %30:gpr64 = LDRXui %fixed-stack.11, 0 :: (load (s64) from %fixed-stack.11, align 16)
+    dead $xzr = SUBSXri %9, 0, 0, implicit-def $nzcv
+    %22:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+    %23:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+    dead $xzr = ADDSXri undef %25:gpr64sp, 1, 0, implicit-def $nzcv
+    %8:gpr64 = LDRXui %fixed-stack.5, 0 :: (load (s64) from %fixed-stack.5, align 16)
+    %29:gpr64 = LDRXui %fixed-stack.4, 0 :: (load (s64) from %fixed-stack.4)
+    %26:gpr64common = ADCSXr %8, $xzr, implicit-def dead $nzcv, implicit $nzcv
+    dead $xzr = ADDSXri undef %28:gpr64sp, 1, 0, implicit-def $nzcv
+    %31:gpr64 = LDRXui %fixed-stack.3, 0 :: (load (s64) from %fixed-stack.3, align 16)
+    %33:gpr64 = LDRXui %fixed-stack.1, 0 :: (load (s64) from %fixed-stack.1, align 16)
+    %34:gpr64 = LDRXui %fixed-stack.0, 0 :: (load (s64) from %fixed-stack.0)
+    %35:gpr64common = LDRXui %fixed-stack.9, 0 :: (load (s64) from %fixed-stack.9, align 16)
+    %36:gpr64 = LDRXui %fixed-stack.8, 0 :: (load (s64) from %fixed-stack.8)
+    dead $xzr = ADCSXr undef %39:gpr64, $xzr, implicit-def $nzcv, implicit $nzcv
+    %41:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    dead $xzr = SUBSXrr undef %43:gpr64, %37, implicit-def $nzcv
+    %44:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+    %45:gpr64common = ADDSXrr undef %46:gpr64, %36, implicit-def $nzcv
+    %32:gpr64 = LDRXui %fixed-stack.7, 0 :: (load (s64) from %fixed-stack.7, align 16)
+    %86:gpr64 = LDRXui %fixed-stack.6, 0 :: (load (s64) from %fixed-stack.6)
+    %52:gpr64 = nuw MADDXrrr %34, %33, %32
+    %47:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    dead $xzr = SUBSXri %35, 0, 0, implicit-def $nzcv
+    undef %50.sub_32:gpr64 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+    %57:gpr64 = nuw MADDXrrr %50, %31, %32
+    dead $xzr = SUBSXrr %5, %4, implicit-def $nzcv
+    undef %54.sub_32:gpr64 = ORRWrr %41, %22
+    %55:gpr64 = nuw ADDXrr %52, %54
+    %59:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+    dead $xzr = SUBSXri %45, 0, 0, implicit-def $nzcv
+    %66:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+    undef %68.sub_32:gpr64 = ORRWrr %47, %66
+    dead $xzr = ADDSXrr %55, %68, implicit-def $nzcv
+    %72:gpr64 = nuw MADDXrrr %7, %30, %35
+    undef %61.sub_32:gpr64 = ORRWrr %59, %6
+    %63:gpr64common = ANDXri %61, 4096
+    %64:gpr64 = nuw ADDXrr %57, %63
+    %73:gpr64 = nuw ADDXrr %72, %29
+    %74:gpr64 = CSINCXr %64, %64, 1, implicit $nzcv
+    dead $xzr = SUBSXri %26, 0, 0, implicit-def $nzcv
+    %76:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+    undef %78.sub_32:gpr64 = ORRWrr %23, %76
+    dead $xzr = nuw ADDSXrr %73, %78, implicit-def $nzcv
+    %81:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+    dead $xzr = SUBSXrr %8, undef %83:gpr64, implicit-def $nzcv
+    CCMPXr %14, undef %84:gpr64, 0, 2, implicit-def $nzcv, implicit $nzcv
+    undef %88.sub_32:gpr64 = ORRWrr %44, %37.sub_32
+    undef %90.sub_32:gpr64 = ORRWrr %81, %6
+    %94:gpr64 = ADDXrr %36, %88
+    %95:gpr64 = ADDXrr %94, %74
+    %92:gpr64common = ANDXri %90, 4096
+    %96:gpr64 = ADDXrr %95, %92
+    undef %93.sub_32:gpr64 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+    $nzcv = COPY %16
+    %97:gpr64 = ADCSXr %93, %96, implicit-def dead $nzcv, implicit $nzcv
+    dead $xzr = SUBSXrr %20, %86, implicit-def $nzcv
+    %99:gpr64 = ADDXrr %97, %9
+    %100:gpr64 = CSINCXr %99, %99, 2, implicit $nzcv
+    ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+    $x0 = COPY %0
+    $x1 = COPY %1
+    $w2 = COPY %2
+    $x3 = COPY %3
+    BL @__bid128_mul, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $x1, implicit $w2, implicit $x3, implicit-def $sp, implicit-def dead $x0, implicit-def dead $x1
+    ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+    ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+    $x0 = COPY %0
+    $x1 = COPY %1
+    $x2 = COPY %100
+    $x3 = COPY $xzr
+    $w4 = COPY %2
+    $x5 = COPY %3
+    BL @__bid128_mul, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $w4, implicit $x5, implicit-def $sp, implicit-def dead $x0, implicit-def dead $x1
+    ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+    BRK 1
+
+...