diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4733,7 +4733,8 @@
   EVT MemVT =
       TLI.getMemValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
 
-  if (I.getAlign().value() < MemVT.getSizeInBits() / 8)
+  if (!TLI.supportsUnalignedAtomics() &&
+      I.getAlign().value() < MemVT.getSizeInBits() / 8)
     report_fatal_error("Cannot generate unaligned atomic store");
 
   auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());
diff --git a/llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll b/llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
rename from llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll
rename to llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
--- a/llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll
+++ b/llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mattr=addsubiw < %s -march=avr | FileCheck %s
 
-; This verifies that the middle end can handle an unaligned atomic load.
+; This verifies that the backend can handle an unaligned atomic load and store.
 ;
 ; In the past, an assertion inside the SelectionDAGBuilder would always
 ; hit an assertion for unaligned loads and stores.
@@ -14,6 +14,7 @@
 start:
   %a = getelementptr inbounds %AtomicI16, %AtomicI16* %self, i16 0, i32 0, i32 0
   load atomic i16, i16* %a seq_cst, align 1
+  store atomic i16 5, i16* %a seq_cst, align 1
   ret void
 }