Index: llvm/lib/CodeGen/MIRParser/MIParser.cpp
===================================================================
--- llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -2707,19 +2707,19 @@
     return true;
 
   uint32_t *Mask = MF.allocateRegMask();
-  while (true) {
-    if (Token.isNot(MIToken::NamedRegister))
-      return error("expected a named register");
-    Register Reg;
-    if (parseNamedRegister(Reg))
-      return true;
-    lex();
-    Mask[Reg / 32] |= 1U << (Reg % 32);
+  do {
+    if (Token.isNot(MIToken::rparen)) {
+      if (Token.isNot(MIToken::NamedRegister))
+        return error("expected a named register");
+      Register Reg;
+      if (parseNamedRegister(Reg))
+        return true;
+      lex();
+      Mask[Reg / 32] |= 1U << (Reg % 32);
+    }
+
     // TODO: Report an error if the same register is used more than once.
-    if (Token.isNot(MIToken::comma))
-      break;
-    lex();
-  }
+  } while (consumeIfPresent(MIToken::comma));
 
   if (expectAndConsume(MIToken::rparen))
     return true;
Index: llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
@@ -0,0 +1,18 @@
+# RUN: llc -march=amdgcn -run-pass=none -o - %s | FileCheck %s
+
+# Make sure there's no parse error on empty CustomRegMask or trailing comma
+
+# CHECK: $sgpr30_sgpr31 = SI_CALL %0, 0, CustomRegMask()
+# CHECK: $sgpr30_sgpr31 = SI_CALL %0, 0, CustomRegMask($vgpr0)
+
+---
+name: func
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr8_sgpr9
+    %0:sreg_64_xexec = COPY $sgpr8_sgpr9
+    $sgpr30_sgpr31 = SI_CALL %0, 0, CustomRegMask()
+    $sgpr30_sgpr31 = SI_CALL %0, 0, CustomRegMask($vgpr0,)
+    S_ENDPGM 0
+...