Index: llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
===================================================================
--- llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
+++ llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
@@ -18,7 +18,7 @@
 # RESULT-NEXT: %{{[0-9]+}}:_(s64) = G_IMPLICIT_DEF
 # RESULT-NEXT: %{{[0-9]+}}:vreg_64(s64) = IMPLICIT_DEF
 # RESULT-NEXT: %{{[0-9]+}}:_(<2 x s32>) = G_IMPLICIT_DEF
-# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %14(<2 x s32>)
+# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %{{[0-9]+}}(<2 x s32>)
 # RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu
 # RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF
 # RESULT-NEXT: G_STORE %{{[0-9]+}}(s32), %ptr(p1) :: (store (s32), addrspace 1)
Index: llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
===================================================================
--- llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
+++ llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
@@ -8,9 +8,9 @@
 
 # RESULT: bb.0:
 
-# RESULT: %3:vgpr_32 = IMPLICIT_DEF
-# RESULT-NEXT: %4:sreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %5:vreg_64 = IMPLICIT_DEF
+# RESULT: %{{[0-9]+}}:vgpr_32 = IMPLICIT_DEF
+# RESULT-NEXT: %{{[0-9]+}}:sreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %{{[0-9]+}}:vreg_64 = IMPLICIT_DEF
 # RESULT-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
 # RESULT-NEXT: S_BRANCH %bb.3
 
@@ -18,7 +18,7 @@
 # RESULT-NEXT: S_BRANCH %bb.3
 
 # RESULT: bb.2:
-# RESULT-NEXT: S_NOP 0, implicit %3, implicit killed %5, implicit %4
+# RESULT-NEXT: S_NOP 0, implicit %{{[0-9]+}}, implicit killed %{{[0-9]+}}, implicit %{{[0-9]+}}
 
 ---
 name: unreachable_block
Index: llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
===================================================================
--- llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
+++ llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
@@ -4,9 +4,9 @@
 
 # CHECK-INTERESTINGNESS: V_ADD_U32
 
-# RESULT: undef %2.sub1:vreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %3.sub0:vreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %1:vgpr_32 = V_ADD_U32_e32 %2.sub0, %2.sub1, implicit $exec
+# RESULT: undef %{{[0-9]+}}.sub1:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %{{[0-9]+}}.sub0:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %1:vgpr_32 = V_ADD_U32_e32 %{{[0-9]+}}.sub0, %{{[0-9]+}}.sub1, implicit $exec
 # RESULT-NEXT: S_ENDPGM 0, implicit %1
 
 ---
Index: llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
===================================================================
--- llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
+++ llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
@@ -5,10 +5,10 @@
 # CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec
 # CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 4, %{{[0-9]+}}.sub0, implicit $exec
 
-# RESULT: undef %2.sub1:vreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %0.sub0:vreg_64 = V_ADD_U32_e32 %2.sub1, %2.sub0, implicit $exec
-# RESULT-NEXT: %1.sub0:vreg_64 = V_ADD_U32_e32 4, %2.sub0, implicit $exec
-# RESULT-NEXT: S_ENDPGM 0, implicit %2, implicit %2.sub0
+# RESULT: undef %{{[0-9]+}}.sub1:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %0.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec
+# RESULT-NEXT: %1.sub0:vreg_64 = V_ADD_U32_e32 4, %{{[0-9]+}}.sub0, implicit $exec
+# RESULT-NEXT: S_ENDPGM 0, implicit %{{[0-9]+}}, implicit %{{[0-9]+}}.sub0
 ---
 name:            f
 tracksRegLiveness: true
Index: llvm/test/tools/llvm-reduce/remove-invoked-functions.ll
===================================================================
--- llvm/test/tools/llvm-reduce/remove-invoked-functions.ll
+++ llvm/test/tools/llvm-reduce/remove-invoked-functions.ll
@@ -18,7 +18,7 @@
 declare void @thrown()
 
 ; CHECK-INTERESTINGNESS: define void @caller(
-; CHECK-FINAL: define void @caller(i32 %arg)
+; CHECK-FINAL: define void @caller()
 define void @caller(i32 %arg) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
 ; CHECK-ALL: bb:
 bb:
Index: llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
===================================================================
--- llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
+++ llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
@@ -10,7 +10,7 @@
 declare void @f2()
 declare void @f3()
 
-; CHECK-FINAL-LABEL: define void @interesting(i32 %arg0, i32 %arg1, i32 %arg2) {
+; CHECK-FINAL-LABEL: define void @interesting(i32 %arg0, i32 %arg2) {
 ; CHECK-FINAL-NEXT:  entry:
 ; CHECK-FINAL-NEXT:    call void @f1() [ "bundle0"(), "align"(i32 %arg0), "whatever0"() ]
 ; CHECK-FINAL-NEXT:    call void @f2()
Index: llvm/tools/llvm-reduce/llvm-reduce.cpp
===================================================================
--- llvm/tools/llvm-reduce/llvm-reduce.cpp
+++ llvm/tools/llvm-reduce/llvm-reduce.cpp
@@ -89,8 +89,8 @@
 static cl::opt<int>
     MaxPassIterations("max-pass-iterations",
                       cl::desc("Maximum number of times to run the full set "
-                               "of delta passes (default=1)"),
-                      cl::init(1), cl::cat(LLVMReduceOptions));
+                               "of delta passes (default=5)"),
+                      cl::init(5), cl::cat(LLVMReduceOptions));
 
 static codegen::RegisterCodeGenFlags CGF;