Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3713,6 +3713,14 @@ } } + // Turn this into xor if N0 is 2^n-1 and the remaining high bits of N1 are + // known zero. + if (ConstantSDNode *C0 = isConstOrConstSplat(N0)) { + const APInt& C0Val = C0->getAPIntValue(); + if (C0Val.isMask() && (C0Val | DAG.computeKnownBits(N1).Zero).isAllOnes()) + return DAG.getNode(ISD::XOR, DL, VT, N1, N0); + } + return SDValue(); } Index: llvm/test/CodeGen/AArch64/sub1.ll =================================================================== --- llvm/test/CodeGen/AArch64/sub1.ll +++ llvm/test/CodeGen/AArch64/sub1.ll @@ -18,9 +18,8 @@ ; CHECK-LABEL: masked_sub_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #5 -; CHECK-NEXT: mov w9, #7 ; CHECK-NEXT: and w8, w0, w8 -; CHECK-NEXT: sub w0, w9, w8 +; CHECK-NEXT: eor w0, w8, #0x7 ; CHECK-NEXT: ret %a = and i8 %x, 5 %m = sub i8 7, %a @@ -43,9 +42,8 @@ ; CHECK-LABEL: masked_sub_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #9 -; CHECK-NEXT: mov w9, #31 ; CHECK-NEXT: and w8, w0, w8 -; CHECK-NEXT: sub w0, w9, w8 +; CHECK-NEXT: eor w0, w8, #0x1f ; CHECK-NEXT: ret %a = and i32 %x, 9 %m = sub i32 31, %a @@ -58,7 +56,7 @@ ; CHECK-NEXT: movi v1.4s, #42 ; CHECK-NEXT: movi v2.4s, #1, msl #8 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b -; CHECK-NEXT: sub v0.4s, v2.4s, v0.4s +; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b ; CHECK-NEXT: ret %a = and <4 x i32> %x, %m = sub <4 x i32> , %a Index: llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll +++ llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll @@ -109,26 +109,26 @@ ; CI-LABEL: add_x_shl_neg_to_sub_max_offset: ; CI: ; %bb.0: ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0 +; CI-NEXT: v_xor_b32_e32 v0, 0xffff, v0 ; CI-NEXT: v_mov_b32_e32 v1, 13 ; CI-NEXT: s_mov_b32 m0, -1 -; CI-NEXT: ds_write_b8 v0, v1 offset:65535 +; CI-NEXT: ds_write_b8 v0, v1 ; CI-NEXT: s_endpgm ; ; GFX9-LABEL: add_x_shl_neg_to_sub_max_offset: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0 +; GFX9-NEXT: v_xor_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_mov_b32_e32 v1, 13 -; GFX9-NEXT: ds_write_b8 v0, v1 offset:65535 +; GFX9-NEXT: ds_write_b8 v0, v1 ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: add_x_shl_neg_to_sub_max_offset: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, 13 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0, v0 -; GFX10-NEXT: ds_write_b8 v0, v1 offset:65535 +; GFX10-NEXT: v_xor_b32_e32 v0, 0xffff, v0 +; GFX10-NEXT: ds_write_b8 v0, v1 ; GFX10-NEXT: s_endpgm %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %neg = sub i32 0, %x.i Index: llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll +++ llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll @@ -15,10 +15,10 @@ ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: ds_read_b32 v0, v0 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; CHECK-NEXT: s_cmpk_lg_u32 vcc_lo, 0x0 -; CHECK-NEXT: s_subb_u32 s4, 1, 0 -; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, s4, vcc_lo +; CHECK-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo ; CHECK-NEXT: s_setpc_b64 s[30:31] bb: %i = load i32, i32 addrspace(3)* null, align 16 Index: llvm/test/CodeGen/ARM/intrinsics-overflow.ll =================================================================== --- llvm/test/CodeGen/ARM/intrinsics-overflow.ll +++ llvm/test/CodeGen/ARM/intrinsics-overflow.ll @@ -58,18 +58,18 @@ ; ARM: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] ; ARM: mov r[[R2:[0-9]+]], #0 ; ARM: adc r[[R0]], r[[R2]], #0 - ; ARM: rsb r[[R0]], r[[R0]], #1 + ; ARM: eor r[[R0]], r[[R0]], #1 ; THUMBV6: movs r[[R2:[0-9]+]], #0 ; THUMBV6: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] ; THUMBV6: adcs r[[R2]], r[[R2]] ; THUMBV6: movs r[[R0]], #1 - ; THUMBV6: subs r[[R0]], r[[R0]], r[[R2]] + ; THUMBV6: eors r[[R0]], r[[R2]] ; THUMBV7: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] ; THUMBV7: mov.w r[[R2:[0-9]+]], #0 ; THUMBV7: adc r[[R0]], r[[R2]], #0 - ; THUMBV7: rsb.w r[[R0]], r[[R0]], #1 + ; THUMBV7: eor r[[R0]], r[[R0]], #1 ; We should know that the overflow is just 1 bit, ; no need to clear any other bit Index: llvm/test/CodeGen/ARM/usub_sat.ll =================================================================== --- llvm/test/CodeGen/ARM/usub_sat.ll +++ llvm/test/CodeGen/ARM/usub_sat.ll @@ -48,7 +48,7 @@ ; CHECK-T1-NEXT: mov r0, r1 ; CHECK-T1-NEXT: adcs r0, r1 ; CHECK-T1-NEXT: movs r3, #1 -; CHECK-T1-NEXT: subs r3, r3, r0 +; CHECK-T1-NEXT: eors r3, r0 ; CHECK-T1-NEXT: mov r0, r1 ; CHECK-T1-NEXT: beq .LBB1_3 ; CHECK-T1-NEXT: @ %bb.1: @@ -70,7 +70,7 @@ ; CHECK-T2-NEXT: mov.w r12, #0 ; CHECK-T2-NEXT: sbcs r1, r3 ; CHECK-T2-NEXT: adc r2, r12, #0 -; CHECK-T2-NEXT: rsbs.w r2, r2, #1 +; CHECK-T2-NEXT: eors r2, r2, #1 ; CHECK-T2-NEXT: itt ne ; CHECK-T2-NEXT: movne r0, #0 ; CHECK-T2-NEXT: movne r1, #0 @@ -82,7 +82,7 @@ ; CHECK-ARM-NEXT: mov r12, #0 ; CHECK-ARM-NEXT: sbcs r1, r1, r3 ; CHECK-ARM-NEXT: adc r2, r12, #0 -; CHECK-ARM-NEXT: rsbs r2, r2, #1 +; CHECK-ARM-NEXT: eors r2, r2, #1 ; CHECK-ARM-NEXT: movwne r0, #0 ; CHECK-ARM-NEXT: movwne r1, #0 ; CHECK-ARM-NEXT: bx lr Index: llvm/test/CodeGen/ARM/usub_sat_plus.ll =================================================================== --- llvm/test/CodeGen/ARM/usub_sat_plus.ll +++ llvm/test/CodeGen/ARM/usub_sat_plus.ll @@ -54,7 +54,7 @@ ; CHECK-T1-NEXT: mov r0, r1 ; CHECK-T1-NEXT: adcs r0, r1 ; CHECK-T1-NEXT: movs r4, #1 -; CHECK-T1-NEXT: subs r4, r4, r0 +; CHECK-T1-NEXT: eors r4, r0 ; CHECK-T1-NEXT: mov r0, r1 ; CHECK-T1-NEXT: beq .LBB1_3 ; CHECK-T1-NEXT: @ %bb.1: @@ -77,7 +77,7 @@ ; CHECK-T2-NEXT: subs r0, r0, r2 ; CHECK-T2-NEXT: sbcs r1, r3 ; CHECK-T2-NEXT: adc r2, r12, #0 -; CHECK-T2-NEXT: rsbs.w r2, r2, #1 +; CHECK-T2-NEXT: eors r2, r2, #1 ; CHECK-T2-NEXT: itt ne ; CHECK-T2-NEXT: movne r0, #0 ; CHECK-T2-NEXT: movne r1, #0 @@ -91,7 +91,7 @@ ; CHECK-ARM-NEXT: subs r0, r0, r2 ; CHECK-ARM-NEXT: sbcs r1, r1, r3 ; CHECK-ARM-NEXT: adc r2, r12, #0 -; CHECK-ARM-NEXT: rsbs r2, r2, #1 +; CHECK-ARM-NEXT: eors r2, r2, #1 ; CHECK-ARM-NEXT: movwne r0, #0 ; CHECK-ARM-NEXT: movwne r1, #0 ; CHECK-ARM-NEXT: bx lr Index: llvm/test/CodeGen/PowerPC/select_const.ll =================================================================== --- llvm/test/CodeGen/PowerPC/select_const.ll +++ llvm/test/CodeGen/PowerPC/select_const.ll @@ -495,7 +495,7 @@ ; ALL-LABEL: sel_constants_urem_constant: ; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 -; ALL-NEXT: subfic 3, 3, 3 +; ALL-NEXT: xori 3, 3, 3 ; ALL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 %bo = urem i8 %sel, 5 Index: llvm/test/CodeGen/SPARC/64bit.ll =================================================================== --- llvm/test/CodeGen/SPARC/64bit.ll +++ llvm/test/CodeGen/SPARC/64bit.ll @@ -238,8 +238,8 @@ declare void @g(i8*) ; CHECK: expand_setcc -; CHECK: cmp %i0, 1 -; CHECK: movl %xcc, 1, +; CHECK: cmp %i0, 0 +; CHECK: movg %xcc, 1, %i1 define i32 @expand_setcc(i64 %a) { %cond = icmp sle i64 %a, 0 %cast2 = zext i1 %cond to i32