diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3213,6 +3213,28 @@
   defm SQXTUNT_ZZ : sve2_int_sat_extract_narrow_top<0b10, "sqxtunt", int_aarch64_sve_sqxtunt>;
 } // End HasSVE2orSME
 
+let Predicates = [HasSVE2orSME] in {
+  multiclass sraPat<ValueType Ty, ValueType PredTy, ValueType ShiftTy,
+                    ComplexPattern cast, SDPatternOperator shift,
+                    Instruction DestAdrIns> {
+    def : Pat<(add Ty:$Op1,
+                  (Ty (shift (PredTy (SVEAllActive)),
+                                    Ty:$Op2,
+                                    (Ty (AArch64dup (ShiftTy (cast i32:$Op3))))))),
+              (DestAdrIns $Op1, $Op2, i32:$Op3)>;
+  }
+
+  defm : sraPat<nxv2i64, nxv2i1, i64, SVEShiftImmR64, AArch64lsr_p, USRA_ZZI_D>;
+  defm : sraPat<nxv4i32, nxv4i1, i32, SVEShiftImmR32, AArch64lsr_p, USRA_ZZI_S>;
+  defm : sraPat<nxv8i16, nxv8i1, i32, SVEShiftImmR16, AArch64lsr_p, USRA_ZZI_H>;
+  defm : sraPat<nxv16i8, nxv16i1, i32, SVEShiftImmR8, AArch64lsr_p, USRA_ZZI_B>;
+
+  defm : sraPat<nxv2i64, nxv2i1, i64, SVEShiftImmR64, AArch64asr_p, SSRA_ZZI_D>;
+  defm : sraPat<nxv4i32, nxv4i1, i32, SVEShiftImmR32, AArch64asr_p, SSRA_ZZI_S>;
+  defm : sraPat<nxv8i16, nxv8i1, i32, SVEShiftImmR16, AArch64asr_p, SSRA_ZZI_H>;
+  defm : sraPat<nxv16i8, nxv16i1, i32, SVEShiftImmR8, AArch64asr_p, SSRA_ZZI_B>;
+}
+
 let Predicates = [HasSVE2] in {
   // SVE2 character match
   defm MATCH_PPzZZ  : sve2_char_match<0b0, "match",  int_aarch64_sve_match>;
diff --git a/llvm/test/CodeGen/AArch64/sve2-add-shift-to-sra.ll b/llvm/test/CodeGen/AArch64/sve2-add-shift-to-sra.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve2-add-shift-to-sra.ll
@@ -0,0 +1,106 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; USRA
+
+define <vscale x 16 x i8> @usra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
+; CHECK-LABEL: usra_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    usra z0.b, z1.b, #1
+; CHECK-NEXT:    ret
+  %ins = insertelement <vscale x 16 x i8> poison, i8 1, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
+  %shift = lshr <vscale x 16 x i8> %b, %splat
+  %add = add <vscale x 16 x i8> %a, %shift
+  ret <vscale x 16 x i8> %add
+}
+
+define <vscale x 8 x i16> @usra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
+; CHECK-LABEL: usra_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    usra z0.h, z1.h, #2
+; CHECK-NEXT:    ret
+  %ins = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
+  %shift = lshr <vscale x 8 x i16> %b, %splat
+  %add = add <vscale x 8 x i16> %a, %shift
+  ret <vscale x 8 x i16> %add
+}
+
+define <vscale x 4 x i32> @usra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
+; CHECK-LABEL: usra_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    usra z0.s, z1.s, #3
+; CHECK-NEXT:    ret
+  %ins = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+  %shift = lshr <vscale x 4 x i32> %b, %splat
+  %add = add <vscale x 4 x i32> %a, %shift
+  ret <vscale x 4 x i32> %add
+}
+
+define <vscale x 2 x i64> @usra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
+; CHECK-LABEL: usra_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    usra z0.d, z1.d, #4
+; CHECK-NEXT:    ret
+  %ins = insertelement <vscale x 2 x i64> poison, i64 4, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
+  %shift = lshr <vscale x 2 x i64> %b, %splat
+  %add = add <vscale x 2 x i64> %a, %shift
+  ret <vscale x 2 x i64> %add
+}
+
+; SSRA
+
+define <vscale x 16 x i8> @ssra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
+; CHECK-LABEL: ssra_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ssra z0.b, z1.b, #1
+; CHECK-NEXT:    ret
+  %ins = insertelement <vscale x 16 x i8> poison, i8 1, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
+  %shift = ashr <vscale x 16 x i8> %b, %splat
+  %add = add <vscale x 16 x i8> %a, %shift
+  ret <vscale x 16 x i8> %add
+}
+
+define <vscale x 8 x i16> @ssra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
+; CHECK-LABEL: ssra_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ssra z0.h, z1.h, #2
+; CHECK-NEXT:    ret
+  %ins = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
+  %shift = ashr <vscale x 8 x i16> %b, %splat
+  %add = add <vscale x 8 x i16> %a, %shift
+  ret <vscale x 8 x i16> %add
+}
+
+define <vscale x 4 x i32> @ssra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
+; CHECK-LABEL: ssra_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ssra z0.s, z1.s, #3
+; CHECK-NEXT:    ret
+  %ins = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+  %shift = ashr <vscale x 4 x i32> %b, %splat
+  %add = add <vscale x 4 x i32> %a, %shift
+  ret <vscale x 4 x i32> %add
+}
+
+define <vscale x 2 x i64> @ssra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
+; CHECK-LABEL: ssra_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ssra z0.d, z1.d, #4
+; CHECK-NEXT:    ret
+  %ins = insertelement <vscale x 2 x i64> poison, i64 4, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
+  %shift = ashr <vscale x 2 x i64> %b, %splat
+  %add = add <vscale x 2 x i64> %a, %shift
+  ret <vscale x 2 x i64> %add
+}
+
+attributes #0 = { "target-features"="+sve,+sve2" }