diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -556,6 +556,15 @@
   FeatureSpecRestrict
   ]>;
 
+// Only available to disassemblers.
+def FeatureAll
+    : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", [
+      HasV9_3aOps, FeatureCrypto, FeatureETE, FeatureFP16FML, FeatureMTE,
+      FeatureMatMulFP32, FeatureMatMulFP64, FeaturePerfMon, FeatureRandGen,
+      FeatureRME, FeatureSMEF64, FeatureSMEI64, FeatureSPE, FeatureSVE2AES,
+      FeatureSVE2BitPerm, FeatureSVE2SM4, FeatureSVE2SHA3
+    ]>;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/AArch64/mattr-all.ll b/llvm/test/CodeGen/AArch64/mattr-all.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/mattr-all.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+all < %s | FileCheck %s
+
+define <vscale x 16 x i8> @sve_aesd(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {
+; CHECK-LABEL: sve_aesd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    aesd z0.b, z0.b, z1.b
+; CHECK-NEXT:    ret
+  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> %a,
+                                                        <vscale x 16 x i8> %b)
+  ret <vscale x 16 x i8> %out
+}
+
+define half @bf16() nounwind {
+; CHECK-LABEL: bf16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi d0, #0000000000000000
+; CHECK-NEXT:    ret
+  ret half 0xH0000
+}
+
+define i64 @perfmon() nounwind {
+; CHECK-LABEL: perfmon:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mrs x0, PMCCNTR_EL0
+; CHECK-NEXT:    ret
+  %tmp0 = call i64 @llvm.readcyclecounter()
+  ret i64 %tmp0
+}
+
+declare <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8>, <vscale x 16 x i8>)
+declare i64 @llvm.readcyclecounter()
diff --git a/llvm/test/MC/AArch64/armv8.6a-bf16.s b/llvm/test/MC/AArch64/armv8.6a-bf16.s
--- a/llvm/test/MC/AArch64/armv8.6a-bf16.s
+++ b/llvm/test/MC/AArch64/armv8.6a-bf16.s
@@ -1,5 +1,6 @@
 // RUN:     llvm-mc -triple aarch64 -show-encoding  -mattr=+bf16 < %s       | FileCheck %s
 // RUN:     llvm-mc -triple aarch64 -show-encoding  -mattr=+v8.6a < %s      | FileCheck %s
+// RUN:     llvm-mc -triple aarch64 -show-encoding  -mattr=+all %s          | FileCheck %s
 // RUN: not llvm-mc -triple aarch64 -show-encoding  -mattr=-bf16  < %s 2>&1 | FileCheck %s --check-prefix=NOBF16
 // RUN: not llvm-mc -triple aarch64 -show-encoding  < %s 2>&1 | FileCheck %s --check-prefix=NOBF16
 
diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s b/llvm/test/MC/AArch64/directive-arch_extension.s
--- a/llvm/test/MC/AArch64/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension.s
@@ -1,5 +1,7 @@
 // RUN: llvm-mc -triple aarch64 -filetype asm -o - %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 --defsym err=1 %s 2>&1 | FileCheck %s --check-prefix=ERR
 
+.ifndef err
 .arch_extension crc
 crc32cx w0, w1, x3
 // CHECK: crc32cx w0, w1, x3
@@ -92,3 +94,8 @@
 .arch_extension mops
 cpyfp [x0]!, [x1]!, x2!
 // CHECK: cpyfp [x0]!, [x1]!, x2!
+.else
+
+.arch_extension all
+// ERR: :[[#@LINE-1]]:17: error: unknown architectural extension: all
+.endif
diff --git a/llvm/test/MC/Disassembler/AArch64/mattr-all.txt b/llvm/test/MC/Disassembler/AArch64/mattr-all.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/mattr-all.txt
@@ -0,0 +1,33 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+all -disassemble %s 2>&1 | FileCheck %s
+
+## aes
+# CHECK: aese v0.16b, v1.16b
+[0x20,0x48,0x28,0x4e]
+
+## ete
+# CHECK: mrs x0, TRCRSR
+[0x00,0x0a,0x31,0xd5]
+
+## fp16fml
+# CHECK: fmlal v0.2s, v1.2h, v2.2h
+[0x20,0xec,0x22,0x0e]
+
+## armv8.5a mte
+# CHECK: irg x0, x1
+[0x20,0x10,0xdf,0x9a]
+
+## armv8.5a rand
+# CHECK: mrs x0, RNDR
+[0x00,0x24,0x3b,0xd5]
+
+## armv8.6a matmul
+# CHECK: smmla v1.4s, v16.16b, v31.16b
+[0x01,0xa6,0x9f,0x4e]
+
+## armv8.8a-hbc
+# CHECK: bc.eq #4
+[0x30,0x00,0x00,0x54]
+
+## armv9a rme
+# CHECK: mrs x0, MFAR_EL3
+[0xa0,0x60,0x3e,0xd5]