diff --git a/bolt/lib/Core/BinaryContext.cpp b/bolt/lib/Core/BinaryContext.cpp --- a/bolt/lib/Core/BinaryContext.cpp +++ b/bolt/lib/Core/BinaryContext.cpp @@ -124,8 +124,7 @@ break; case llvm::Triple::aarch64: ArchName = "aarch64"; - FeaturesStr = "+fp-armv8,+neon,+crypto,+dotprod,+crc,+lse,+ras,+rdm," - "+fullfp16,+spe,+fuse-aes,+rcpc"; + FeaturesStr = "+all"; break; default: return createStringError(std::errc::not_supported, diff --git a/lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp b/lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp --- a/lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp +++ b/lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp @@ -1179,16 +1179,9 @@ features_str += "+dspr2,"; } - // If any AArch64 variant, enable latest ISA with all extensions. + // If any AArch64 variant, enable all features. if (triple.isAArch64()) { - features_str += "+v9.3a,"; - std::vector features; - // Get all possible features - llvm::AArch64::getExtensionFeatures(-1, features); - features_str += llvm::join(features, ","); - - if (triple.getVendor() == llvm::Triple::Apple) - cpu = "apple-latest"; + features_str += "+all"; } if (triple.isRISCV()) { diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp --- a/llvm/lib/MC/MCSubtargetInfo.cpp +++ b/llvm/lib/MC/MCSubtargetInfo.cpp @@ -198,6 +198,8 @@ Help(ProcDesc, ProcFeatures); else if (Feature == "+cpuhelp") cpuHelp(ProcDesc); + else if (Feature == "+all") + Bits.set(); else ApplyFeatureFlag(Bits, Feature, ProcFeatures); } diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -1693,6 +1693,10 @@ if (!MAttrs.empty()) for (unsigned I = 0; I != MAttrs.size(); ++I) Features.AddFeature(MAttrs[I]); + else { + if (Obj->getArch() == llvm::Triple::aarch64) + Features.AddFeature("+all"); + } std::unique_ptr MRI( TheTarget->createMCRegInfo(TripleName));