diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -3850,6 +3850,22 @@ if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg()) return Warning(Ops[0]->getStartLoc(), "Destination register should be " "distinct from source registers"); + } else if (isV4FMADDPS(Opcode) || isV4FMADDSS(Opcode) || + isV4FNMADDPS(Opcode) || isV4FNMADDSS(Opcode) || + isVP4DPWSSDS(Opcode) || isVP4DPWSSD(Opcode)) { + unsigned Src2 = Inst.getOperand(Inst.getNumOperands() - + X86::AddrNumOperands - 1).getReg(); + unsigned Src2Enc = MRI->getEncodingValue(Src2); + if (Src2Enc % 4 != 0) { + StringRef RegName = X86IntelInstPrinter::getRegisterName(Src2); + unsigned GroupStart = (Src2Enc / 4) * 4; + unsigned GroupEnd = GroupStart + 3; + return Warning(Ops[0]->getStartLoc(), + "source register '" + RegName + "' implicitly denotes '" + + RegName.take_front(3) + Twine(GroupStart) + "' to '" + + RegName.take_front(3) + Twine(GroupEnd) + + "' source group"); + } } switch (Inst.getOpcode()) { @@ -3910,39 +3926,6 @@ "should be distinct"); break; } - case X86::V4FMADDPSrm: - case X86::V4FMADDPSrmk: - case X86::V4FMADDPSrmkz: - case X86::V4FMADDSSrm: - case X86::V4FMADDSSrmk: - case X86::V4FMADDSSrmkz: - case X86::V4FNMADDPSrm: - case X86::V4FNMADDPSrmk: - case X86::V4FNMADDPSrmkz: - case X86::V4FNMADDSSrm: - case X86::V4FNMADDSSrmk: - case X86::V4FNMADDSSrmkz: - case X86::VP4DPWSSDSrm: - case X86::VP4DPWSSDSrmk: - case X86::VP4DPWSSDSrmkz: - case X86::VP4DPWSSDrm: - case X86::VP4DPWSSDrmk: - case X86::VP4DPWSSDrmkz: { - unsigned Src2 = Inst.getOperand(Inst.getNumOperands() - - X86::AddrNumOperands - 1).getReg(); - unsigned Src2Enc = MRI->getEncodingValue(Src2); - if (Src2Enc % 4 != 0) { - StringRef RegName = X86IntelInstPrinter::getRegisterName(Src2); - unsigned GroupStart = (Src2Enc / 4) * 4; - unsigned GroupEnd = GroupStart + 3; - return Warning(Ops[0]->getStartLoc(), - "source register '" + RegName + "' implicitly denotes '" + - RegName.take_front(3) + Twine(GroupStart) + "' to '" + - RegName.take_front(3) + Twine(GroupEnd) + - "' source group"); - } - break; - } } const MCInstrDesc &MCID = MII.get(Inst.getOpcode());