diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -314,10 +314,16 @@
     assert(LMUL == 1 && "LMUL must be 1, 2, or 4.");
 
   for (unsigned I = 0; I < NF; ++I) {
+    // Adding implicit-use of super register to describe we are using part of
+    // super register, that prevent machine verifier complain when part of
+    // subreg is undef, see comment in MachineVerifier::checkLiveness for more
+    // detail.
     BuildMI(MBB, MBBI, DL, TII->get(Opcode))
         .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
         .addReg(Base)
-        .addMemOperand(*(MBBI->memoperands_begin()));
+        .addMemOperand(*(MBBI->memoperands_begin()))
+        .add(
+            MachineOperand::CreateReg(SrcReg, /*isDef=*/false, /*isImp=*/true));
     if (I != NF - 1)
       BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)
           .addReg(Base)
diff --git a/llvm/test/CodeGen/RISCV/undef-subreg-range.mir b/llvm/test/CodeGen/RISCV/undef-subreg-range.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/undef-subreg-range.mir
@@ -0,0 +1,260 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -O2 -mtriple riscv64 -riscv-enable-subreg-liveness \
+# RUN:     -verify-machineinstrs -run-pass=riscv-expand-pseudo -o - 2>&1 \
+# RUN:     | FileCheck %s
+--- |
+  ; ModuleID = '/scratch1/kitoc/llvm-workspace/llvm-project/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll'
+  source_filename = "/scratch1/kitoc/llvm-workspace/llvm-project/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll"
+  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+  target triple = "riscv64"
+
+  @var_47 = dso_local global [2 x i16] [i16 -32732, i16 19439], align 2
+  @__const._Z3foov.var_49 = private unnamed_addr constant [2 x i16] [i16 157, i16 24062], align 2
+  @__const._Z3foov.var_48 = private unnamed_addr constant [2 x i8] c"\AEN", align 1
+  @__const._Z3foov.var_46 = private unnamed_addr constant [2 x i16] [i16 729, i16 -32215], align 2
+  @__const._Z3foov.var_45 = private unnamed_addr constant [2 x i16] [i16 -27462, i16 -1435], align 2
+  @__const._Z3foov.var_44 = private unnamed_addr constant [2 x i16] [i16 22611, i16 -18435], align 2
+  @__const._Z3foov.var_40 = private unnamed_addr constant [2 x i16] [i16 -19932, i16 -26252], align 2
+
+  define void @_Z3foov() #0 {
+  entry:
+    %0 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, ptr nonnull @__const._Z3foov.var_49, i64 2)
+    %1 = tail call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.i64(<vscale x 8 x i8> undef, ptr nonnull @__const._Z3foov.var_48, i64 2)
+    %2 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, ptr nonnull @__const._Z3foov.var_46, i64 2)
+    %3 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, ptr nonnull @__const._Z3foov.var_45, i64 2)
+    tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
+    %4 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, ptr nonnull @__const._Z3foov.var_44, i64 2)
+    %5 = tail call i64 @llvm.riscv.vsetvli.i64(i64 2, i64 1, i64 1)
+    %6 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, ptr nonnull @__const._Z3foov.var_40, i64 2)
+    %7 = tail call i64 @llvm.riscv.vsetvli.i64(i64 2, i64 1, i64 1)
+    %8 = tail call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i16.i16.i64(<vscale x 8 x i16> %6, i16 -15456, i64 2)
+    %9 = tail call i64 @llvm.riscv.vsetvli.i64(i64 2, i64 1, i64 1)
+    %10 = tail call <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %8, i64 2, i64 0)
+    tail call void @llvm.riscv.vsseg4.nxv8i16.i64(<vscale x 8 x i16> %10, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, <vscale x 8 x i16> %4, ptr nonnull @var_47, i64 2)
+    ret void
+  }
+
+  ; Function Attrs: nounwind readonly
+  declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16>, ptr nocapture, i64) #1
+
+  ; Function Attrs: nounwind readonly
+  declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.i64(<vscale x 8 x i8>, ptr nocapture, i64) #1
+
+  ; Function Attrs: nounwind
+  declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #2
+
+  ; Function Attrs: nounwind readnone
+  declare <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i16.i16.i64(<vscale x 8 x i16>, i16, i64) #3
+
+  ; Function Attrs: nounwind readnone
+  declare <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #3
+
+  ; Function Attrs: nounwind writeonly
+  declare void @llvm.riscv.vsseg4.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, ptr nocapture, i64) #4
+
+  attributes #0 = { "target-features"="+v,+m,+zbb" }
+  attributes #1 = { nounwind readonly "target-features"="+v,+m,+zbb" }
+  attributes #2 = { nounwind "target-features"="+v,+m,+zbb" }
+  attributes #3 = { nounwind readnone "target-features"="+v,+m,+zbb" }
+  attributes #4 = { nounwind writeonly "target-features"="+v,+m,+zbb" }
+
+...
+---
+name:            _Z3foov
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+callsEHReturn:   false
+callsUnwindInit: false
+hasEHCatchret:   false
+hasEHScopes:     false
+hasEHFunclets:   false
+failsVerification: false
+tracksDebugUserValues: true
+registers:       []
+liveins:         []
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       16
+  offsetAdjustment: 0
+  maxAlignment:    16
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  functionContext: ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -80, size: 64, alignment: 8,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: default, offset: -8, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 3, name: '', type: default, offset: -16, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo:
+  varArgsFrameIndex: 0
+  varArgsSaveSize: 0
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: _Z3foov
+    ; CHECK: $x2 = frame-setup ADDI $x2, -16
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB
+    ; CHECK-NEXT: $x11 = frame-setup ADDI killed $x0, 10
+    ; CHECK-NEXT: $x10 = frame-setup MUL killed $x10, killed $x11
+    ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10
+    ; CHECK-NEXT: renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_49
+    ; CHECK-NEXT: renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_49
+    ; CHECK-NEXT: dead $x0 = VSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vtype, implicit-def $vl
+    ; CHECK-NEXT: renamable $v8m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_48
+    ; CHECK-NEXT: renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_48
+    ; CHECK-NEXT: renamable $v10 = PseudoVLE8_V_M1 killed renamable $x10, 2, 3 /* e8 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $x10 = PseudoReadVLENB
+    ; CHECK-NEXT: $x10 = SLLI killed $x10, 3
+    ; CHECK-NEXT: $x10 = ADD $x2, killed $x10
+    ; CHECK-NEXT: $x10 = ADDI $x10, 16
+    ; CHECK-NEXT: PseudoVSPILL_M1 killed renamable $v10, killed $x10 :: (store unknown-size into %stack.0, align 8)
+    ; CHECK-NEXT: renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_46
+    ; CHECK-NEXT: renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_46
+    ; CHECK-NEXT: renamable $v10m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_45
+    ; CHECK-NEXT: renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_45
+    ; CHECK-NEXT: renamable $v12m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $x10 = ADDI $x2, 16
+    ; CHECK-NEXT: $x11 = PseudoReadVLENB
+    ; CHECK-NEXT: $x11 = SLLI $x11, 1
+    ; CHECK-NEXT: VS2R_V $v8m2, $x10, implicit $v8m2_v10m2_v12m2_v14m2 :: (store unknown-size into %stack.1, align 8)
+    ; CHECK-NEXT: $x10 = ADD $x10, $x11
+    ; CHECK-NEXT: VS2R_V $v10m2, $x10, implicit $v8m2_v10m2_v12m2_v14m2 :: (store unknown-size into %stack.1, align 8)
+    ; CHECK-NEXT: $x10 = ADD $x10, $x11
+    ; CHECK-NEXT: VS2R_V $v12m2, $x10, implicit $v8m2_v10m2_v12m2_v14m2 :: (store unknown-size into %stack.1, align 8)
+    ; CHECK-NEXT: $x10 = ADD $x10, $x11
+    ; CHECK-NEXT: VS2R_V $v14m2, $x10, implicit $v8m2_v10m2_v12m2_v14m2 :: (store unknown-size into %stack.1, align 8)
+    ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $v0, 12 /* clobber */, implicit-def dead early-clobber $v1, 12 /* clobber */, implicit-def dead early-clobber $v2, 12 /* clobber */, implicit-def dead early-clobber $v3, 12 /* clobber */, implicit-def dead early-clobber $v4, 12 /* clobber */, implicit-def dead early-clobber $v5, 12 /* clobber */, implicit-def dead early-clobber $v6, 12 /* clobber */, implicit-def dead early-clobber $v7, 12 /* clobber */, implicit-def dead early-clobber $v8, 12 /* clobber */, implicit-def dead early-clobber $v9, 12 /* clobber */, implicit-def dead early-clobber $v10, 12 /* clobber */, implicit-def dead early-clobber $v11, 12 /* clobber */, implicit-def dead early-clobber $v12, 12 /* clobber */, implicit-def dead early-clobber $v13, 12 /* clobber */, implicit-def dead early-clobber $v14, 12 /* clobber */, implicit-def dead early-clobber $v15, 12 /* clobber */, implicit-def dead early-clobber $v16, 12 /* clobber */, implicit-def dead early-clobber $v17, 12 /* clobber */, implicit-def dead early-clobber $v18, 12 /* clobber */, implicit-def dead early-clobber $v19, 12 /* clobber */, implicit-def dead early-clobber $v20, 12 /* clobber */, implicit-def dead early-clobber $v21, 12 /* clobber */, implicit-def dead early-clobber $v22, 12 /* clobber */, implicit-def dead early-clobber $v23, 12 /* clobber */, implicit-def dead early-clobber $v24, 12 /* clobber */, implicit-def dead early-clobber $v25, 12 /* clobber */, implicit-def dead early-clobber $v26, 12 /* clobber */, implicit-def dead early-clobber $v27, 12 /* clobber */, implicit-def dead early-clobber $v28, 12 /* clobber */, implicit-def dead early-clobber $v29, 12 /* clobber */, implicit-def dead early-clobber $v30, 12 /* clobber */, implicit-def dead early-clobber $v31
+    ; CHECK-NEXT: renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_44
+    ; CHECK-NEXT: renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_44
+    ; CHECK-NEXT: dead $x0 = VSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vtype, implicit-def $vl
+    ; CHECK-NEXT: $x11 = ADDI $x2, 16
+    ; CHECK-NEXT: $x12 = PseudoReadVLENB
+    ; CHECK-NEXT: $x12 = SLLI $x12, 1
+    ; CHECK-NEXT: $v10m2 = VL2RE8_V $x11 :: (load unknown-size from %stack.1, align 8)
+    ; CHECK-NEXT: $x11 = ADD $x11, $x12
+    ; CHECK-NEXT: $v12m2 = VL2RE8_V $x11 :: (load unknown-size from %stack.1, align 8)
+    ; CHECK-NEXT: $x11 = ADD $x11, $x12
+    ; CHECK-NEXT: $v14m2 = VL2RE8_V $x11 :: (load unknown-size from %stack.1, align 8)
+    ; CHECK-NEXT: $x11 = ADD $x11, $x12
+    ; CHECK-NEXT: $v16m2 = VL2RE8_V $x11 :: (load unknown-size from %stack.1, align 8)
+    ; CHECK-NEXT: renamable $v16m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $x0 = VSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vtype, implicit-def $vl
+    ; CHECK-NEXT: renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_40
+    ; CHECK-NEXT: renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_40
+    ; CHECK-NEXT: renamable $v8m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $x0 = VSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vtype, implicit-def $vl
+    ; CHECK-NEXT: renamable $x10 = LUI 1048572
+    ; CHECK-NEXT: renamable $x10 = ADDIW killed renamable $x10, 928
+    ; CHECK-NEXT: early-clobber renamable $v0 = PseudoVMSBC_VX_M2 killed renamable $v8m2, killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $x0 = VSETIVLI 2, 9 /* e16, m2, tu, mu */, implicit-def $vtype, implicit-def $vl
+    ; CHECK-NEXT: $x10 = PseudoReadVLENB
+    ; CHECK-NEXT: $x10 = SLLI killed $x10, 3
+    ; CHECK-NEXT: $x10 = ADD $x2, killed $x10
+    ; CHECK-NEXT: $x10 = ADDI $x10, 16
+    ; CHECK-NEXT: renamable $v8 = PseudoVRELOAD_M1 killed $x10 :: (load unknown-size from %stack.0, align 8)
+    ; CHECK-NEXT: early-clobber renamable $v10m2 = PseudoVSEXT_VF2_M2_MASK renamable $v10m2, killed renamable $v8, $v0, 2, 4 /* e16 */, 0, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: renamable $x10 = LUI target-flags(riscv-hi) @var_47
+    ; CHECK-NEXT: renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @var_47
+    ; CHECK-NEXT: PseudoVSSEG4E16_V_M2 killed renamable $v10m2_v12m2_v14m2_v16m2, killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB
+    ; CHECK-NEXT: $x11 = frame-destroy ADDI killed $x0, 10
+    ; CHECK-NEXT: $x10 = frame-destroy MUL killed $x10, killed $x11
+    ; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10
+    ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16
+    ; CHECK-NEXT: PseudoRET
+    $x2 = frame-setup ADDI $x2, -16
+    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    $x10 = frame-setup PseudoReadVLENB
+    $x11 = frame-setup ADDI killed $x0, 10
+    $x10 = frame-setup MUL killed $x10, killed $x11
+    $x2 = frame-setup SUB $x2, killed $x10
+    renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_49
+    renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_49
+    dead $x0 = PseudoVSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
+    renamable $v8m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_48
+    renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_48
+    renamable $v10 = PseudoVLE8_V_M1 killed renamable $x10, 2, 3 /* e8 */, implicit $vl, implicit $vtype
+    $x10 = PseudoReadVLENB
+    $x10 = SLLI killed $x10, 3
+    $x10 = ADD $x2, killed $x10
+    $x10 = ADDI $x10, 16
+    PseudoVSPILL_M1 killed renamable $v10, killed $x10 :: (store unknown-size into %stack.0, align 8)
+    renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_46
+    renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_46
+    renamable $v10m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_45
+    renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_45
+    renamable $v12m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    $x10 = ADDI $x2, 16
+    $x11 = PseudoReadVLENB
+    $x11 = SLLI $x11, 1
+    PseudoVSPILL4_M2 renamable $v8m2_v10m2_v12m2_v14m2, killed $x10, killed $x11 :: (store unknown-size into %stack.1, align 8)
+    INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $v0, 12 /* clobber */, implicit-def dead early-clobber $v1, 12 /* clobber */, implicit-def dead early-clobber $v2, 12 /* clobber */, implicit-def dead early-clobber $v3, 12 /* clobber */, implicit-def dead early-clobber $v4, 12 /* clobber */, implicit-def dead early-clobber $v5, 12 /* clobber */, implicit-def dead early-clobber $v6, 12 /* clobber */, implicit-def dead early-clobber $v7, 12 /* clobber */, implicit-def dead early-clobber $v8, 12 /* clobber */, implicit-def dead early-clobber $v9, 12 /* clobber */, implicit-def dead early-clobber $v10, 12 /* clobber */, implicit-def dead early-clobber $v11, 12 /* clobber */, implicit-def dead early-clobber $v12, 12 /* clobber */, implicit-def dead early-clobber $v13, 12 /* clobber */, implicit-def dead early-clobber $v14, 12 /* clobber */, implicit-def dead early-clobber $v15, 12 /* clobber */, implicit-def dead early-clobber $v16, 12 /* clobber */, implicit-def dead early-clobber $v17, 12 /* clobber */, implicit-def dead early-clobber $v18, 12 /* clobber */, implicit-def dead early-clobber $v19, 12 /* clobber */, implicit-def dead early-clobber $v20, 12 /* clobber */, implicit-def dead early-clobber $v21, 12 /* clobber */, implicit-def dead early-clobber $v22, 12 /* clobber */, implicit-def dead early-clobber $v23, 12 /* clobber */, implicit-def dead early-clobber $v24, 12 /* clobber */, implicit-def dead early-clobber $v25, 12 /* clobber */, implicit-def dead early-clobber $v26, 12 /* clobber */, implicit-def dead early-clobber $v27, 12 /* clobber */, implicit-def dead early-clobber $v28, 12 /* clobber */, implicit-def dead early-clobber $v29, 12 /* clobber */, implicit-def dead early-clobber $v30, 12 /* clobber */, implicit-def dead early-clobber $v31
+    renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_44
+    renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_44
+    dead $x0 = PseudoVSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
+    $x11 = ADDI $x2, 16
+    $x12 = PseudoReadVLENB
+    $x12 = SLLI $x12, 1
+    renamable $v10m2_v12m2_v14m2_v16m2 = PseudoVRELOAD4_M2 killed $x11, killed $x12 :: (load unknown-size from %stack.1, align 8)
+    renamable $v16m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    $x0 = PseudoVSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
+    renamable $x10 = LUI target-flags(riscv-hi) @__const._Z3foov.var_40
+    renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @__const._Z3foov.var_40
+    renamable $v8m2 = PseudoVLE16_V_M2 killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    $x0 = PseudoVSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
+    renamable $x10 = LUI 1048572
+    renamable $x10 = ADDIW killed renamable $x10, 928
+    early-clobber renamable $v0 = PseudoVMSBC_VX_M2 killed renamable $v8m2, killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    $x0 = PseudoVSETIVLI 2, 9 /* e16, m2, tu, mu */, implicit-def $vl, implicit-def $vtype
+    $x10 = PseudoReadVLENB
+    $x10 = SLLI killed $x10, 3
+    $x10 = ADD $x2, killed $x10
+    $x10 = ADDI $x10, 16
+    renamable $v8 = PseudoVRELOAD_M1 killed $x10 :: (load unknown-size from %stack.0, align 8)
+    early-clobber renamable $v10m2 = PseudoVSEXT_VF2_M2_MASK renamable $v10m2, killed renamable $v8, $v0, 2, 4 /* e16 */, 0, implicit $vl, implicit $vtype
+    renamable $x10 = LUI target-flags(riscv-hi) @var_47
+    renamable $x10 = ADDI killed renamable $x10, target-flags(riscv-lo) @var_47
+    PseudoVSSEG4E16_V_M2 killed renamable $v10m2_v12m2_v14m2_v16m2, killed renamable $x10, 2, 4 /* e16 */, implicit $vl, implicit $vtype
+    $x10 = frame-destroy PseudoReadVLENB
+    $x11 = frame-destroy ADDI killed $x0, 10
+    $x10 = frame-destroy MUL killed $x10, killed $x11
+    $x2 = frame-destroy ADD $x2, killed $x10
+    $x2 = frame-destroy ADDI $x2, 16
+    PseudoRET
+
+...