diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -2166,6 +2166,9 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); + MachineModuleInfo &MMI = MF.getMMI(); + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + const std::vector &CSI = MFI.getCalleeSavedInfo(); X86MachineFunctionInfo *X86FI = MF.getInfo(); MachineBasicBlock::iterator Terminator = MBB.getFirstTerminator(); MachineBasicBlock::iterator MBBI = Terminator; @@ -2337,7 +2340,7 @@ if (NeedsWin64CFI && MF.hasWinCFI()) BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue)); - if (!HasFP && NeedsDwarfCFI) { + if (NeedsDwarfCFI) { MBBI = FirstCSPop; int64_t Offset = -CSSize - SlotSize; // Mark callee-saved pop instruction. @@ -2346,7 +2349,22 @@ MachineBasicBlock::iterator PI = MBBI; unsigned Opc = PI->getOpcode(); ++MBBI; - if (Opc == X86::POP32r || Opc == X86::POP64r) { + if (Opc == X86::POP32r || Opc == X86::POP64r) + continue; + if (!has128ByteRedZone(MF)) { + Register Reg = PI->getOperand(0).getReg(); + // Check if the poped register is callee-saved register. + if (std::find_if(CSI.begin(), CSI.end(), + [&Reg](const CalleeSavedInfo &I) -> bool { + return Reg == I.getReg(); + }) != CSI.end()) { + unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); + BuildCFI(MBB, MBBI, DL, + MCCFIInstruction::createRestore(nullptr, DwarfReg), + MachineInstr::FrameDestroy); + } + } + if (!HasFP) { Offset += SlotSize; BuildCFI(MBB, MBBI, DL, MCCFIInstruction::cfiDefCfaOffset(nullptr, -Offset),