diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -290,7 +290,7 @@
Register SrcReg = MBBI->getOperand(0).getReg();
Register Base = MBBI->getOperand(1).getReg();
Register VL = MBBI->getOperand(2).getReg();
- auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MBBI->getOpcode());
+ auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MBBI->getOpcode());
if (!ZvlssegInfo)
return false;
unsigned NF = ZvlssegInfo->first;
@@ -335,7 +335,7 @@
Register DestReg = MBBI->getOperand(0).getReg();
Register Base = MBBI->getOperand(1).getReg();
Register VL = MBBI->getOperand(2).getReg();
- auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MBBI->getOpcode());
+ auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MBBI->getOpcode());
if (!ZvlssegInfo)
return false;
unsigned NF = ZvlssegInfo->first;
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -941,14 +941,14 @@
return std::make_pair(StackSize, RVVStackAlign);
}
-static bool hasRVVSpillWithFIs(MachineFunction &MF, const RISCVInstrInfo &TII) {
+static bool hasRVVSpillWithFIs(MachineFunction &MF) {
if (!MF.getSubtarget<RISCVSubtarget>().hasVInstructions())
return false;
- return any_of(MF, [&TII](const MachineBasicBlock &MBB) {
- return any_of(MBB, [&TII](const MachineInstr &MI) {
- return TII.isRVVSpill(MI, /*CheckFIs*/ true);
- });
- });
+ for (const MachineBasicBlock &MBB : MF)
+ for (const MachineInstr &MI : MBB)
+ if (RISCV::isRVVSpill(MI, /*CheckFIs*/ true))
+ return true;
+ return false;
}
void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
@@ -971,8 +971,6 @@
// target-independent code.
MFI.ensureMaxAlignment(RVVStackAlign);
- const RISCVInstrInfo &TII = *MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
-
// estimateStackSize has been observed to under-estimate the final stack
// size, so give ourselves wiggle-room by checking for stack size
// representable an 11-bit signed field rather than 12-bits.
@@ -982,7 +980,7 @@
// RVV loads & stores have no capacity to hold the immediate address offsets
// so we must always reserve an emergency spill slot if the MachineFunction
// contains any RVV spills.
- if (!isInt<11>(MFI.estimateStackSize(MF)) || hasRVVSpillWithFIs(MF, TII)) {
+ if (!isInt<11>(MFI.estimateStackSize(MF)) || hasRVVSpillWithFIs(MF)) {
int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
RegInfo->getSpillAlign(*RC), false);
RS->addScavengingFrameIndex(RegScavFI);
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1413,11 +1413,10 @@
void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
const MachineFunction *MF = MBB.getParent();
- const RISCVInstrInfo *TII = MF->getSubtarget<RISCVSubtarget>().getInstrInfo();
for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
MachineInstr &MI = *I++;
- if (TII->isFaultFirstLoad(MI)) {
+ if (RISCV::isFaultFirstLoad(MI)) {
Register VLOutput = MI.getOperand(1).getReg();
if (!MRI->use_nodbg_empty(VLOutput))
BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -177,22 +177,21 @@
MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount,
MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
- // Returns true if the given MI is an RVV instruction opcode for which we may
- // expect to see a FrameIndex operand. When CheckFIs is true, the instruction
- // must contain at least one FrameIndex operand.
- bool isRVVSpill(const MachineInstr &MI, bool CheckFIs) const;
-
- Optional<std::pair<unsigned, unsigned>>
- isRVVSpillForZvlsseg(unsigned Opcode) const;
-
- bool isFaultFirstLoad(const MachineInstr &MI) const;
-
protected:
const RISCVSubtarget &STI;
};
namespace RISCV {
+// Returns true if the given MI is an RVV instruction opcode for which we may
+// expect to see a FrameIndex operand. When CheckFIs is true, the instruction
+// must contain at least one FrameIndex operand.
+bool isRVVSpill(const MachineInstr &MI, bool CheckFIs);
+
+Optional<std::pair<unsigned, unsigned>> isRVVSpillForZvlsseg(unsigned Opcode);
+
+bool isFaultFirstLoad(const MachineInstr &MI);
+
// Implemented in RISCVGenInstrInfo.inc
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1878,7 +1878,7 @@
}
}
-bool RISCVInstrInfo::isRVVSpill(const MachineInstr &MI, bool CheckFIs) const {
+bool RISCV::isRVVSpill(const MachineInstr &MI, bool CheckFIs) {
// RVV lacks any support for immediate addressing for stack addresses, so be
// conservative.
unsigned Opcode = MI.getOpcode();
@@ -1891,7 +1891,7 @@
}
Optional<std::pair<unsigned, unsigned>>
-RISCVInstrInfo::isRVVSpillForZvlsseg(unsigned Opcode) const {
+RISCV::isRVVSpillForZvlsseg(unsigned Opcode) {
switch (Opcode) {
default:
return None;
@@ -1931,7 +1931,7 @@
}
}
-bool RISCVInstrInfo::isFaultFirstLoad(const MachineInstr &MI) const {
+bool RISCV::isFaultFirstLoad(const MachineInstr &MI) {
return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
!MI.isInlineAsm();
}
diff --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
--- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
@@ -145,7 +145,6 @@
const TargetRegisterInfo *TRI =
MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
- const RISCVInstrInfo *TII = MF->getSubtarget<RISCVSubtarget>().getInstrInfo();
assert(TRI && "TargetRegisterInfo expected");
@@ -160,7 +159,7 @@
if (RISCVII::hasSEWOp(TSFlags))
--NumOps;
- bool hasVLOutput = TII->isFaultFirstLoad(*MI);
+ bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
// Skip vl ouput. It should be the second output.
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -174,7 +174,7 @@
Register FrameReg;
StackOffset Offset =
getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
- bool IsRVVSpill = TII->isRVVSpill(MI, /*CheckFIs*/ false);
+ bool IsRVVSpill = RISCV::isRVVSpill(MI, /*CheckFIs*/ false);
if (!IsRVVSpill)
Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
@@ -273,7 +273,7 @@
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
}
- auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MI.getOpcode());
+ auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MI.getOpcode());
if (ZvlssegInfo) {
Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);