diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -280,10 +280,17 @@
                                    S23, S24, S25, S26, S27, S28, S29, S30, S31
                               )>;
 
+def CSR_SPE_NO_S30 : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21,
+				          S22, S23, S24, S25, S26, S27, S28, S29,
+					  S31
+			      )>;
+
 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
 
 def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
 
+def CSR_SVR432_SPE_NO_S30 : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE_NO_S30)>;
+
 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
                                      R21, R22, R23, R24, R25, R26, R27, R28,
                                      R29, R30, R31, F14, F15, F16, F17, F18,
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -253,8 +253,11 @@
     return CSR_SVR432_VSRP_SaveList;
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
-  else if (Subtarget.hasSPE())
+  else if (Subtarget.hasSPE()) {
+    if (TM.isPositionIndependent() && !TM.isPPC64())
+      return CSR_SVR432_SPE_NO_S30_SaveList;
     return CSR_SVR432_SPE_SaveList;
+   }
   return CSR_SVR432_SaveList;
 }
 
@@ -313,7 +316,9 @@
                ? CSR_SVR432_VSRP_RegMask
                : (Subtarget.hasAltivec()
                       ? CSR_SVR432_Altivec_RegMask
-                      : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
+                      : (Subtarget.hasSPE() ? (TM.isPositionIndependent()
+						? CSR_SVR432_SPE_NO_S30_RegMask
+						: CSR_SVR432_SPE_RegMask)
                                             : CSR_SVR432_RegMask));
 }