diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -1260,12 +1260,17 @@ // FIXME? Maybe this could be a TableGen attribute on some registers and // this table could be generated automatically from RegInfo. -Register SystemZTargetLowering::getRegisterByName(const char *RegName, LLT VT, - const MachineFunction &MF) const { +Register +SystemZTargetLowering::getRegisterByName(const char *RegName, LLT VT, + const MachineFunction &MF) const { + const SystemZSubtarget *Subtarget = &MF.getSubtarget(); + + Register Reg = + StringSwitch(RegName) + .Case("r4", Subtarget->isTargetXPLINK64() ? SystemZ::R4D : 0) + .Case("r15", Subtarget->isTargetELF() ? SystemZ::R15D : 0) + .Default(0); - Register Reg = StringSwitch(RegName) - .Case("r15", SystemZ::R15D) - .Default(0); if (Reg) return Reg; report_fatal_error("Invalid register name global variable"); diff --git a/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll b/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s + +; CHECK-LABEL: get_stack: +; CHECK: lgr 3, 4 +; CHECK: b 2(7) + +define i8* @get_stack() nounwind { +entry: + %0 = call i64 @llvm.read_register.i64(metadata !0) + %1 = inttoptr i64 %0 to i8* + ret i8* %1 +} + +declare i64 @llvm.read_register.i64(metadata) nounwind + +!0 = !{!"r4"}