Index: llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp =================================================================== --- llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -13,6 +13,8 @@ #include "InstCombineInternal.h" #include "llvm/Analysis/CmpInstAnalysis.h" #include "llvm/Analysis/InstructionSimplify.h" +#include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Analysis/Loads.h" #include "llvm/IR/ConstantRange.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/PatternMatch.h" @@ -2993,6 +2995,134 @@ Builder.CreateOr(C, Builder.CreateAnd(A, B)), D); } + // Identify and Merge consecutive loads of the form + // 1. (zExt(L1) << shift1) | (zExt(L2) << shift2) -> zExt(L3) << shift1 + // 2. (? | (zExt(L1) << shift1)) | (zExt(L2) << shift2) -> ? | (zExt(L3) << + // shift1) + const APInt *ShAmt2; + if (match(&I, m_c_Or(m_Value(X), m_OneUse(m_Shl(m_Value(Y), m_APInt(ShAmt2)))))) { + Value *ShAmt1 = NULL; + Instruction *L1, *L2; + Value *Hold = NULL; + // Check if X and Y have loads. + if ((match(X, m_OneUse(m_ZExt(m_Instruction(L1)))) || + match(X, m_OneUse(m_c_Or(m_Value(Hold), + m_OneUse(m_Shl(m_OneUse(m_ZExt(m_OneUse(m_Instruction(L1)))), m_Value(ShAmt1))))))) && + match(Y, m_OneUse(m_ZExt(m_OneUse(m_Instruction(L2)))))) { + // Check if loads are different + if (L1 == L2) + return nullptr; + + LoadInst *LI1, *LI2; + if (!((LI1 = dyn_cast(L1)) && (LI2 = dyn_cast(L2)))) + return nullptr; + + // Return if volatile or atomic + if (!LI1->isSimple() && !LI2->isSimple()) + return nullptr; + + // Check if loads are consecutive and same size. + Value *Op1 = LI1->getOperand(0); + Value *Op2 = LI2->getOperand(0); + + // Second load must be a GEP. Extract load info. + if (isa(Op2)) { + GetElementPtrInst *GEP2 = dyn_cast(Op2); + // Parse Index + uint64_t Idx2 = 0; + uint64_t Src2Type = DL.getTypeStoreSizeInBits(GEP2->getSourceElementType()); + if (ConstantInt *CI = dyn_cast(GEP2->getOperand(1))) + Idx2 = CI->getZExtValue(); + + Value *Load1Ptr; + uint64_t Idx1 = 0; + uint64_t Shift1 = 0; + uint64_t Src1Type = 0; + GetElementPtrInst *GEP1 = NULL; + if (isa(Op1)) { + GEP1 = dyn_cast(Op1); + Load1Ptr = GEP1->getPointerOperand(); + if (ConstantInt *CI = dyn_cast(GEP1->getOperand(1))) + Idx1 = CI->getZExtValue(); + Src1Type = DL.getTypeStoreSizeInBits(GEP1->getSourceElementType()); + if (Src1Type != Src2Type) + return nullptr; + } + else + // Considering this then a direct load from pointer. + Load1Ptr = LI1->getPointerOperand(); + + // Parse shift amount of Load1 if available. + const APInt *Temp; + if (ShAmt1 && match(ShAmt1, m_APInt(Temp))) + Shift1 = Temp->getZExtValue(); + + // Verify if both loads have same base pointers and load sizes are same. + uint64_t loadSize1 = DL.getTypeStoreSizeInBits(LI1->getType()); + uint64_t loadSize2 = DL.getTypeStoreSizeInBits(LI2->getType()); + if ((Load1Ptr != GEP2->getPointerOperand()) || (loadSize1 != loadSize2)) + return nullptr; + + // Verify if shift amount and load index aligns and verifies that loads + // are consecutive. + if (!((ShAmt2->getZExtValue() - Shift1) == loadSize1) && + (((Idx2 * Src2Type) - (Idx1 * Src1Type)) == loadSize1)) + return nullptr; + + // Alias Analysis to check for store b/w the loads. + BasicBlock *LoadBB = LI2->getParent(); + BasicBlock::iterator BBIt(LI2); + bool IsLoadCSE = false; + if (!FindAvailableLoadedValue(LI1, LoadBB, BBIt, DefMaxInstsToScan, AA, + &IsLoadCSE)) + return nullptr; + + LoadInst *NewLoad; + if (!GEP1) + NewLoad = new LoadInst( + IntegerType::get(Load1Ptr->getContext(), loadSize1 * 2), Load1Ptr, + "", LI1->isVolatile(), LI1->getAlign(), LI1->getOrdering(), + LI1->getSyncScopeID()); + else + NewLoad = + new LoadInst(IntegerType::get(GEP1->getContext(), loadSize1 * 2), + GEP1, "", LI1->isVolatile(), LI1->getAlign(), + LI1->getOrdering(), LI1->getSyncScopeID()); + + // Attempt to improve the alignment. + Value *Op = LI1->getOperand(0); + Align KnownAlign = getOrEnforceKnownAlignment( + Op, DL.getPrefTypeAlign(LI1->getType()), DL, LI1, &AC, &DT); + if (KnownAlign > LI1->getAlign()) + LI1->setAlignment(KnownAlign); + + NewLoad->takeName(LI1); + copyMetadataForLoad(*NewLoad, *LI1); + InsertNewInstWith(NewLoad, *LI1); + + // Check if zero extend needed. + Value *NewOp; + if (NewLoad->getType() != X->getType()) { + NewOp = Builder.CreateZExt(NewLoad, X->getType()); + } else + NewOp = (Value *)NewLoad; + + // Check if shift needed. We need to shift with the amount of load1 + // shift if not zero. + if (Shift1 != 0) { + NewOp = BinaryOperator::CreateShl(NewOp, ShAmt1); + Builder.Insert(NewOp); + } + + if (match(X, m_ZExt(m_Instruction(L1))) && !Hold) { + Value *Zero = Constant::getNullValue(X->getType()); + return BinaryOperator::CreateOr(NewOp, Zero); + } else + return BinaryOperator::CreateOr(Hold, NewOp); + } + } + } + return nullptr; } Index: llvm/test/Transforms/InstCombine/or-load.ll =================================================================== --- /dev/null +++ llvm/test/Transforms/InstCombine/or-load.ll @@ -0,0 +1,527 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -passes=instcombine -S | FileCheck %s + + +define i32 @loadCombine_4consecutive(ptr %p) { +; CHECK-LABEL: @loadCombine_4consecutive( +; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1 +; CHECK-NEXT: ret i32 [[L1]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %p3 = getelementptr i8, ptr %p, i32 3 + %l1 = load i8, ptr %p + %l2 = load i8, ptr %p1 + %l3 = load i8, ptr %p2 + %l4 = load i8, ptr %p3 + + %e1 = zext i8 %l1 to i32 + %e2 = zext i8 %l2 to i32 + %e3 = zext i8 %l3 to i32 + %e4 = zext i8 %l4 to i32 + + %s1 = shl i32 %e1, 0 + %s2 = shl i32 %e2, 8 + %s3 = shl i32 %e3, 16 + %s4 = shl i32 %e4, 24 + + %o1 = or i32 %s1, %s2 + %o2 = or i32 %o1, %s3 + %o3 = or i32 %o2, %s4 + ret i32 %o3 +} + +define i32 @loadCombine_4consecutive_with_alias1(ptr %p) { +; CHECK-LABEL: @loadCombine_4consecutive_with_alias1( +; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 2 +; CHECK-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 1 +; CHECK-NEXT: store i8 10, ptr [[P]], align 1 +; CHECK-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 1 +; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[L1]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[L3]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP2]], 16 +; CHECK-NEXT: [[O3:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CHECK-NEXT: ret i32 [[O3]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %p3 = getelementptr i8, ptr %p, i32 3 + %l1 = load i8, ptr %p + store i8 10, i8* %p + %l2 = load i8, ptr %p1 + %l3 = load i8, ptr %p2 + %l4 = load i8, ptr %p3 + + %e1 = zext i8 %l1 to i32 + %e2 = zext i8 %l2 to i32 + %e3 = zext i8 %l3 to i32 + %e4 = zext i8 %l4 to i32 + + %s1 = shl i32 %e1, 0 + %s2 = shl i32 %e2, 8 + %s3 = shl i32 %e3, 16 + %s4 = shl i32 %e4, 24 + + %o1 = or i32 %s1, %s2 + %o2 = or i32 %o1, %s3 + %o3 = or i32 %o2, %s4 + ret i32 %o3 +} + +define i32 @loadCombine_4consecutive_with_alias2(ptr %p, ptr %ps) { +; CHECK-LABEL: @loadCombine_4consecutive_with_alias2( +; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 +; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 +; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 +; CHECK-NEXT: store i8 10, ptr [[PS:%.*]], align 1 +; CHECK-NEXT: [[L2:%.*]] = load i16, ptr [[P1]], align 1 +; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 +; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 +; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 +; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 +; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[L2]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 8 +; CHECK-NEXT: [[O2:%.*]] = or i32 [[TMP2]], [[E1]] +; CHECK-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]] +; CHECK-NEXT: ret i32 [[O3]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %p3 = getelementptr i8, ptr %p, i32 3 + %l1 = load i8, ptr %p + store i8 10, i8* %ps + %l2 = load i8, ptr %p1 + %l3 = load i8, ptr %p2 + %l4 = load i8, ptr %p3 + + %e1 = zext i8 %l1 to i32 + %e2 = zext i8 %l2 to i32 + %e3 = zext i8 %l3 to i32 + %e4 = zext i8 %l4 to i32 + + %s1 = shl i32 %e1, 0 + %s2 = shl i32 %e2, 8 + %s3 = shl i32 %e3, 16 + %s4 = shl i32 %e4, 24 + + %o1 = or i32 %s1, %s2 + %o2 = or i32 %o1, %s3 + %o3 = or i32 %o2, %s4 + ret i32 %o3 +} + +define i32 @loadCombine_4consecutive_with_alias3(ptr %p, ptr %ps) { +; CHECK-LABEL: @loadCombine_4consecutive_with_alias3( +; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 +; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 +; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 +; CHECK-NEXT: [[PS1:%.*]] = getelementptr i8, ptr [[PS:%.*]], i64 1 +; CHECK-NEXT: [[PS2:%.*]] = getelementptr i8, ptr [[PS]], i64 2 +; CHECK-NEXT: [[PS3:%.*]] = getelementptr i8, ptr [[PS]], i64 3 +; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 +; CHECK-NEXT: store i8 10, ptr [[PS]], align 1 +; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 +; CHECK-NEXT: store i8 10, ptr [[PS1]], align 1 +; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 +; CHECK-NEXT: store i8 10, ptr [[PS2]], align 1 +; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 +; CHECK-NEXT: store i8 10, ptr [[PS3]], align 1 +; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 +; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 +; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 +; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 +; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 +; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 +; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 +; CHECK-NEXT: [[O1:%.*]] = or i32 [[S2]], [[E1]] +; CHECK-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]] +; CHECK-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]] +; CHECK-NEXT: ret i32 [[O3]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %p3 = getelementptr i8, ptr %p, i32 3 + %ps1 = getelementptr i8, ptr %ps, i32 1 + %ps2 = getelementptr i8, ptr %ps, i32 2 + %ps3 = getelementptr i8, ptr %ps, i32 3 + %l1 = load i8, ptr %p + store i8 10, i8* %ps + %l2 = load i8, ptr %p1 + store i8 10, i8* %ps1 + %l3 = load i8, ptr %p2 + store i8 10, i8* %ps2 + %l4 = load i8, ptr %p3 + store i8 10, i8* %ps3 + + %e1 = zext i8 %l1 to i32 + %e2 = zext i8 %l2 to i32 + %e3 = zext i8 %l3 to i32 + %e4 = zext i8 %l4 to i32 + + %s1 = shl i32 %e1, 0 + %s2 = shl i32 %e2, 8 + %s3 = shl i32 %e3, 16 + %s4 = shl i32 %e4, 24 + + %o1 = or i32 %s1, %s2 + %o2 = or i32 %o1, %s3 + %o3 = or i32 %o2, %s4 + ret i32 %o3 +} + +; Function Attrs: nounwind uwtable +define i64 @Load64(ptr %ptr) { +; CHECK-LABEL: @Load64( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[PTR:%.*]], align 1 +; CHECK-NEXT: ret i64 [[TMP0]] +; +entry: + %0 = load i8, ptr %ptr, align 1 + %conv = zext i8 %0 to i64 + %arrayidx1 = getelementptr inbounds i8, ptr %ptr, i64 1 + %1 = load i8, ptr %arrayidx1, align 1 + %conv2 = zext i8 %1 to i64 + %shl = shl i64 %conv2, 8 + %or = or i64 %conv, %shl + %arrayidx3 = getelementptr inbounds i8, ptr %ptr, i64 2 + %2 = load i8, ptr %arrayidx3, align 1 + %conv4 = zext i8 %2 to i64 + %shl5 = shl i64 %conv4, 16 + %or6 = or i64 %or, %shl5 + %arrayidx7 = getelementptr inbounds i8, ptr %ptr, i64 3 + %3 = load i8, ptr %arrayidx7, align 1 + %conv8 = zext i8 %3 to i64 + %shl9 = shl i64 %conv8, 24 + %or10 = or i64 %or6, %shl9 + %arrayidx11 = getelementptr inbounds i8, ptr %ptr, i64 4 + %4 = load i8, ptr %arrayidx11, align 1 + %conv12 = zext i8 %4 to i64 + %shl13 = shl i64 %conv12, 32 + %or14 = or i64 %or10, %shl13 + %arrayidx15 = getelementptr inbounds i8, ptr %ptr, i64 5 + %5 = load i8, ptr %arrayidx15, align 1 + %conv16 = zext i8 %5 to i64 + %shl17 = shl i64 %conv16, 40 + %or18 = or i64 %or14, %shl17 + %arrayidx19 = getelementptr inbounds i8, ptr %ptr, i64 6 + %6 = load i8, ptr %arrayidx19, align 1 + %conv20 = zext i8 %6 to i64 + %shl21 = shl i64 %conv20, 48 + %or22 = or i64 %or18, %shl21 + %arrayidx23 = getelementptr inbounds i8, ptr %ptr, i64 7 + %7 = load i8, ptr %arrayidx23, align 1 + %conv24 = zext i8 %7 to i64 + %shl25 = shl i64 %conv24, 56 + %or26 = or i64 %or22, %shl25 + ret i64 %or26 +} + +declare void @use(i8) +declare void @use2(i32) + +define i32 @loadCombine_4consecutive_hasOneUse1(ptr %p) { +; CHECK-LABEL: @loadCombine_4consecutive_hasOneUse1( +; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 +; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 +; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 +; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 +; CHECK-NEXT: call void @use(i8 [[L1]]) +; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 +; CHECK-NEXT: call void @use(i8 [[L2]]) +; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 +; CHECK-NEXT: call void @use(i8 [[L3]]) +; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 +; CHECK-NEXT: call void @use(i8 [[L4]]) +; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 +; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 +; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 +; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 +; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 +; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 +; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 +; CHECK-NEXT: [[O1:%.*]] = or i32 [[S2]], [[E1]] +; CHECK-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]] +; CHECK-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]] +; CHECK-NEXT: ret i32 [[O3]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %p3 = getelementptr i8, ptr %p, i32 3 + %l1 = load i8, ptr %p + call void @use(i8 %l1) + %l2 = load i8, ptr %p1 + call void @use(i8 %l2) + %l3 = load i8, ptr %p2 + call void @use(i8 %l3) + %l4 = load i8, ptr %p3 + call void @use(i8 %l4) + + %e1 = zext i8 %l1 to i32 + %e2 = zext i8 %l2 to i32 + %e3 = zext i8 %l3 to i32 + %e4 = zext i8 %l4 to i32 + + %s1 = shl i32 %e1, 0 + %s2 = shl i32 %e2, 8 + %s3 = shl i32 %e3, 16 + %s4 = shl i32 %e4, 24 + + %o1 = or i32 %s1, %s2 + %o2 = or i32 %o1, %s3 + %o3 = or i32 %o2, %s4 + ret i32 %o3 +} + +define i32 @loadCombine_4consecutive_hasOneUse2(ptr %p) { +; CHECK-LABEL: @loadCombine_4consecutive_hasOneUse2( +; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 +; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 +; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 +; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 +; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 +; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 +; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 +; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 +; CHECK-NEXT: call void @use(i32 [[E1]]) +; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 +; CHECK-NEXT: call void @use(i32 [[E2]]) +; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 +; CHECK-NEXT: call void @use(i32 [[E3]]) +; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 +; CHECK-NEXT: call void @use(i32 [[E4]]) +; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 +; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 +; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 +; CHECK-NEXT: [[O1:%.*]] = or i32 [[S2]], [[E1]] +; CHECK-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]] +; CHECK-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]] +; CHECK-NEXT: ret i32 [[O3]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %p3 = getelementptr i8, ptr %p, i32 3 + %l1 = load i8, ptr %p + %l2 = load i8, ptr %p1 + %l3 = load i8, ptr %p2 + %l4 = load i8, ptr %p3 + + %e1 = zext i8 %l1 to i32 + call void @use(i32 %e1) + %e2 = zext i8 %l2 to i32 + call void @use(i32 %e2) + %e3 = zext i8 %l3 to i32 + call void @use(i32 %e3) + %e4 = zext i8 %l4 to i32 + call void @use(i32 %e4) + + %s1 = shl i32 %e1, 0 + %s2 = shl i32 %e2, 8 + %s3 = shl i32 %e3, 16 + %s4 = shl i32 %e4, 24 + + %o1 = or i32 %s1, %s2 + %o2 = or i32 %o1, %s3 + %o3 = or i32 %o2, %s4 + ret i32 %o3 +} + +define i32 @loadCombine_4consecutive_hasOneUse3(ptr %p) { +; CHECK-LABEL: @loadCombine_4consecutive_hasOneUse3( +; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 +; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 +; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 +; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 +; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 +; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 +; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 +; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 +; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 +; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 +; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 +; CHECK-NEXT: call void @use(i32 [[E1]]) +; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 +; CHECK-NEXT: call void @use(i32 [[S2]]) +; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 +; CHECK-NEXT: call void @use(i32 [[S3]]) +; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 +; CHECK-NEXT: call void @use(i32 [[S4]]) +; CHECK-NEXT: [[O1:%.*]] = or i32 [[S2]], [[E1]] +; CHECK-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]] +; CHECK-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]] +; CHECK-NEXT: ret i32 [[O3]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %p3 = getelementptr i8, ptr %p, i32 3 + %l1 = load i8, ptr %p + %l2 = load i8, ptr %p1 + %l3 = load i8, ptr %p2 + %l4 = load i8, ptr %p3 + + %e1 = zext i8 %l1 to i32 + %e2 = zext i8 %l2 to i32 + %e3 = zext i8 %l3 to i32 + %e4 = zext i8 %l4 to i32 + + %s1 = shl i32 %e1, 0 + call void @use(i32 %s1) + %s2 = shl i32 %e2, 8 + call void @use(i32 %s2) + %s3 = shl i32 %e3, 16 + call void @use(i32 %s3) + %s4 = shl i32 %e4, 24 + call void @use(i32 %s4) + + %o1 = or i32 %s1, %s2 + %o2 = or i32 %o1, %s3 + %o3 = or i32 %o2, %s4 + ret i32 %o3 +} + +define i32 @loadCombine_4consecutive_hasOneUse4(ptr %p) { +; CHECK-LABEL: @loadCombine_4consecutive_hasOneUse4( +; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 2 +; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 +; CHECK-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 1 +; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 +; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 +; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 +; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 +; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 +; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 +; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[L1]] to i32 +; CHECK-NEXT: call void @use(i32 [[TMP1]]) +; CHECK-NEXT: [[O2:%.*]] = or i32 [[S3]], [[TMP1]] +; CHECK-NEXT: call void @use(i32 [[O2]]) +; CHECK-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]] +; CHECK-NEXT: ret i32 [[O3]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %p3 = getelementptr i8, ptr %p, i32 3 + %l1 = load i8, ptr %p + %l2 = load i8, ptr %p1 + %l3 = load i8, ptr %p2 + %l4 = load i8, ptr %p3 + + %e1 = zext i8 %l1 to i32 + %e2 = zext i8 %l2 to i32 + %e3 = zext i8 %l3 to i32 + %e4 = zext i8 %l4 to i32 + + %s1 = shl i32 %e1, 0 + %s2 = shl i32 %e2, 8 + %s3 = shl i32 %e3, 16 + %s4 = shl i32 %e4, 24 + + %o1 = or i32 %s1, %s2 + call void @use(i32 %o1) + %o2 = or i32 %o1, %s3 + call void @use(i32 %o2) + %o3 = or i32 %o2, %s4 + ret i32 %o3 +} + +define i32 @loadCombine_4consecutive_hasOneUse5(ptr %p) { +; CHECK-LABEL: @loadCombine_4consecutive_hasOneUse5( +; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 +; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 +; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 +; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 +; CHECK-NEXT: call void @use(i8 [[L1]]) +; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 +; CHECK-NEXT: call void @use(i8 [[L2]]) +; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 +; CHECK-NEXT: call void @use(i8 [[L3]]) +; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 +; CHECK-NEXT: call void @use(i8 [[L4]]) +; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 +; CHECK-NEXT: call void @use(i32 [[E1]]) +; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 +; CHECK-NEXT: call void @use(i32 [[E2]]) +; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 +; CHECK-NEXT: call void @use(i32 [[E3]]) +; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 +; CHECK-NEXT: call void @use(i32 [[E4]]) +; CHECK-NEXT: call void @use(i32 [[E1]]) +; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 +; CHECK-NEXT: call void @use(i32 [[S2]]) +; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 +; CHECK-NEXT: call void @use(i32 [[S3]]) +; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 +; CHECK-NEXT: call void @use(i32 [[S4]]) +; CHECK-NEXT: [[O1:%.*]] = or i32 [[S2]], [[E1]] +; CHECK-NEXT: call void @use(i32 [[O1]]) +; CHECK-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]] +; CHECK-NEXT: call void @use(i32 [[O2]]) +; CHECK-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]] +; CHECK-NEXT: ret i32 [[O3]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %p3 = getelementptr i8, ptr %p, i32 3 + %l1 = load i8, ptr %p + call void @use(i8 %l1) + %l2 = load i8, ptr %p1 + call void @use(i8 %l2) + %l3 = load i8, ptr %p2 + call void @use(i8 %l3) + %l4 = load i8, ptr %p3 + call void @use(i8 %l4) + + %e1 = zext i8 %l1 to i32 + call void @use(i32 %e1) + %e2 = zext i8 %l2 to i32 + call void @use(i32 %e2) + %e3 = zext i8 %l3 to i32 + call void @use(i32 %e3) + %e4 = zext i8 %l4 to i32 + call void @use(i32 %e4) + + %s1 = shl i32 %e1, 0 + call void @use(i32 %s1) + %s2 = shl i32 %e2, 8 + call void @use(i32 %s2) + %s3 = shl i32 %e3, 16 + call void @use(i32 %s3) + %s4 = shl i32 %e4, 24 + call void @use(i32 %s4) + + %o1 = or i32 %s1, %s2 + call void @use(i32 %o1) + %o2 = or i32 %o1, %s3 + call void @use(i32 %o2) + %o3 = or i32 %o2, %s4 + ret i32 %o3 +} + +define i32 @loadCombine_parLoad1(ptr %p) { +; CHECK-LABEL: @loadCombine_parLoad1( +; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 2 +; CHECK-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 1 +; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 +; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 +; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 +; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[L1]] to i32 +; CHECK-NEXT: [[O2:%.*]] = or i32 [[S3]], [[TMP1]] +; CHECK-NEXT: ret i32 [[O2]] +; + %p1 = getelementptr i8, ptr %p, i32 1 + %p2 = getelementptr i8, ptr %p, i32 2 + %l1 = load i8, ptr %p + %l2 = load i8, ptr %p1 + %l3 = load i8, ptr %p2 + + %e1 = zext i8 %l1 to i32 + %e2 = zext i8 %l2 to i32 + %e3 = zext i8 %l3 to i32 + + %s1 = shl i32 %e1, 0 + %s2 = shl i32 %e2, 8 + %s3 = shl i32 %e3, 16 + + %o1 = or i32 %s1, %s2 + %o2 = or i32 %o1, %s3 + ret i32 %o2 +}