Index: llvm/include/llvm/CodeGen/MachineBasicBlock.h
===================================================================
--- llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -405,7 +405,7 @@
   // Iteration support for live in sets.  These sets are kept in sorted
   // order by their register number.
   using livein_iterator = LiveInVector::const_iterator;
-#ifndef NDEBUG
+
   /// Unlike livein_begin, this method does not check that the liveness
   /// information is accurate. Still for debug purposes it may be useful
   /// to have iterators that won't assert if the liveness information
@@ -414,7 +414,7 @@
   iterator_range<livein_iterator> liveins_dbg() const {
     return make_range(livein_begin_dbg(), livein_end());
   }
-#endif
+
   livein_iterator livein_begin() const;
   livein_iterator livein_end()   const { return LiveIns.end(); }
   bool            livein_empty() const { return LiveIns.empty(); }
Index: llvm/lib/CodeGen/MIRPrinter.cpp
===================================================================
--- llvm/lib/CodeGen/MIRPrinter.cpp
+++ llvm/lib/CodeGen/MIRPrinter.cpp
@@ -691,11 +691,11 @@
 
   // Print the live in registers.
   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
-  if (MRI.tracksLiveness() && !MBB.livein_empty()) {
+  if (!MBB.livein_empty()) {
     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
     OS.indent(2) << "liveins: ";
     bool First = true;
-    for (const auto &LI : MBB.liveins()) {
+    for (const auto &LI : MBB.liveins_dbg()) {
       if (!First)
         OS << ", ";
       First = false;
Index: llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
@@ -17,6 +17,7 @@
   ; CHECK-LABEL: name: tbnzx_and
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
   ; CHECK-NEXT:   TBNZX [[COPY]], 33, %bb.1
@@ -215,6 +216,7 @@
   ; CHECK-LABEL: name: dont_fold_and_not_power_of_2
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
   ; CHECK-NEXT:   [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[COPY]], 4098
@@ -247,6 +249,7 @@
   ; CHECK-LABEL: name: dont_fold_cmp_not_0
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
   ; CHECK-NEXT:   [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 8064
Index: llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
@@ -12,6 +12,7 @@
   ; CHECK-LABEL: name: fold_shl
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64all = COPY $x0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
@@ -49,6 +50,7 @@
   ; CHECK-LABEL: name: dont_fold_shl_1
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   %fold_me:gpr64 = UBFMXri %copy, 59, 58
@@ -87,6 +89,7 @@
   ; CHECK-LABEL: name: dont_fold_shl_2
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   %fold_cst:gpr64 = MOVi64imm -5
@@ -127,6 +130,7 @@
   ; CHECK-LABEL: name: dont_fold_shl_3
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   %shl:gpr64 = UBFMXri %copy, 62, 61
@@ -170,6 +174,7 @@
   ; CHECK-LABEL: name: fold_ashr_in_range
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64all = COPY $x0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
@@ -209,6 +214,7 @@
   ; CHECK-LABEL: name: fold_ashr_msb_1
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
   ; CHECK-NEXT:   TBNZW %copy, 31, %bb.1
@@ -245,6 +251,7 @@
   ; CHECK-LABEL: name: fold_ashr_msb_2
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   TBNZX %copy, 63, %bb.1
@@ -281,6 +288,7 @@
   ; CHECK-LABEL: name: fold_lshr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
   ; CHECK-NEXT:   TBNZW %copy, 4, %bb.1
@@ -317,6 +325,7 @@
   ; CHECK-LABEL: name: fold_lshr_2
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   TBNZX %copy, 32, %bb.1
@@ -354,6 +363,7 @@
   ; CHECK-LABEL: name: dont_fold_lshr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
   ; CHECK-NEXT:   %fold_cst:gpr32 = MOVi32imm 29
@@ -393,6 +403,7 @@
   ; CHECK-LABEL: name: lshr_negative
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
   ; CHECK-NEXT:   TBNZW %copy, 2, %bb.1
Index: llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
@@ -10,6 +10,7 @@
   ; CHECK-LABEL: name: flip_eq
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64all = COPY $x0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
@@ -52,6 +53,7 @@
   ; CHECK-LABEL: name: flip_ne
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64all = COPY $x0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
@@ -89,6 +91,7 @@
   ; CHECK-LABEL: name: dont_flip_eq
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64all = COPY $x0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
@@ -165,6 +168,7 @@
   ; CHECK-LABEL: name: dont_flip_ne
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64all = COPY $x0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
@@ -202,6 +206,7 @@
   ; CHECK-LABEL: name: xor_chain
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64all = COPY $x0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
Index: llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
@@ -10,6 +10,7 @@
   ; CHECK-LABEL: name: condbr_of_not
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
   ; CHECK-NEXT:   [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
@@ -49,6 +50,7 @@
   ; CHECK-LABEL: name: condbr_of_not_64
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
   ; CHECK-NEXT:   [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
@@ -89,6 +91,7 @@
   ; CHECK-LABEL: name: condbr_of_and
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %lhs:gpr32 = COPY $w0
   ; CHECK-NEXT:   TBNZW %lhs, 0, %bb.2
@@ -122,6 +125,7 @@
   ; CHECK-LABEL: name: condbr_of_and_no_cst
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0, $w1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %lhs:gpr32 = COPY $w0
   ; CHECK-NEXT:   %rhs:gpr32 = COPY $w1
@@ -157,6 +161,7 @@
   ; CHECK-LABEL: name: condbr_of_shl
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %lhs:gpr32 = COPY $w0
   ; CHECK-NEXT:   %op:gpr32 = UBFMWri %lhs, 31, 30
@@ -195,6 +200,7 @@
   ; CHECK-LABEL: name: condbr_of_ashr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %lhs:gpr32 = COPY $w0
   ; CHECK-NEXT:   TBNZW %lhs, 1, %bb.2
@@ -232,6 +238,7 @@
   ; CHECK-LABEL: name: tbnzx
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %lhs:gpr64 = COPY $x0
   ; CHECK-NEXT:   TBNZX %lhs, 63, %bb.2
Index: llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
@@ -10,6 +10,7 @@
   ; CHECK-LABEL: name: cbz_s32
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
   ; CHECK-NEXT:   CBZW [[COPY]], %bb.1
@@ -39,6 +40,7 @@
   ; CHECK-LABEL: name: cbz_s64
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
   ; CHECK-NEXT:   CBZX [[COPY]], %bb.1
@@ -68,6 +70,7 @@
   ; CHECK-LABEL: name: cbnz_s32
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
   ; CHECK-NEXT:   CBNZW [[COPY]], %bb.1
@@ -97,6 +100,7 @@
   ; CHECK-LABEL: name: cbnz_s64
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
   ; CHECK-NEXT:   CBNZX [[COPY]], %bb.1
Index: llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
@@ -16,6 +16,7 @@
   ; CHECK-LABEL: name: tbnzx_slt
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   TBNZX %copy, 63, %bb.1
@@ -45,6 +46,7 @@
   ; CHECK-LABEL: name: tbnzw_slt
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
   ; CHECK-NEXT:   TBNZW %copy, 31, %bb.1
@@ -74,6 +76,7 @@
   ; CHECK-LABEL: name: no_tbnz_not_zero
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr32sp = COPY $w0
   ; CHECK-NEXT:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
@@ -104,6 +107,7 @@
   ; CHECK-LABEL: name: dont_fold_and
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %copy, 8000, implicit-def $nzcv
@@ -137,6 +141,7 @@
   ; CHECK-LABEL: name: dont_commute
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   %zero:gpr64 = COPY $xzr
Index: llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
@@ -16,6 +16,7 @@
   ; CHECK-LABEL: name: tbzx_sgt
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   TBZX %copy, 63, %bb.1
@@ -45,6 +46,7 @@
   ; CHECK-LABEL: name: tbzw_sgt
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
   ; CHECK-NEXT:   TBZW %copy, 31, %bb.1
@@ -74,6 +76,7 @@
   ; CHECK-LABEL: name: no_tbz_not_negative_one
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr32sp = COPY $w0
   ; CHECK-NEXT:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
@@ -104,6 +107,7 @@
   ; CHECK-LABEL: name: dont_fold_and
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   %and:gpr64sp = ANDXri %copy, 8000
@@ -138,6 +142,7 @@
   ; CHECK-LABEL: name: dont_commute
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
   ; CHECK-NEXT:   %negative_one:gpr64 = MOVi64imm -1
Index: llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
===================================================================
--- llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
+++ llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
@@ -272,6 +272,8 @@
 
   bb.1.return (address-taken):
     ; CHECK: bb.1.return (address-taken):
+    ; CHECK-NEXT: liveins:
+    ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: HINT 36
     liveins: $x8
 
@@ -283,6 +285,8 @@
 
   bb.2.lab2 (address-taken):
     ; CHECK: bb.2.lab2 (address-taken):
+    ; CHECK-NEXT: liveins:
+    ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: HINT 36
     liveins: $x8
 
@@ -315,6 +319,8 @@
 
   bb.1.return (address-taken):
     ; CHECK: bb.1.return (address-taken):
+    ; CHECK-NEXT: liveins:
+    ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: HINT 36
     liveins: $x8
     frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
Index: llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
===================================================================
--- llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
+++ llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
@@ -31,6 +31,8 @@
 
 # CHECK-LABEL: : test_1_callsite_info
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:    BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $x0, implicit $sp, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BLR $x0, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
 # CHECK-NEXT:      ORRXrs $xzr, $fp, 0
@@ -52,6 +54,8 @@
 
 # CHECK-LABEL: : test_bl_pass_x0_arg
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:     BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit $x0, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
 # CHECK-NEXT:      $fp = ORRXrs $xzr, $fp, 0
@@ -70,6 +74,8 @@
 
 # CHECK-LABEL: : test_bl_pass_x0_x1_x2_args
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:     BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def $x0, implicit-def $w0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $x0
 # CHECK-NEXT:      $fp = ORRXrs $xzr, $fp, 0
@@ -88,6 +94,8 @@
 
 # CHECK-LABEL: : test_bl_pass_w0_w1_args
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:     BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit $w0, implicit $w1, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $w1, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
 # CHECK-NEXT:      $fp = ORRXrs $xzr, $fp, 0
@@ -107,6 +115,8 @@
 
 # CHECK-LABEL: : test_blr_pass_w0_w1_args
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:     BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $x8, implicit $sp, implicit $w0, implicit $w1, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BLR $x8, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $w1, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
 # CHECK-NEXT:      $fp = ORRXrs $xzr, $fp, 0
Index: llvm/test/CodeGen/AArch64/framelayout-sve.mir
===================================================================
--- llvm/test/CodeGen/AArch64/framelayout-sve.mir
+++ llvm/test/CodeGen/AArch64/framelayout-sve.mir
@@ -116,6 +116,8 @@
 # CHECK:       stackSize: 48
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -32
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 32
 # CHECK-NEXT: frame-setup STPXi killed $x21, killed $x20, $sp, 2
@@ -194,6 +196,8 @@
 # CHECK:       stackSize: 32
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: $fp = frame-setup ADDXri $sp, 0, 0
@@ -257,6 +261,8 @@
 # CHECK:       stackSize: 32
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
@@ -338,6 +344,8 @@
 # CHECK:       stackSize: 32
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: $fp = frame-setup ADDXri $sp, 0, 0
@@ -414,6 +422,8 @@
 # CHECK:       stackSize: 32
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
@@ -485,6 +495,8 @@
 # CHECK:       stackSize: 16
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
@@ -617,6 +629,8 @@
 
 # CHECK-LABEL: name: test_address_gpr_vla
 # CHECK: bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: early-clobber $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -4
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 32
 # CHECK-NEXT: frame-setup STRXui killed $x19, $sp, 2
@@ -1165,6 +1179,8 @@
 # CHECK-NEXT:       stack-id: default, callee-saved-register: '$fp',
 #
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
Index: llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
+++ llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
@@ -10,8 +10,6 @@
 name:            hazard_buffer_store_v_interp
 body:             |
   bb.0.entry:
-    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10
-
     BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, implicit $exec
     $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $mode, implicit $m0, implicit $exec
     S_ENDPGM 0
Index: llvm/test/CodeGen/AMDGPU/optimize-compare.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/optimize-compare.mir
+++ llvm/test/CodeGen/AMDGPU/optimize-compare.mir
@@ -7,6 +7,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_u32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -43,6 +44,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_u32_1_used_and
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
@@ -81,6 +83,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_i32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -117,6 +120,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_i32_1_phys
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   $sgpr2 = S_AND_B32 1, killed [[COPY]], implicit-def dead $scc
@@ -154,6 +158,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_i32_1_different_blocks
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x80000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def dead $scc
@@ -199,6 +204,7 @@
   ; GCN-LABEL: name: and_3_cmp_eq_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 3, killed [[COPY]], implicit-def dead $scc
@@ -236,6 +242,7 @@
   ; GCN-LABEL: name: commuted_and_1_cmp_eq_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -272,6 +279,7 @@
   ; GCN-LABEL: name: cmp_eq_1_undef_src
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_CMP_EQ_U32 undef %1:sreg_32, 1, implicit-def $scc
@@ -307,6 +315,7 @@
   ; GCN-LABEL: name: and_1_cmp_subreg0_eq_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def dead $scc
@@ -346,6 +355,7 @@
   ; GCN-LABEL: name: and_reg_cmp_eq_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $sgpr1, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
@@ -385,6 +395,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_1_killed_scc
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
@@ -424,6 +435,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_1_clobbered_scc
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
@@ -463,6 +475,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_2
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def dead $scc
@@ -500,6 +513,7 @@
   ; GCN-LABEL: name: or_1_cmp_eq_u32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 1, killed [[COPY]], implicit-def dead $scc
@@ -537,6 +551,7 @@
   ; GCN-LABEL: name: and_1_cmp_ge_u32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -573,6 +588,7 @@
   ; GCN-LABEL: name: and_1_cmp_ge_i32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -609,6 +625,7 @@
   ; GCN-LABEL: name: and_1_cmp_gt_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -645,6 +662,7 @@
   ; GCN-LABEL: name: and_1_cmp_gt_i32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -681,6 +699,7 @@
   ; GCN-LABEL: name: and_1_cmp_gt_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def dead $scc
@@ -718,6 +737,7 @@
   ; GCN-LABEL: name: and_1_cmp_lg_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -754,6 +774,7 @@
   ; GCN-LABEL: name: and_1_cmp_lg_i32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -790,6 +811,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_u64_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
   ; GCN-NEXT:   S_BITCMP1_B64 killed [[COPY]], 0, implicit-def $scc
@@ -826,6 +848,7 @@
   ; GCN-LABEL: name: and_1_cmp_lg_u64_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
   ; GCN-NEXT:   S_BITCMP1_B64 killed [[COPY]], 0, implicit-def $scc
@@ -862,6 +885,7 @@
   ; GCN-LABEL: name: and_1_cmpk_eq_u32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -898,6 +922,7 @@
   ; GCN-LABEL: name: and_1_cmpk_eq_i32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -934,6 +959,7 @@
   ; GCN-LABEL: name: and_1_cmpk_ge_u32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -970,6 +996,7 @@
   ; GCN-LABEL: name: and_1_cmpk_ge_i32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -1006,6 +1033,7 @@
   ; GCN-LABEL: name: and_1_cmpk_lg_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -1042,6 +1070,7 @@
   ; GCN-LABEL: name: and_1_cmpk_lg_i32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -1078,6 +1107,7 @@
   ; GCN-LABEL: name: and_1_cmpk_gt_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -1114,6 +1144,7 @@
   ; GCN-LABEL: name: and_1_cmpk_gt_i32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
@@ -1150,6 +1181,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_u32_1_imm_src
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   S_BITCMP1_B32 11, 0, implicit-def $scc
   ; GCN-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit $scc
@@ -1184,6 +1216,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP0_B32 killed [[COPY]], 0, implicit-def $scc
@@ -1220,6 +1253,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_i32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP0_B32 killed [[COPY]], 0, implicit-def $scc
@@ -1256,6 +1290,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_u64_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
   ; GCN-NEXT:   S_BITCMP0_B64 killed [[COPY]], 0, implicit-def $scc
@@ -1292,6 +1327,7 @@
   ; GCN-LABEL: name: and_1_cmp_lg_u32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP0_B32 killed [[COPY]], 0, implicit-def $scc
@@ -1328,6 +1364,7 @@
   ; GCN-LABEL: name: and_1_cmp_lg_i32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP0_B32 killed [[COPY]], 0, implicit-def $scc
@@ -1364,6 +1401,7 @@
   ; GCN-LABEL: name: and_1_cmp_lg_u64_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
   ; GCN-NEXT:   S_BITCMP0_B64 killed [[COPY]], 0, implicit-def $scc
@@ -1400,6 +1438,7 @@
   ; GCN-LABEL: name: and_1_cmp_eq_u32_0_used_and
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def dead $scc
@@ -1439,6 +1478,7 @@
   ; GCN-LABEL: name: and_1_cmp_ge_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def dead $scc
@@ -1476,6 +1516,7 @@
   ; GCN-LABEL: name: and_1_cmp_gt_u32_1
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def dead $scc
@@ -1513,6 +1554,7 @@
   ; GCN-LABEL: name: and_1_folded_src0_cmp_eq_u32_1_folded_src2
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
@@ -1551,6 +1593,7 @@
   ; GCN-LABEL: name: and_1_folded_src1_cmp_eq_u32_1_folded_src2
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
@@ -1589,6 +1632,7 @@
   ; GCN-LABEL: name: and_1_folded_src1_cmp_eq_u64_1_folded_src2
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
   ; GCN-NEXT:   [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 1
@@ -1627,6 +1671,7 @@
   ; GCN-LABEL: name: and_1024_cmp_eq_u32_1024
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 10, implicit-def $scc
@@ -1663,6 +1708,7 @@
   ; GCN-LABEL: name: and_0x80000000_cmp_eq_u32_0x80000000
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 31, implicit-def $scc
@@ -1699,6 +1745,7 @@
   ; GCN-LABEL: name: and_0x80000000_cmp_ge_u32_0x80000000
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 31, implicit-def $scc
@@ -1735,6 +1782,7 @@
   ; GCN-LABEL: name: and_0x80000000_cmp_ge_i32_0x80000000
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 2147483648, killed [[COPY]], implicit-def dead $scc
@@ -1772,6 +1820,7 @@
   ; GCN-LABEL: name: and_1024_cmp_ge_i32_1024
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 10, implicit-def $scc
@@ -1808,6 +1857,7 @@
   ; GCN-LABEL: name: and_0x80000000_cmp_lg_i32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 31, implicit-def $scc
@@ -1844,6 +1894,7 @@
   ; GCN-LABEL: name: and_0x80000000_cmp_gt_i32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 2147483648, killed [[COPY]], implicit-def dead $scc
@@ -1881,6 +1932,7 @@
   ; GCN-LABEL: name: and_0x80000000_cmp_gt_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 31, implicit-def $scc
@@ -1917,6 +1969,7 @@
   ; GCN-LABEL: name: and_0x80000000_cmp_eq_u64_0x80000000
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
   ; GCN-NEXT:   S_BITCMP1_B64 killed [[COPY]], 35, implicit-def $scc
@@ -1953,6 +2006,7 @@
   ; GCN-LABEL: name: and_0x8000000000000000_cmp_eq_u64_0x8000000000000000
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
   ; GCN-NEXT:   S_BITCMP1_B64 killed [[COPY]], 63, implicit-def $scc
@@ -1989,6 +2043,7 @@
   ; GCN-LABEL: name: and_2_cmp_eq_u32_2_used_and
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 2, killed [[COPY]], implicit-def $scc
@@ -2028,6 +2083,7 @@
   ; GCN-LABEL: name: and_3_cmp_eq_u32_3
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 3, killed [[COPY]], implicit-def dead $scc
@@ -2065,6 +2121,7 @@
   ; GCN-LABEL: name: and_3_cmp_lg_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 3, killed [[COPY]], implicit-def dead $scc
@@ -2102,6 +2159,7 @@
   ; GCN-LABEL: name: and_4_cmp_lg_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP1_B32 killed [[COPY]], 2, implicit-def $scc
@@ -2138,6 +2196,7 @@
   ; GCN-LABEL: name: and_0x80000000_cmp_eq_u32_0
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   S_BITCMP0_B32 killed [[COPY]], 31, implicit-def $scc
@@ -2174,6 +2233,7 @@
   ; GCN-LABEL: name: and_0x8000000000000000_cmp_lg_u64_0x8000000000000000
   ; GCN: bb.0:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
   ; GCN-NEXT:   S_BITCMP0_B64 killed [[COPY]], 63, implicit-def $scc
Index: llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
===================================================================
--- llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
+++ llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
@@ -6,6 +6,8 @@
   bb.0:
 
     ;CHECK-LABEL: bb.0
+    ;CHECK-NEXT: liveins
+    ;CHECK-NEXT: {{  $}}
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(p0) = COPY $d0
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(<4 x s32>) = COPY $q0
     ;CHECK-NEXT: G_STORE %bb0_{{[0-9]+}}__1(<4 x s32>), %bb0_{{[0-9]+}}__1(p0) :: (store (<4 x s32>))
@@ -74,6 +76,8 @@
     liveins: $x0, $x1, $d0, $d1
 
     ;CHECK-LABEL: bb.0:
+    ;CHECK-NEXT: liveins
+    ;CHECK-NEXT: {{  $}}
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui %stack.0, 0
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1
Index: llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
===================================================================
--- llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
+++ llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
@@ -33,7 +33,9 @@
 # CHECK-LABEL: name: testBuildPairF64
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
+
 # CHECK-NEXT: BuildPairF64
 body: |
   bb.0:
@@ -48,6 +50,7 @@
 # CHECK-LABEL: name: testBuildPairF64_64
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: BuildPairF64_64
 body: |
@@ -63,6 +66,7 @@
 # CHECK-LABEL: name: testBuildPairF64implicitSp
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
 body: |
@@ -78,6 +82,7 @@
 # CHECK-LABEL: name: testBuildPairF64_64implicitSp
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
 body: |
@@ -93,6 +98,7 @@
 # CHECK-LABEL: name: testExtractElementF64
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: ExtractElementF64
 body: |
@@ -108,6 +114,7 @@
 # CHECK-LABEL: name: testExtractElementF64_64
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: ExtractElementF64_64
 body: |
@@ -123,6 +130,7 @@
 # CHECK-LABEL: name: testExtractElementF64implicitSp
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
 body: |
@@ -138,6 +146,7 @@
 # CHECK-LABEL: name: testExtractElementF64_64implicitSp
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
 body: |
Index: llvm/test/CodeGen/RISCV/copy-frameindex.mir
===================================================================
--- llvm/test/CodeGen/RISCV/copy-frameindex.mir
+++ llvm/test/CodeGen/RISCV/copy-frameindex.mir
@@ -40,6 +40,7 @@
   ; CHECK-LABEL: name: sink_addi_fi
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x10
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
   ; CHECK-NEXT:   BEQ killed [[COPY]], $x0, %bb.2
Index: llvm/test/CodeGen/X86/flags-copy-lowering.mir
===================================================================
--- llvm/test/CodeGen/X86/flags-copy-lowering.mir
+++ llvm/test/CodeGen/X86/flags-copy-lowering.mir
@@ -4,9 +4,9 @@
 
 --- |
   target triple = "x86_64-unknown-unknown"
-  
+
   declare void @foo()
-  
+
   define i32 @test_branch(i64 %a, i64 %b) {
   entry:
     call void @foo()
@@ -106,14 +106,14 @@
 ---
 name:            test_branch
 # CHECK-LABEL: name: test_branch
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     successors: %bb.1, %bb.2, %bb.3
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
@@ -142,17 +142,17 @@
   ; CHECK-NEXT:   TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
   ; CHECK-NEXT:   JCC_1 %bb.2, 5, implicit killed $eflags
   ; CHECK-NEXT:   JMP_1 %bb.3
-  
+
   bb.1:
     %3:gr32 = MOV32ri 42
     $eax = COPY %3
     RET 0, $eax
-  
+
   bb.2:
     %4:gr32 = MOV32ri 43
     $eax = COPY %4
     RET 0, $eax
-  
+
   bb.3:
     %5:gr32 = MOV32r0 implicit-def dead $eflags
     $eax = COPY %5
@@ -162,14 +162,14 @@
 ---
 name:            test_branch_fallthrough
 # CHECK-LABEL: name: test_branch_fallthrough
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     successors: %bb.1, %bb.2, %bb.3
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
@@ -203,28 +203,28 @@
     %5:gr32 = MOV32r0 implicit-def dead $eflags
     $eax = COPY %5
     RET 0, $eax
-  
+
   bb.2:
     %3:gr32 = MOV32ri 42
     $eax = COPY %3
     RET 0, $eax
-  
+
   bb.3:
     %4:gr32 = MOV32ri 43
     $eax = COPY %4
     RET 0, $eax
-  
+
 ...
 ---
 name:            test_setcc
 # CHECK-LABEL: name: test_setcc
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
@@ -261,13 +261,13 @@
 ---
 name:            test_cmov
 # CHECK-LABEL: name: test_cmov
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
@@ -307,13 +307,13 @@
 ---
 name:            test_adc
 # CHECK-LABEL: name: test_adc
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -341,13 +341,13 @@
 ---
 name:            test_sbb
 # CHECK-LABEL: name: test_sbb
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = SUB64rr %0, %1, implicit-def $eflags
@@ -375,13 +375,13 @@
 ---
 name:            test_adcx
 # CHECK-LABEL: name: test_adcx
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -414,13 +414,13 @@
 ---
 name:            test_adox
 # CHECK-LABEL: name: test_adox
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -453,13 +453,13 @@
 ---
 name:            test_rcl
 # CHECK-LABEL: name: test_rcl
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -487,13 +487,13 @@
 ---
 name:            test_rcr
 # CHECK-LABEL: name: test_rcr
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -920,6 +920,7 @@
     $rax = COPY %8
     RET 0, $rax
   ; CHECK:      bb.9:
+  ; CHECK-NEXT: liveins: $eflags
   ; CHECK-NOT:     $eflags
   ; CHECK:         %8:gr64 = CMOV64rr %0, %1, 4, implicit killed $eflags
 
Index: llvm/test/CodeGen/X86/optimize-compare.mir
===================================================================
--- llvm/test/CodeGen/X86/optimize-compare.mir
+++ llvm/test/CodeGen/X86/optimize-compare.mir
@@ -609,6 +609,7 @@
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
+  ; CHECK-NEXT:   liveins: $eflags
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   JCC_1 %bb.2, 15, implicit $eflags
   ; CHECK-NEXT:   JMP_1 %bb.3
@@ -659,6 +660,7 @@
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT:   liveins: $eflags
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   $al = SETCCr 4, implicit $eflags
   ; CHECK-NEXT: {{  $}}
@@ -725,6 +727,8 @@
   ; CHECK-NEXT:   JMP_1 %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   liveins: $eflags
+  ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   $al = SETCCr 14, implicit $eflags
   bb.0:
     %0:gr64 = COPY $rsi
Index: llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected
===================================================================
--- llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected
+++ llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected
@@ -30,6 +30,7 @@
   ; CHECK-LABEL: name: test
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $edi
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; CHECK-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
Index: llvm/test/tools/llvm-reduce/mir/tracks-reg-liveness.mir
===================================================================
--- /dev/null
+++ llvm/test/tools/llvm-reduce/mir/tracks-reg-liveness.mir
@@ -0,0 +1,29 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -simplify-mir --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: V_MOV_B32_e32 $vgpr0
+# CHECK-INTERESTINGNESS: S_NOP 0
+
+# The block liveins list needs to be carried through even though this
+# tracksRegLiveness is false
+
+# RESULT: bb.0:
+# RESULT-NEXT: liveins: $vgpr0, $vgpr1_vgpr2
+# RESULT: %0:vgpr_32 = V_MOV_B32_e32 $vgpr0, implicit $exec
+# RESULT-NEXT: S_NOP 0
+# RESULT-NEXT: S_ENDPGM 0, implicit %0, implicit %0
+
+---
+name: func
+tracksRegLiveness: false
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1_vgpr2
+    S_WAITCNT 0
+    %0:vgpr_32 = V_MOV_B32_e32 $vgpr0, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_e32 $vgpr1, implicit $exec
+    S_NOP 0
+    S_ENDPGM 0, implicit %0, implicit %1
+...
+
Index: llvm/tools/llvm-reduce/ReducerWorkItem.cpp
===================================================================
--- llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -270,7 +270,8 @@
       auto *DstSuccMBB = Src2DstMBB[SrcSuccMBB];
       DstMBB->addSuccessor(DstSuccMBB, SrcMBB.getSuccProbability(It));
     }
-    for (auto &LI : SrcMBB.liveins())
+
+    for (auto &LI : SrcMBB.liveins_dbg())
       DstMBB->addLiveIn(LI);
 
     // Make sure MRI knows about registers clobbered by unwinder.