diff --git a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll --- a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll +++ b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -code-model=small -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -code-model=small -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I-SMALL -; RUN: llc -mtriple=riscv32 -mattr=+f -code-model=medium -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -code-model=medium -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM ; Check lowering of globals @@ -127,22 +127,18 @@ define float @lower_constantpool(float %a) nounwind { ; RV32I-SMALL-LABEL: lower_constantpool: ; RV32I-SMALL: # %bb.0: -; RV32I-SMALL-NEXT: lui a1, %hi(.LCPI3_0) -; RV32I-SMALL-NEXT: flw ft0, %lo(.LCPI3_0)(a1) -; RV32I-SMALL-NEXT: fmv.w.x ft1, a0 -; RV32I-SMALL-NEXT: fadd.s ft0, ft1, ft0 -; RV32I-SMALL-NEXT: fmv.x.w a0, ft0 +; RV32I-SMALL-NEXT: lui a0, %hi(.LCPI3_0) +; RV32I-SMALL-NEXT: flw ft0, %lo(.LCPI3_0)(a0) +; RV32I-SMALL-NEXT: fadd.s fa0, fa0, ft0 ; RV32I-SMALL-NEXT: ret ; ; RV32I-MEDIUM-LABEL: lower_constantpool: ; RV32I-MEDIUM: # %bb.0: ; RV32I-MEDIUM-NEXT: .LBB3_1: # Label of block must be emitted -; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI3_0) -; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB3_1) -; RV32I-MEDIUM-NEXT: flw ft0, 0(a1) -; RV32I-MEDIUM-NEXT: fmv.w.x ft1, a0 -; RV32I-MEDIUM-NEXT: fadd.s ft0, ft1, ft0 -; RV32I-MEDIUM-NEXT: fmv.x.w a0, ft0 +; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(.LCPI3_0) +; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB3_1) +; RV32I-MEDIUM-NEXT: flw ft0, 0(a0) +; RV32I-MEDIUM-NEXT: fadd.s fa0, fa0, ft0 ; RV32I-MEDIUM-NEXT: ret %1 = fadd float %a, 1.0 ret float %1 diff --git a/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll b/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll --- a/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll +++ b/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck %s -check-prefix=RV64IF ; This file exhaustively checks float<->i32 conversions. In general, @@ -10,8 +10,7 @@ define i32 @aext_fptosi(float %a) nounwind strictfp { ; RV64IF-LABEL: aext_fptosi: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp ret i32 %1 @@ -21,8 +20,7 @@ define signext i32 @sext_fptosi(float %a) nounwind strictfp { ; RV64IF-LABEL: sext_fptosi: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp ret i32 %1 @@ -31,8 +29,7 @@ define zeroext i32 @zext_fptosi(float %a) nounwind strictfp { ; RV64IF-LABEL: zext_fptosi: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz ; RV64IF-NEXT: slli a0, a0, 32 ; RV64IF-NEXT: srli a0, a0, 32 ; RV64IF-NEXT: ret @@ -43,8 +40,7 @@ define i32 @aext_fptoui(float %a) nounwind strictfp { ; RV64IF-LABEL: aext_fptoui: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp ret i32 %1 @@ -54,8 +50,7 @@ define signext i32 @sext_fptoui(float %a) nounwind strictfp { ; RV64IF-LABEL: sext_fptoui: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp ret i32 %1 @@ -64,8 +59,7 @@ define zeroext i32 @zext_fptoui(float %a) nounwind strictfp { ; RV64IF-LABEL: zext_fptoui: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp ret i32 %1 @@ -74,8 +68,7 @@ define float @uitofp_aext_i32_to_f32(i32 %a) nounwind strictfp { ; RV64IF-LABEL: uitofp_aext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.wu fa0, a0 ; RV64IF-NEXT: ret %1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp ret float %1 @@ -85,8 +78,7 @@ define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp { ; RV64IF-LABEL: uitofp_sext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.wu fa0, a0 ; RV64IF-NEXT: ret %1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp ret float %1 @@ -95,8 +87,7 @@ define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp { ; RV64IF-LABEL: uitofp_zext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.wu fa0, a0 ; RV64IF-NEXT: ret %1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp ret float %1 @@ -105,8 +96,7 @@ define float @sitofp_aext_i32_to_f32(i32 %a) nounwind strictfp { ; RV64IF-LABEL: sitofp_aext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.w fa0, a0 ; RV64IF-NEXT: ret %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp ret float %1 @@ -116,8 +106,7 @@ define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp { ; RV64IF-LABEL: sitofp_sext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.w fa0, a0 ; RV64IF-NEXT: ret %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp ret float %1 @@ -126,8 +115,7 @@ define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp { ; RV64IF-LABEL: sitofp_zext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.w fa0, a0 ; RV64IF-NEXT: ret %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp ret float %1 diff --git a/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll b/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll --- a/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll +++ b/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IF ; This file exhaustively checks float<->i32 conversions. In general, @@ -10,8 +10,7 @@ define i32 @aext_fptosi(float %a) nounwind { ; RV64IF-LABEL: aext_fptosi: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = fptosi float %a to i32 ret i32 %1 @@ -20,8 +19,7 @@ define signext i32 @sext_fptosi(float %a) nounwind { ; RV64IF-LABEL: sext_fptosi: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = fptosi float %a to i32 ret i32 %1 @@ -30,8 +28,7 @@ define zeroext i32 @zext_fptosi(float %a) nounwind { ; RV64IF-LABEL: zext_fptosi: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz ; RV64IF-NEXT: slli a0, a0, 32 ; RV64IF-NEXT: srli a0, a0, 32 ; RV64IF-NEXT: ret @@ -42,8 +39,7 @@ define i32 @aext_fptoui(float %a) nounwind { ; RV64IF-LABEL: aext_fptoui: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = fptoui float %a to i32 ret i32 %1 @@ -52,8 +48,7 @@ define signext i32 @sext_fptoui(float %a) nounwind { ; RV64IF-LABEL: sext_fptoui: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = fptoui float %a to i32 ret i32 %1 @@ -62,8 +57,7 @@ define zeroext i32 @zext_fptoui(float %a) nounwind { ; RV64IF-LABEL: zext_fptoui: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz +; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: ret %1 = fptoui float %a to i32 ret i32 %1 @@ -72,9 +66,7 @@ define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind { ; RV64IF-LABEL: bcvt_f32_to_aext_i32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a1 -; RV64IF-NEXT: fmv.w.x ft1, a0 -; RV64IF-NEXT: fadd.s ft0, ft1, ft0 +; RV64IF-NEXT: fadd.s ft0, fa0, fa1 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %1 = fadd float %a, %b @@ -85,9 +77,7 @@ define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind { ; RV64IF-LABEL: bcvt_f32_to_sext_i32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a1 -; RV64IF-NEXT: fmv.w.x ft1, a0 -; RV64IF-NEXT: fadd.s ft0, ft1, ft0 +; RV64IF-NEXT: fadd.s ft0, fa0, fa1 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %1 = fadd float %a, %b @@ -98,9 +88,7 @@ define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind { ; RV64IF-LABEL: bcvt_f32_to_zext_i32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a1 -; RV64IF-NEXT: fmv.w.x ft1, a0 -; RV64IF-NEXT: fadd.s ft0, ft1, ft0 +; RV64IF-NEXT: fadd.s ft0, fa0, fa1 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: slli a0, a0, 32 ; RV64IF-NEXT: srli a0, a0, 32 @@ -115,8 +103,7 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft1, a1 -; RV64IF-NEXT: fadd.s ft0, ft0, ft1 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fadd.s fa0, ft0, ft1 ; RV64IF-NEXT: ret %1 = trunc i64 %a to i32 %2 = trunc i64 %b to i32 @@ -129,8 +116,7 @@ define float @uitofp_aext_i32_to_f32(i32 %a) nounwind { ; RV64IF-LABEL: uitofp_aext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.wu fa0, a0 ; RV64IF-NEXT: ret %1 = uitofp i32 %a to float ret float %1 @@ -139,8 +125,7 @@ define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind { ; RV64IF-LABEL: uitofp_sext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.wu fa0, a0 ; RV64IF-NEXT: ret %1 = uitofp i32 %a to float ret float %1 @@ -149,8 +134,7 @@ define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind { ; RV64IF-LABEL: uitofp_zext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.wu fa0, a0 ; RV64IF-NEXT: ret %1 = uitofp i32 %a to float ret float %1 @@ -159,8 +143,7 @@ define float @sitofp_aext_i32_to_f32(i32 %a) nounwind { ; RV64IF-LABEL: sitofp_aext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.w fa0, a0 ; RV64IF-NEXT: ret %1 = sitofp i32 %a to float ret float %1 @@ -169,8 +152,7 @@ define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind { ; RV64IF-LABEL: sitofp_sext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.w fa0, a0 ; RV64IF-NEXT: ret %1 = sitofp i32 %a to float ret float %1 @@ -179,8 +161,7 @@ define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind { ; RV64IF-LABEL: sitofp_zext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w ft0, a0 -; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: fcvt.s.w fa0, a0 ; RV64IF-NEXT: ret %1 = sitofp i32 %a to float ret float %1