diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp @@ -543,15 +543,15 @@ if (Opcode != ISD::VP_SELECT && Opcode != ISD::VP_MERGE) { Lo = DAG.getNode(Opcode, dl, LL.getValueType(), CL, LL, RL); Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH); - return; + } else { + assert((Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE) && + "Expected VP_SELECT Or VP_MERGE Opcode"); + SDValue EVLLo, EVLHi; + std::tie(EVLLo, EVLHi) = + DAG.SplitEVL(N->getOperand(3), N->getValueType(0), dl); + Lo = DAG.getNode(Opcode, dl, LL.getValueType(), CL, LL, RL, EVLLo); + Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH, EVLHi); } - - SDValue EVLLo, EVLHi; - std::tie(EVLLo, EVLHi) = - DAG.SplitEVL(N->getOperand(3), N->getValueType(0), dl); - - Lo = DAG.getNode(Opcode, dl, LL.getValueType(), CL, LL, RL, EVLLo); - Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH, EVLHi); } void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo,