Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -915,6 +915,59 @@
   return CurInfo.isCompatibleWithLoadStoreEEW(EEW, Require);
 }
 
+bool isFaultFirstLoad(const MachineInstr &MI) {
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case RISCV::PseudoVLE8FF_V_M1:
+  case RISCV::PseudoVLE8FF_V_M1_MASK:
+  case RISCV::PseudoVLE8FF_V_M2:
+  case RISCV::PseudoVLE8FF_V_M2_MASK:
+  case RISCV::PseudoVLE8FF_V_M4:
+  case RISCV::PseudoVLE8FF_V_M4_MASK:
+  case RISCV::PseudoVLE8FF_V_M8:
+  case RISCV::PseudoVLE8FF_V_M8_MASK:
+  case RISCV::PseudoVLE8FF_V_MF2:
+  case RISCV::PseudoVLE8FF_V_MF2_MASK:
+  case RISCV::PseudoVLE8FF_V_MF4:
+  case RISCV::PseudoVLE8FF_V_MF4_MASK:
+  case RISCV::PseudoVLE8FF_V_MF8:
+  case RISCV::PseudoVLE8FF_V_MF8_MASK:
+  case RISCV::PseudoVLE16FF_V_M1:
+  case RISCV::PseudoVLE16FF_V_M1_MASK:
+  case RISCV::PseudoVLE16FF_V_M2:
+  case RISCV::PseudoVLE16FF_V_M2_MASK:
+  case RISCV::PseudoVLE16FF_V_M4:
+  case RISCV::PseudoVLE16FF_V_M4_MASK:
+  case RISCV::PseudoVLE16FF_V_M8:
+  case RISCV::PseudoVLE16FF_V_M8_MASK:
+  case RISCV::PseudoVLE16FF_V_MF2:
+  case RISCV::PseudoVLE16FF_V_MF2_MASK:
+  case RISCV::PseudoVLE16FF_V_MF4:
+  case RISCV::PseudoVLE16FF_V_MF4_MASK:
+  case RISCV::PseudoVLE32FF_V_M1:
+  case RISCV::PseudoVLE32FF_V_M1_MASK:
+  case RISCV::PseudoVLE32FF_V_M2:
+  case RISCV::PseudoVLE32FF_V_M2_MASK:
+  case RISCV::PseudoVLE32FF_V_M4:
+  case RISCV::PseudoVLE32FF_V_M4_MASK:
+  case RISCV::PseudoVLE32FF_V_M8:
+  case RISCV::PseudoVLE32FF_V_M8_MASK:
+  case RISCV::PseudoVLE32FF_V_MF2:
+  case RISCV::PseudoVLE32FF_V_MF2_MASK:
+  case RISCV::PseudoVLE64FF_V_M1:
+  case RISCV::PseudoVLE64FF_V_M1_MASK:
+  case RISCV::PseudoVLE64FF_V_M2:
+  case RISCV::PseudoVLE64FF_V_M2_MASK:
+  case RISCV::PseudoVLE64FF_V_M4:
+  case RISCV::PseudoVLE64FF_V_M4_MASK:
+  case RISCV::PseudoVLE64FF_V_M8:
+  case RISCV::PseudoVLE64FF_V_M8_MASK:
+    return true;
+  };
+}
+
+
 bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB) {
   bool HadVectorOp = false;
 
@@ -953,8 +1006,20 @@
     // If this is something that updates VL/VTYPE that we don't know about, set
     // the state to unknown.
     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
-        MI.modifiesRegister(RISCV::VTYPE))
-      BBInfo.Change = VSETVLIInfo::getUnknown();
+        MI.modifiesRegister(RISCV::VTYPE)) {
+      bool Handled = false;
+      if (isFaultFirstLoad(MI)) {
+        if (std::next(MI.getIterator()) != MBB.end()) {
+          const MachineInstr &NextMI = *std::next(MI.getIterator());
+          if (NextMI.getOpcode() == RISCV::PseudoReadVL) {
+            BBInfo.Change.setAVLReg(NextMI.getOperand(0).getReg());
+            Handled = true;
+          }
+        }
+      }
+      if (!Handled)
+        BBInfo.Change = VSETVLIInfo::getUnknown();
+    }
   }
 
   return HadVectorOp;
@@ -1149,7 +1214,18 @@
     // the state to unknown.
     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
         MI.modifiesRegister(RISCV::VTYPE)) {
-      CurInfo = VSETVLIInfo::getUnknown();
+      bool Handled = false;
+      if (isFaultFirstLoad(MI)) {
+        if (std::next(MI.getIterator()) != MBB.end()) {
+          const MachineInstr &NextMI = *std::next(MI.getIterator());
+          if (NextMI.getOpcode() == RISCV::PseudoReadVL) {
+            CurInfo.setAVLReg(NextMI.getOperand(0).getReg());
+            Handled = true;
+          }
+        }
+      }
+      if (!Handled)
+        CurInfo = VSETVLIInfo::getUnknown();
       PrevVSETVLIMI = nullptr;
     }
   }
@@ -1273,8 +1349,20 @@
     // If this is something that updates VL/VTYPE that we don't know about,
     // set the state to unknown.
     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
-        MI.modifiesRegister(RISCV::VTYPE))
-      CurInfo = VSETVLIInfo::getUnknown();
+        MI.modifiesRegister(RISCV::VTYPE)) {
+      bool Handled = false;
+      if (isFaultFirstLoad(MI)) {
+        if (std::next(MI.getIterator()) != MBB.end()) {
+          const MachineInstr &NextMI = *std::next(MI.getIterator());
+          if (NextMI.getOpcode() == RISCV::PseudoReadVL) {
+            CurInfo.setAVLReg(NextMI.getOperand(0).getReg());
+            Handled = true;
+          }
+        }
+      }
+      if (!Handled)
+        CurInfo = VSETVLIInfo::getUnknown();
+    }
   }
 }
 
Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -502,7 +502,7 @@
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64ff.v v8, (a0)
 ; CHECK-NEXT:    csrr a0, vl
-; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, mu
+; CHECK-NEXT:    vsetvli zero, zero, e64, m1, tu, mu
 ; CHECK-NEXT:    vadd.vx v8, v8, a2
 ; CHECK-NEXT:    ret
 entry: