diff --git a/bolt/lib/Target/X86/CMakeLists.txt b/bolt/lib/Target/X86/CMakeLists.txt
--- a/bolt/lib/Target/X86/CMakeLists.txt
+++ b/bolt/lib/Target/X86/CMakeLists.txt
@@ -4,7 +4,7 @@
   MC
   MCDisassembler
   Support
-  X86Desc
+  X86CodeGen
   )
 
 add_llvm_library(LLVMBOLTTargetX86
diff --git a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
--- a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -13,6 +13,7 @@
 #include "MCTargetDesc/X86BaseInfo.h"
 #include "MCTargetDesc/X86InstrRelaxTables.h"
 #include "MCTargetDesc/X86MCTargetDesc.h"
+#include "X86InstrInfo.h"
 #include "X86MCSymbolizer.h"
 #include "bolt/Core/MCPlus.h"
 #include "bolt/Core/MCPlusBuilder.h"
@@ -1003,6 +1004,76 @@
     }
   }
 
+  static uint8_t getMemDataSize(const MCInst &Inst, int MemOpNo) {
+    using namespace X86::OpTypes;
+    switch (X86::getOperandType(Inst, MemOpNo)) {
+    default:
+      return 0;
+    case i8mem:
+    case i8mem_NOREX:
+      return 1;
+    case i16mem:
+    case f16mem:
+      return 2;
+    case i32mem:
+    case i32mem_TC:
+    case f32mem:
+      return 4;
+
+    case i64mem:
+    case i64mem_TC:
+    case f64mem:
+    case vx64mem:
+    case vx64xmem:
+      return 8;
+
+    case f80mem:
+      return 10;
+
+    case i128mem:
+    case f128mem:
+    case vx128mem:
+    case vx128xmem:
+    case vy128mem:
+    case vy128xmem:
+      return 16;
+
+    case i256mem:
+    case f256mem:
+    case vx256mem:
+    case vx256xmem:
+    case vy256mem:
+    case vy256xmem:
+    case vz256mem:
+      return 32;
+
+    case i512mem:
+    case f512mem:
+    case vy512xmem:
+    case vz512mem:
+      return 64;
+    }
+  }
+
+  /// Classifying a stack access as *not* "SIMPLE" here means we don't know how
+  /// to change this instruction memory access. It will disable any changes to
+  /// the stack layout, so we can't do the most aggressive form of shrink
+  /// wrapping. We must do so in a way that keeps the original stack layout.
+  /// Otherwise you need to adjust the offset of all instructions accessing the
+  /// stack: we can't do that anymore because there is one instruction that is
+  /// not simple. There are other implications as well. We have heuristics to
+  /// detect when a register is callee-saved and thus eligible for shrink
+  /// wrapping. If you are restoring a register using a non-simple stack access,
+  /// then it is classified as NOT callee-saved, and it disables shrink wrapping
+  /// for *that* register (but not for others).
+  ///
+  /// Classifying a stack access as "size 0" or detecting an indexed memory
+  /// access (to address a vector, for example) here means we know there is a
+  /// stack access, but we can't quite understand how wide is the access in
+  /// bytes. This is very serious because we can't understand how memory accesses
+  /// alias with each other for this function. This will essentially disable not
+  /// only shrink wrapping but all frame analysis, it will fail it as "we don't
+  /// understand this function and we give up on it".
   bool isStackAccess(const MCInst &Inst, bool &IsLoad, bool &IsStore,
                      bool &IsStoreFromReg, MCPhysReg &Reg, int32_t &SrcImm,
                      uint16_t &StackPtrReg, int64_t &StackOffset, uint8_t &Size,
@@ -1058,24 +1129,12 @@
 
     switch (Inst.getOpcode()) {
     default: {
-      uint8_t Sz = 0;
       bool IsLoad = MCII.mayLoad();
       bool IsStore = MCII.mayStore();
       // Is it LEA? (deals with memory but is not loading nor storing)
       if (!IsLoad && !IsStore)
         return false;
-
-      // Try to guess data size involved in the load/store by looking at the
-      // register size. If there's no reg involved, return 0 as size, meaning
-      // we don't know.
-      for (unsigned I = 0, E = MCII.getNumOperands(); I != E; ++I) {
-        if (MCII.OpInfo[I].OperandType != MCOI::OPERAND_REGISTER)
-          continue;
-        if (static_cast<int>(I) >= MemOpNo && I < X86::AddrNumOperands)
-          continue;
-        Sz = RegInfo->getRegClass(MCII.OpInfo[I].RegClass).getSizeInBits() / 8;
-        break;
-      }
+      uint8_t Sz = getMemDataSize(Inst, MemOpNo);
       I = {Sz, IsLoad, IsStore, false, false};
       break;
     }
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -21,6 +21,7 @@
 #include <vector>
 
 #define GET_INSTRINFO_HEADER
+#define GET_INSTRINFO_OPERAND_TYPES_ENUM
 #include "X86GenInstrInfo.inc"
 
 namespace llvm {
@@ -75,6 +76,8 @@
 
 /// Check if the instruction is X87 instruction.
 bool isX87Instruction(MachineInstr &MI);
+
+OpTypes::OperandType getOperandType(const MCInst &Inst, unsigned OpIdx);
 } // namespace X86
 
 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -9648,4 +9648,10 @@
 }
 
 #define GET_INSTRINFO_HELPERS
+#define GET_INSTRINFO_OPERAND_TYPE
 #include "X86GenInstrInfo.inc"
+
+X86::OpTypes::OperandType X86::getOperandType(const MCInst &Inst,
+                                              unsigned OpIdx) {
+  return (X86::OpTypes::OperandType)getOperandType(Inst.getOpcode(), OpIdx);
+}