diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -220,6 +220,7 @@ class SM_Inval_Pseudo : SM_Pseudo< opName, (outs), (ins), "", [(node)]> { let hasSideEffects = 1; + let mayLoad = 0; let mayStore = 0; let has_sdst = 0; let has_sbase = 0; diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll @@ -16,7 +16,7 @@ ; GCN-LABEL: {{^}}test_s_dcache_inv_vol_insert_wait: ; GCN-NEXT: ; %bb.0: -; GCN-NEXT: s_dcache_inv_vol +; GCN: s_dcache_inv_vol ; GCN: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_inv_vol_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.inv.vol() diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll @@ -14,7 +14,7 @@ ; VI-LABEL: {{^}}test_s_dcache_wb_insert_wait: ; VI-NEXT: ; %bb.0: -; VI-NEXT: s_dcache_wb +; VI: s_dcache_wb ; VI: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_wb_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.wb() diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll @@ -14,7 +14,7 @@ ; VI-LABEL: {{^}}test_s_dcache_wb_vol_insert_wait: ; VI-NEXT: ; %bb.0: -; VI-NEXT: s_dcache_wb_vol +; VI: s_dcache_wb_vol ; VI: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_wb_vol_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.wb.vol()