diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -1359,6 +1359,27 @@
       Idx = Idx.getRegSlot(true);
 
     SlotIndex Next = Idx.getNextSlot();
+    if (MO.isUse() && MO.isTied()) {
+      assert(Next.isRegister());
+      // We want to extend a live range into `e` slot rather than `r` slot if
+      // tied-def is early clobber, because the e slot will already contained
+      // in the live range of early-clobber tied-def operand, give an example
+      // here:
+      //  0  %0 = ...
+      // 16  early-clobber %0 = Op %0 (tied-def 0), ...
+      // 32  ... = Op %0
+      // Before extend:
+      //   %0 = [0r, 0d) [16e, 32d)
+      // The point we want to extend is 0d to 16e not 16r in this case, but if
+      // we use 16r here we will extend nothing because that already contained
+      // in [16e, 32d).
+      unsigned OpIdx = MI->findRegisterUseOperandIdx(MO.getReg());
+      unsigned DefOpIdx = MI->findTiedOperandIdx(OpIdx);
+      const MachineOperand &DefOp = MI->getOperand(DefOpIdx);
+      if (DefOp.isEarlyClobber())
+        Next = Idx;
+    }
+
     if (LI.hasSubRanges()) {
       // We have to delay extending subranges until we have seen all operands
       // defining the register. This is because a <def,read-undef> operand
diff --git a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
--- a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
+++ b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
@@ -55,14 +55,14 @@
 ; CHECK-NEXT:    addi a1, sp, 16
 ; CHECK-NEXT:    csrr a2, vlenb
 ; CHECK-NEXT:    slli a2, a2, 1
-; CHECK-NEXT:    vl2r.v v8, (a1) # Unknown-size Folded Reload
-; CHECK-NEXT:    add a1, a1, a2
 ; CHECK-NEXT:    vl2r.v v10, (a1) # Unknown-size Folded Reload
 ; CHECK-NEXT:    add a1, a1, a2
 ; CHECK-NEXT:    vl2r.v v12, (a1) # Unknown-size Folded Reload
 ; CHECK-NEXT:    add a1, a1, a2
 ; CHECK-NEXT:    vl2r.v v14, (a1) # Unknown-size Folded Reload
-; CHECK-NEXT:    vle16.v v14, (a0)
+; CHECK-NEXT:    add a1, a1, a2
+; CHECK-NEXT:    vl2r.v v16, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vsetivli zero, 2, e16, m2, ta, mu
 ; CHECK-NEXT:    lui a0, %hi(.L__const._Z3foov.var_40)
 ; CHECK-NEXT:    addi a0, a0, %lo(.L__const._Z3foov.var_40)
@@ -76,11 +76,11 @@
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    add a0, sp, a0
 ; CHECK-NEXT:    addi a0, a0, 16
-; CHECK-NEXT:    vl1r.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT:    vsext.vf2 v8, v16, v0.t
+; CHECK-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT:    vsext.vf2 v10, v8, v0.t
 ; CHECK-NEXT:    lui a0, %hi(var_47)
 ; CHECK-NEXT:    addi a0, a0, %lo(var_47)
-; CHECK-NEXT:    vsseg4e16.v v8, (a0)
+; CHECK-NEXT:    vsseg4e16.v v10, (a0)
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a1, a0, 3
 ; CHECK-NEXT:    add a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir
--- a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir
+++ b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir
@@ -216,7 +216,7 @@
     ; CHECK-NEXT:   rewr %bb.0	464B:0	early-clobber %28.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %28.sub_vrm2_0:vrn4m2nov0(tied-def 0), %5:vr, $v0, 2, 4, 0, implicit $vl, implicit $vtype
     ; CHECK-NEXT:   rewr %bb.0	512B:0	PseudoVSSEG4E16_V_M2 %28:vrn4m2nov0, %27:gpr, 2, 4, implicit $vl, implicit $vtype
     ; CHECK-NEXT:   rewr %bb.0	216B:1	undef %28.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0 = COPY %29.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0
-    ; CHECK-NEXT: queuing new interval: %28 [216r,288r:0)[288r,464e:1)[464e,512r:2) 0@216r 1@288r 2@464e  L000000000000000C [216r,216d:0)[464e,512r:1) 0@216r 1@464e  L0000000000000300 [288r,512r:0) 0@288r  L00000000000000C0 [216r,512r:0) 0@216r  L0000000000000030 [216r,512r:0) 0@216r  weight:8.706897e-03
+    ; CHECK-NEXT: queuing new interval: %28 [216r,288r:0)[288r,464e:1)[464e,512r:2) 0@216r 1@288r 2@464e L000000000000000C [216r,464e:0)[464e,512r:1) 0@216r 1@464e L0000000000000300 [288r,512r:0) 0@288r L00000000000000C0 [216r,512r:0) 0@216r L0000000000000030 [216r,512r:0) 0@216r weight:8.706897e-03
     %26:gpr = LUI target-flags(riscv-hi) @var_47
     %27:gpr = ADDI %26, target-flags(riscv-lo) @var_47
     PseudoVSSEG4E16_V_M2 %25, %27, 2, 4 /* e16 */, implicit $vl, implicit $vtype