diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -7736,7 +7736,8 @@
 }
 
 bool AMDGPUOperand::isSMEMOffset() const {
-  return isImm(); // Offset range is checked later by validator.
+  return isImmTy(ImmTyNone) ||
+         isImmTy(ImmTyOffset); // Offset range is checked later by validator.
 }
 
 bool AMDGPUOperand::isSMRDLiteralOffset() const {
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_smem.s b/llvm/test/MC/AMDGPU/gfx10_asm_smem.s
--- a/llvm/test/MC/AMDGPU/gfx10_asm_smem.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_smem.s
@@ -1342,3 +1342,9 @@
 
 s_buffer_atomic_xor s5, s[4:7], s2 dlc
 // GFX10: encoding: [0x42,0x41,0x28,0xf5,0x00,0x00,0x00,0x04]
+
+s_load_dword s1, s[2:3] glc
+// GFX10: s_load_dword s1, s[2:3], 0x0 glc ; encoding: [0x41,0x00,0x01,0xf4,0x00,0x00,0x00,0xfa]
+
+s_load_dword s1, s[2:3] dlc
+// GFX10: s_load_dword s1, s[2:3], 0x0 dlc ; encoding: [0x41,0x40,0x00,0xf4,0x00,0x00,0x00,0xfa]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_smem.s b/llvm/test/MC/AMDGPU/gfx8_asm_smem.s
--- a/llvm/test/MC/AMDGPU/gfx8_asm_smem.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_smem.s
@@ -1163,3 +1163,6 @@
 
 s_atc_probe_buffer 0x0, s[8:11], 0x7ffff
 // CHECK: [0x04,0x00,0x9e,0xc0,0xff,0xff,0x07,0x00]
+
+s_load_dword s1, s[2:3] glc
+// CHECK: s_load_dword s1, s[2:3], 0x0 glc ; encoding: [0x41,0x00,0x03,0xc0,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_smem.s b/llvm/test/MC/AMDGPU/gfx9_asm_smem.s
--- a/llvm/test/MC/AMDGPU/gfx9_asm_smem.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_smem.s
@@ -4475,3 +4475,6 @@
 
 s_atomic_dec_x2 s[10:11], s[2:3], s0 glc
 // CHECK: [0x81,0x02,0xb1,0xc2,0x00,0x00,0x00,0x00]
+
+s_load_dword s1, s[2:3] glc
+// CHECK: s_load_dword s1, s[2:3], 0x0 glc ; encoding: [0x41,0x00,0x03,0xc0,0x00,0x00,0x00,0x00]