Index: mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
===================================================================
--- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
+++ mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
@@ -585,20 +585,18 @@
       // Br is handled specially.
       // Switch is handled specially.
       // FIXME: indirectbr
-      // FIXME: invoke
-      INST(Resume, Resume),
-      // FIXME: unreachable
+      // Invoke is handled specially.
+      INST(Resume, Resume), INST(Unreachable, Unreachable),
       // FIXME: cleanupret
       // FIXME: catchret
       // FIXME: catchswitch
       // FIXME: callbr
-      // FIXME: fneg
-      INST(Add, Add), INST(FAdd, FAdd), INST(Sub, Sub), INST(FSub, FSub),
-      INST(Mul, Mul), INST(FMul, FMul), INST(UDiv, UDiv), INST(SDiv, SDiv),
-      INST(FDiv, FDiv), INST(URem, URem), INST(SRem, SRem), INST(FRem, FRem),
-      INST(Shl, Shl), INST(LShr, LShr), INST(AShr, AShr), INST(And, And),
-      INST(Or, Or), INST(Xor, XOr), INST(Alloca, Alloca), INST(Load, Load),
-      INST(Store, Store),
+      INST(FNeg, FNeg), INST(Add, Add), INST(FAdd, FAdd), INST(Sub, Sub),
+      INST(FSub, FSub), INST(Mul, Mul), INST(FMul, FMul), INST(UDiv, UDiv),
+      INST(SDiv, SDiv), INST(FDiv, FDiv), INST(URem, URem), INST(SRem, SRem),
+      INST(FRem, FRem), INST(Shl, Shl), INST(LShr, LShr), INST(AShr, AShr),
+      INST(And, And), INST(Or, Or), INST(Xor, XOr), INST(Alloca, Alloca),
+      INST(Load, Load), INST(Store, Store),
       // Getelementptr is handled specially.
       INST(Ret, Return), INST(Fence, Fence),
       // FIXME: atomiccmpxchg
@@ -613,8 +611,7 @@
       // ICmp is handled specially.
       // FCmp is handled specially.
       // PHI is handled specially.
-      INST(Freeze, Freeze), INST(Call, Call),
-      // FIXME: select
+      INST(Freeze, Freeze), INST(Call, Call), INST(Select, Select),
       // FIXME: vaarg
       INST(ExtractElement, ExtractElement), INST(InsertElement, InsertElement),
       // ShuffleVector is handled specially.
@@ -776,7 +773,10 @@
   case llvm::Instruction::Freeze:
   case llvm::Instruction::BitCast:
   case llvm::Instruction::ExtractElement:
-  case llvm::Instruction::InsertElement: {
+  case llvm::Instruction::InsertElement:
+  case llvm::Instruction::Select:
+  case llvm::Instruction::FNeg:
+  case llvm::Instruction::Unreachable: {
     OperationState state(loc, lookupOperationNameFromOpcode(inst->getOpcode()));
     SmallVector<Value, 4> ops;
     ops.reserve(inst->getNumOperands());
Index: mlir/test/Target/LLVMIR/Import/basic.ll
===================================================================
--- mlir/test/Target/LLVMIR/Import/basic.ll
+++ mlir/test/Target/LLVMIR/Import/basic.ll
@@ -278,6 +278,10 @@
   %10 = frem float %a, %b
   ; CHECK: %[[a13:[0-9]+]] = llvm.frem %arg2, %arg3 : f64
   %11 = frem double %c, %d
+  ; CHECK: %{{.+}} = llvm.fneg %{{.+}} : f32
+  %12 = fneg float %a
+  ; CHECK: %{{.+}} = llvm.fneg %{{.+}} : f64
+  %13 = fneg double %c
   ret void
 }
 
@@ -605,3 +609,18 @@
   ; CHECK: llvm.return %[[V1]]
   ret <4 x half> %r
 }
+
+; Select
+; CHECK-LABEL: llvm.func @select_inst
+define void @select_inst(i32 %arg0, i32 %arg1, i1 %pred) {
+  ; CHECK: %{{.+}} = llvm.select %{{.+}}, %{{.+}}, %{{.+}} : i1, i32
+  %1 = select i1 %pred, i32 %arg0, i32 %arg1
+  ret void
+}
+
+; Unreachable
+; CHECK-LABEL: llvm.func @unreachable_inst
+define void @unreachable_inst() {
+  ; CHECK: llvm.unreachable
+  unreachable
+}