[AMDGPU] Shrink F16 MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

if (Src2.isImm() && !TII->isInlineConstant(Src2)) {
     default:
       llvm_unreachable("Unexpected mad/fma opcode!");
     case AMDGPU::V_MAD_F32_e64:
       NewOpcode = AMDGPU::V_MADAK_F32;
       break;
     case AMDGPU::V_FMA_F32_e64:
       NewOpcode = AMDGPU::V_FMAAK_F32;
       break;
+    case AMDGPU::V_MAD_F16_e64:
+      NewOpcode = AMDGPU::V_MADAK_F16;
+      break;
+    case AMDGPU::V_FMA_F16_e64:
+      NewOpcode = AMDGPU::V_FMAAK_F16;
+      break;
     }
   }
 
   // Detect "Dst = VSrc * Imm + VGPR" and convert to MK form.
   if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) {
     if (Src1.isImm() && !TII->isInlineConstant(Src1))
       Swap = false;
     else if (Src0.isImm() && !TII->isInlineConstant(Src0))
       Swap = true;
     else
       return;
 
     switch (Opcode) {
     default:
       llvm_unreachable("Unexpected mad/fma opcode!");
     case AMDGPU::V_MAD_F32_e64:
       NewOpcode = AMDGPU::V_MADMK_F32;
       break;
     case AMDGPU::V_FMA_F32_e64:
       NewOpcode = AMDGPU::V_FMAMK_F32;
       break;
+    case AMDGPU::V_MAD_F16_e64:
+      NewOpcode = AMDGPU::V_MADMK_F16;
+      break;
+    case AMDGPU::V_FMA_F16_e64:
+      NewOpcode = AMDGPU::V_FMAMK_F16;
+      break;
     }
   }
 
   if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)
     return;
 
   if (Swap) {
     // Swap Src0 and Src1 by building a new instruction.
for (I = MBB.begin(); I != MBB.end(); I = Next) {
               MachineFunctionProperties::Property::NoVRegs)) {
         shrinkMIMG(MI);
         continue;
       }
 
       if (!TII->isVOP3(MI))
         continue;
 
-      // TODO: Also shrink F16 forms.
       if (MI.getOpcode() == AMDGPU::V_MAD_F32_e64 ||
-          MI.getOpcode() == AMDGPU::V_FMA_F32_e64) {
+          MI.getOpcode() == AMDGPU::V_FMA_F32_e64 ||
+          MI.getOpcode() == AMDGPU::V_MAD_F16_e64 ||
+          MI.getOpcode() == AMDGPU::V_FMA_F16_e64) {
         shrinkMadFma(MI);
         continue;
       }
 
       if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
         continue;
 
       if (!TII->canShrink(MI, *MRI)) {

llvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir

 
 ---
 name: mad_cvv_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: mad_cvv_f16
     ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GFX10-NEXT: [[V_MAD_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F16_e64 0, 18688, 0, [[DEF]], 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec
-    ; GFX10-NEXT: SI_RETURN implicit [[V_MAD_F16_e64_]]
+    ; GFX10-NEXT: [[V_MADMK_F16_:%[0-9]+]]:vgpr_32 = V_MADMK_F16 [[DEF]], 18688, [[DEF1]], implicit $mode, implicit $exec
+    ; GFX10-NEXT: SI_RETURN implicit [[V_MADMK_F16_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = V_MAD_F16_e64 0, 18688, 0, %0, 0, %1, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit %2
 ...
 
 ---
 name: mad_vcv_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: mad_vcv_f16
     ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GFX10-NEXT: [[V_MAD_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F16_e64 0, [[DEF]], 0, 18688, 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec
-    ; GFX10-NEXT: SI_RETURN implicit [[V_MAD_F16_e64_]]
+    ; GFX10-NEXT: [[V_MADMK_F16_:%[0-9]+]]:vgpr_32 = V_MADMK_F16 [[DEF]], 18688, [[DEF1]], implicit $mode, implicit $exec
+    ; GFX10-NEXT: SI_RETURN implicit [[V_MADMK_F16_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = V_MAD_F16_e64 0, %0, 0, 18688, 0, %1, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit %2
 ...
 
 ---
 name: mad_vvc_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: mad_vvc_f16
     ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GFX10-NEXT: [[V_MAD_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F16_e64 0, [[DEF]], 0, [[DEF1]], 0, 18688, 0, 0, implicit $mode, implicit $exec
-    ; GFX10-NEXT: SI_RETURN implicit [[V_MAD_F16_e64_]]
+    ; GFX10-NEXT: [[V_MADAK_F16_:%[0-9]+]]:vgpr_32 = V_MADAK_F16 [[DEF]], [[DEF1]], 18688, implicit $mode, implicit $exec
+    ; GFX10-NEXT: SI_RETURN implicit [[V_MADAK_F16_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = V_MAD_F16_e64 0, %0, 0, %1, 0, 18688, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit %2
 ...
 
 ---
 name: mad_vsc_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: mad_vsc_f16
     ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GFX10-NEXT: [[V_MAD_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F16_e64 0, [[DEF]], 0, [[DEF1]], 0, 18688, 0, 0, implicit $mode, implicit $exec
-    ; GFX10-NEXT: SI_RETURN implicit [[V_MAD_F16_e64_]]
+    ; GFX10-NEXT: [[V_MADAK_F16_:%[0-9]+]]:vgpr_32 = V_MADAK_F16 [[DEF1]], [[DEF]], 18688, implicit $mode, implicit $exec
+    ; GFX10-NEXT: SI_RETURN implicit [[V_MADAK_F16_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:sreg_32 = IMPLICIT_DEF
     %2:vgpr_32 = V_MAD_F16_e64 0, %0, 0, %1, 0, 18688, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit %2
 ...
 
 ---
 name: fma_cvv_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: fma_cvv_f16
     ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GFX10-NEXT: [[V_FMA_F16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_e64 0, 18688, 0, [[DEF]], 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec
-    ; GFX10-NEXT: SI_RETURN implicit [[V_FMA_F16_e64_]]
+    ; GFX10-NEXT: [[V_FMAMK_F16_:%[0-9]+]]:vgpr_32 = V_FMAMK_F16 [[DEF]], 18688, [[DEF1]], implicit $mode, implicit $exec
+    ; GFX10-NEXT: SI_RETURN implicit [[V_FMAMK_F16_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = V_FMA_F16_e64 0, 18688, 0, %0, 0, %1, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit %2
 ...
 
 ---
 name: fma_vcv_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: fma_vcv_f16
     ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GFX10-NEXT: [[V_FMA_F16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_e64 0, [[DEF]], 0, 18688, 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec
-    ; GFX10-NEXT: SI_RETURN implicit [[V_FMA_F16_e64_]]
+    ; GFX10-NEXT: [[V_FMAMK_F16_:%[0-9]+]]:vgpr_32 = V_FMAMK_F16 [[DEF]], 18688, [[DEF1]], implicit $mode, implicit $exec
+    ; GFX10-NEXT: SI_RETURN implicit [[V_FMAMK_F16_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = V_FMA_F16_e64 0, %0, 0, 18688, 0, %1, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit %2
 ...
 
 ---
 name: fma_vvc_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: fma_vvc_f16
     ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GFX10-NEXT: [[V_FMA_F16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_e64 0, [[DEF]], 0, [[DEF1]], 0, 18688, 0, 0, implicit $mode, implicit $exec
-    ; GFX10-NEXT: SI_RETURN implicit [[V_FMA_F16_e64_]]
+    ; GFX10-NEXT: [[V_FMAAK_F16_:%[0-9]+]]:vgpr_32 = V_FMAAK_F16 [[DEF]], [[DEF1]], 18688, implicit $mode, implicit $exec
+    ; GFX10-NEXT: SI_RETURN implicit [[V_FMAAK_F16_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = V_FMA_F16_e64 0, %0, 0, %1, 0, 18688, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit %2
 ...
 
 ---
 name: fma_vsc_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: fma_vsc_f16
     ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GFX10-NEXT: [[V_FMA_F16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_e64 0, [[DEF]], 0, [[DEF1]], 0, 18688, 0, 0, implicit $mode, implicit $exec
-    ; GFX10-NEXT: SI_RETURN implicit [[V_FMA_F16_e64_]]
+    ; GFX10-NEXT: [[V_FMAAK_F16_:%[0-9]+]]:vgpr_32 = V_FMAAK_F16 [[DEF1]], [[DEF]], 18688, implicit $mode, implicit $exec
+    ; GFX10-NEXT: SI_RETURN implicit [[V_FMAAK_F16_]]
     %0:vgpr_32 = IMPLICIT_DEF
     %1:sreg_32 = IMPLICIT_DEF
     %2:vgpr_32 = V_FMA_F16_e64 0, %0, 0, %1, 0, 18688, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit %2
 ...