Index: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4367,10 +4367,16 @@
   unsigned CPol = Inst.getOperand(CPolPos).getImm();
 
   uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
-  if ((TSFlags & (SIInstrFlags::SMRD)) &&
-      (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC))) {
-    Error(IDLoc, "invalid cache policy for SMRD instruction");
-    return false;
+  if (TSFlags & SIInstrFlags::SMRD) {
+    if (CPol && (isSI() || isCI())) {
+      SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
+      Error(S, "cache policy is not supported for SMRD instructions");
+      return false;
+    }
+    if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) {
+      Error(IDLoc, "invalid cache policy for SMEM instruction");
+      return false;
+    }
   }
 
   if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {
Index: llvm/lib/Target/AMDGPU/SMInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SMInstructions.td
+++ llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -491,8 +491,6 @@
   let Inst{31-27} = 0x18; //encoding
 }
 
-// FIXME: Assembler should reject trying to use glc on SMRD
-// instructions on SI.
 multiclass SM_Real_Loads_si<bits<5> op, string ps,
                             SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
                             SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
Index: llvm/test/MC/AMDGPU/cpol-err.s
===================================================================
--- llvm/test/MC/AMDGPU/cpol-err.s
+++ llvm/test/MC/AMDGPU/cpol-err.s
@@ -41,6 +41,6 @@
 // CHECK-NEXT:{{^}}                                            ^
 
 s_load_dword s1, s[2:3], 0xfc glc slc
-// CHECK: error: invalid cache policy for SMRD instruction
+// CHECK: error: invalid cache policy for SMEM instruction
 // CHECK-NEXT:{{^}}s_load_dword s1, s[2:3], 0xfc glc slc
 // CHECK-NEXT:{{^}}^
Index: llvm/test/MC/AMDGPU/gfx7_err_pos.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx7_err_pos.s
+++ llvm/test/MC/AMDGPU/gfx7_err_pos.s
@@ -1,5 +1,18 @@
 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
 
+//==============================================================================
+// cache policy is not supported for SMRD instructions
+
+s_load_dword s1, s[2:3], 0xfc glc slc
+// CHECK: error: cache policy is not supported for SMRD instructions
+// CHECK-NEXT:{{^}}s_load_dword s1, s[2:3], 0xfc glc slc
+// CHECK-NEXT:{{^}}                              ^
+
+s_load_dword s1, s[2:3], 0xfc slc
+// CHECK: error: cache policy is not supported for SMRD instructions
+// CHECK-NEXT:{{^}}s_load_dword s1, s[2:3], 0xfc slc
+// CHECK-NEXT:{{^}}                              ^
+
 //==============================================================================
 // d16 modifier is not supported on this GPU
 
Index: llvm/test/MC/AMDGPU/smem.s
===================================================================
--- llvm/test/MC/AMDGPU/smem.s
+++ llvm/test/MC/AMDGPU/smem.s
@@ -107,16 +107,15 @@
 // NOGFX9GFX1012: error: register not available on this GPU
 // NOGFX1030: error: instruction not supported on this GPU
 
-// FIXME: Should error on SI instead of silently ignoring glc
 s_load_dword s1, s[2:3], 0xfc glc
 // GFX89: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x03,0xc0,0xfc,0x00,0x00,0x00]
 // GFX10: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x01,0xf4,0xfc,0x00,0x00,0xfa]
-// SICI: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0xfc,0x83,0x00,0xc0
+// NOSICI: error: cache policy is not supported for SMRD instructions
 
 s_load_dword s1, s[2:3], s4 glc
 // GFX89: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xc0,0x04,0x00,0x00,0x00]
 // GFX10: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xf4,0x00,0x00,0x00,0x08]
-// SICI: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x04,0x82,0x00,0xc0]
+// NOSICI: error: cache policy is not supported for SMRD instructions
 
 s_buffer_store_dword s10, s[92:95], m0
 // GFX89: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xc0,0x7c,0x00,0x00,0x00]
@@ -221,11 +220,10 @@
 // SICI:  s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x7c,0x5c,0x78,0xc2]
 // GFX10: s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x2e,0x1b,0x24,0xf4,0x00,0x00,0x00,0xf8]
 
-// FIXME: Should error on SI instead of silently ignoring glc
 s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc
 // GFX89: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]
 // GFX10: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xf4,0x00,0x00,0x00,0xf8]
-// SICI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x7c,0x5c,0x84,0xc2]
+// NOSICI: error: cache policy is not supported for SMRD instructions
 
 //===----------------------------------------------------------------------===//
 // s_scratch instructions