diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -458,20 +458,14 @@ if (TII->isSALU(MI->getOpcode())) { const MCInstrDesc &InstDesc = MI->getDesc(); const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo]; - const SIRegisterInfo &SRI = TII->getRegisterInfo(); // Fine if the operand can be encoded as an inline constant - if (TII->isLiteralConstantLike(*OpToFold, OpInfo)) { - if (!SRI.opCanUseInlineConstant(OpInfo.OperandType) || - !TII->isInlineConstant(*OpToFold, OpInfo)) { - // Otherwise check for another constant - for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) { - auto &Op = MI->getOperand(i); - if (OpNo != i && - TII->isLiteralConstantLike(Op, OpInfo)) { - return false; - } - } + if (!TII->isInlineConstant(*OpToFold, OpInfo)) { + // Otherwise check for another constant + for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) { + auto &Op = MI->getOperand(i); + if (OpNo != i && !TII->isInlineConstant(Op, OpInfo)) + return false; } } } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -772,6 +772,13 @@ return isInlineConstant(Imm.bitcastToAPInt()); } + // Returns true if this operand definitely does not need to be encoded as a + // 32-bit literal. Note that this function handles all kinds of operands, not + // just immediates. + // + // Some operands like FrameIndexes could resolve to an inline immediate value + // that will not require an additional 4-bytes; this function assumes that it + // will. bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const; bool isInlineConstant(const MachineOperand &MO, @@ -822,23 +829,6 @@ return isInlineConstant(*Parent, Parent->getOperandNo(&MO)); } - bool isLiteralConstant(const MachineOperand &MO, - const MCOperandInfo &OpInfo) const { - return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType); - } - - bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const { - const MachineOperand &MO = MI.getOperand(OpIdx); - return MO.isImm() && !isInlineConstant(MI, OpIdx); - } - - // Returns true if this operand could potentially require a 32-bit literal - // operand, but not necessarily. A FrameIndex for example could resolve to an - // inline immediate value that will not require an additional 4-bytes; this - // assumes that it will. - bool isLiteralConstantLike(const MachineOperand &MO, - const MCOperandInfo &OpInfo) const; - bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1852,7 +1852,7 @@ assert(!SrcOp.isFPImm()); if (ST.hasMovB64()) { MI.setDesc(get(AMDGPU::V_MOV_B64_e32)); - if (!isLiteralConstant(MI, 1) || isUInt<32>(SrcOp.getImm())) + if (isInlineConstant(MI, 1) || isUInt<32>(SrcOp.getImm())) break; } if (SrcOp.isImm()) { @@ -3600,6 +3600,8 @@ bool SIInstrInfo::isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const { + if (MO.isReg()) + return true; if (!MO.isImm() || OperandType < AMDGPU::OPERAND_SRC_FIRST || OperandType > AMDGPU::OPERAND_SRC_LAST) @@ -3682,24 +3684,6 @@ } } -bool SIInstrInfo::isLiteralConstantLike(const MachineOperand &MO, - const MCOperandInfo &OpInfo) const { - switch (MO.getType()) { - case MachineOperand::MO_Register: - return false; - case MachineOperand::MO_Immediate: - return !isInlineConstant(MO, OpInfo); - case MachineOperand::MO_FrameIndex: - case MachineOperand::MO_MachineBasicBlock: - case MachineOperand::MO_ExternalSymbol: - case MachineOperand::MO_GlobalAddress: - case MachineOperand::MO_MCSymbol: - return true; - default: - llvm_unreachable("unexpected operand type"); - } -} - static bool compareMachineOp(const MachineOperand &Op0, const MachineOperand &Op1) { if (Op0.getType() != Op1.getType()) @@ -3895,13 +3879,8 @@ const MachineOperand &MO, const MCOperandInfo &OpInfo) const { // Literal constants use the constant bus. - //if (isLiteralConstantLike(MO, OpInfo)) - // return true; - if (MO.isImm()) - return !isInlineConstant(MO, OpInfo); - if (!MO.isReg()) - return true; // Misc other operands like FrameIndex + return !isInlineConstant(MO, OpInfo); if (!MO.isUse()) return false; @@ -4364,11 +4343,9 @@ const MachineOperand &Src1 = MI.getOperand(Src1Idx); unsigned Immediates = 0; - if (!Src0.isReg() && - !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType)) + if (!isInlineConstant(Src0, Desc.OpInfo[Src0Idx])) Immediates++; - if (!Src1.isReg() && - !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType)) + if (!isInlineConstant(Src1, Desc.OpInfo[Src1Idx])) Immediates++; if (Immediates > 1) { @@ -4964,7 +4941,7 @@ int ConstantBusLimit = ST.getConstantBusLimit(MI.getOpcode()); int VOP3LiteralLimit = ST.hasVOP3Literal() ? 1 : 0; if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) { - if (isVOP3(MI) && isLiteralConstantLike(*MO, OpInfo) && !VOP3LiteralLimit--) + if (isVOP3(MI) && !isInlineConstant(*MO, OpInfo) && !VOP3LiteralLimit--) return false; SmallDenseSet SGPRsUsed; @@ -4987,7 +4964,7 @@ if (--ConstantBusLimit <= 0) return false; } else if (isVOP3(MI) && AMDGPU::isSISrcOperand(InstDesc, i) && - isLiteralConstantLike(Op, InstDesc.OpInfo[i])) { + !isInlineConstant(Op, InstDesc.OpInfo[i])) { if (!VOP3LiteralLimit--) return false; if (--ConstantBusLimit <= 0) @@ -5062,9 +5039,9 @@ // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32 // we need to only have one constant bus use before GFX10. bool HasImplicitSGPR = findImplicitSGPRRead(MI) != AMDGPU::NoRegister; - if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 && - Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) || - isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx]))) + if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 && Src0.isReg() && + (RI.isSGPRReg(MRI, Src0.getReg()) || + !isInlineConstant(Src0, InstrDesc.OpInfo[Src0Idx]))) legalizeOpWithMove(MI, Src0Idx); // Special case: V_WRITELANE_B32 accepts only immediate or SGPR operands for @@ -5206,7 +5183,7 @@ MachineOperand &MO = MI.getOperand(Idx); if (!MO.isReg()) { - if (!isLiteralConstantLike(MO, get(Opc).OpInfo[Idx])) + if (isInlineConstant(MO, get(Opc).OpInfo[Idx])) continue; if (LiteralLimit > 0 && ConstantBusLimit > 0) { @@ -7456,7 +7433,7 @@ for (int I = 0, E = MI.getNumExplicitOperands(); I != E; ++I) { const MachineOperand &Op = MI.getOperand(I); const MCOperandInfo &OpInfo = Desc.OpInfo[I]; - if (isLiteralConstantLike(Op, OpInfo)) { + if (!isInlineConstant(Op, OpInfo)) { HasLiteral = true; break; }