diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -445,6 +445,14 @@ return cst_pred_ty(); } +struct is_shifted_mask { + bool isValue(const APInt &C) { return C.isShiftedMask(); } +}; + +inline cst_pred_ty m_ShiftedMask() { + return cst_pred_ty(); +} + struct is_all_ones { bool isValue(const APInt &C) { return C.isAllOnes(); } }; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -481,6 +481,100 @@ return ConstantInt::get(LHS->getType(), !IsAnd); } +/// Try to fold (icmp(A & B) == 0) & (icmp(A & D) != E) into (icmp A u< D) iff +/// B is a contiguous set of ones starting from the most significant bit +/// (negative power of 2), D and E are equal, and D is a contiguous set of ones +/// starting at the most significant zero bit in B. +static Value *foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous( + bool IsAnd, Value *A, Value *B, Value *D, Value *E, + ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, + InstCombiner::BuilderTy &Builder) { + assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) && + "Expected equality predicates for masked type of icmps."); + if (!IsAnd || PredL != ICmpInst::ICMP_EQ || PredR != ICmpInst::ICMP_NE) + return nullptr; + + if (!match(B, m_NegatedPower2()) || !match(D, m_ShiftedMask()) || + !match(E, m_ShiftedMask())) + return nullptr; + + // Test scalar arguments for conversion. B has been validated earlier to be a + // negative power of two and thus is guaranteed to have one or more contiguous + // ones starting from the MSB followed by zero or more contiguous zeros. D has + // been validated earlier to be a shifted set of one or more contiguous ones. + // In order to match, B leading ones and D leading zeros should be equal. The + // predicate that B be a negative power of 2 prevents the condition of there + // ever being zero leading ones. Thus 0 == 0 cannot occur. The predicate that + // D always be a shifted mask prevents the condition of D equaling 0. This + // prevents matching the condition where B contains the maximum number of + // leading one bits (-1) and D contains the maximum number of leading zero + // bits (0). + auto isReducible = [](const Value *B, const Value *D, const Value *E) { + const APInt *BCst, *DCst, *ECst; + return match(B, m_APIntAllowUndef(BCst)) && match(D, m_APInt(DCst)) && + match(E, m_APInt(ECst)) && *DCst == *ECst && + (isa(B) || + (BCst->countLeadingOnes() == DCst->countLeadingZeros())); + }; + + if (isReducible(B, D, E)) + return Builder.CreateICmp(ICmpInst::ICMP_ULT, A, D); + + // Test vector type arguments for conversion. + if (const auto *BVTy = dyn_cast(B->getType())) { + const auto *BFVTy = dyn_cast(BVTy); + const auto *BConst = dyn_cast(B); + const auto *DConst = dyn_cast(D); + const auto *EConst = dyn_cast(E); + + if (!BFVTy || !BConst || !DConst || !EConst) + return nullptr; + + const auto NumElts = BFVTy->getNumElements(); + + for (unsigned i = 0; i != NumElts; ++i) { + const auto *BElt = BConst->getAggregateElement(i); + const auto *DElt = DConst->getAggregateElement(i); + const auto *EElt = EConst->getAggregateElement(i); + + if (!BElt || !DElt || !EElt) + return nullptr; + + // Similar to scalar argument test with the addition of skipping + // undef/poison values in scalars of B as masking is supported. + if (!isReducible(BElt, DElt, EElt)) + return nullptr; + } + return Builder.CreateICmp(ICmpInst::ICMP_ULT, A, D); + } + return nullptr; +} + +/// Try to fold (icmp(A & B) == C) & (icmp(A & D) != E) or (icmp(A & D) != E) & +/// (icmp(A & B) == C) into (icmp A u< D). Where C is zero and the BMask +/// is not equal to either a mixed or all ones value. +static Value *foldLogOpOfMaskedICmpsAsymmetricOrOther( + bool IsAnd, Value *A, Value *B, Value *C, Value *D, Value *E, + ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, unsigned LHSMask, + unsigned RHSMask, InstCombiner::BuilderTy &Builder) { + assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) && + "Expected equality predicates for masked type of icmps."); + + const auto compareBMask = BMask_NotMixed | BMask_NotAllOnes; + if ((LHSMask & Mask_AllZeros) && (RHSMask == compareBMask)) { + if (Value *V = foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous( + IsAnd, A, B, D, E, PredL, PredR, Builder)) { + return V; + } + } else if ((LHSMask == compareBMask) && (RHSMask & Mask_AllZeros)) { + if (Value *V = foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous( + IsAnd, A, D, B, C, PredR, PredL, Builder)) { + return V; + } + } + return nullptr; +} + /// Try to fold (icmp(A & B) ==/!= 0) &/| (icmp(A & D) ==/!= E) into a single /// (icmp(A & X) ==/!= Y), where the left-hand side and the right hand side /// aren't of the common mask pattern type. @@ -502,14 +596,12 @@ } if ((LHSMask & Mask_NotAllZeros) && (RHSMask & BMask_Mixed)) { if (Value *V = foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed( - LHS, RHS, IsAnd, A, B, C, D, E, - PredL, PredR, Builder)) { + LHS, RHS, IsAnd, A, B, C, D, E, PredL, PredR, Builder)) { return V; } } else if ((LHSMask & BMask_Mixed) && (RHSMask & Mask_NotAllZeros)) { if (Value *V = foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed( - RHS, LHS, IsAnd, A, D, E, B, C, - PredR, PredL, Builder)) { + RHS, LHS, IsAnd, A, D, E, B, C, PredR, PredL, Builder)) { return V; } } @@ -517,7 +609,7 @@ } /// Try to fold (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E) -/// into a single (icmp(A & X) ==/!= Y). +/// into a single (icmp(A & X) ==/!= Y) or (icmp A u< Y). static Value *foldLogOpOfMaskedICmps(ICmpInst *LHS, ICmpInst *RHS, bool IsAnd, bool IsLogical, InstCombiner::BuilderTy &Builder) { @@ -539,6 +631,9 @@ LHS, RHS, IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask, Builder)) return V; + if (Value *V = foldLogOpOfMaskedICmpsAsymmetricOrOther( + IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask, Builder)) + return V; return nullptr; } @@ -592,6 +687,9 @@ Value *NewAnd2 = Builder.CreateAnd(A, NewAnd1); return Builder.CreateICmp(NewCC, NewAnd2, A); } + if (Value *V = foldLogOpOfMaskedICmpsAsymmetricOrOther( + IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask, Builder)) + return V; // Remaining cases assume at least that B and D are constant, and depend on // their actual values. This isn't strictly necessary, just a "handle the diff --git a/llvm/test/Transforms/InstCombine/icmp-logical.ll b/llvm/test/Transforms/InstCombine/icmp-logical.ll --- a/llvm/test/Transforms/InstCombine/icmp-logical.ll +++ b/llvm/test/Transforms/InstCombine/icmp-logical.ll @@ -1914,10 +1914,7 @@ ; ((X u< 0x8000000) & ((X & 0x60000000) != 0x60000000)) -> X u< 0x60000000 define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_1610612736(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_1610612736( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1610612736 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1610612736 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1610612736 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 2147483648 @@ -1929,10 +1926,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_1610612736(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_1610612736( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1610612736 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1610612736 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1610612736 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 2147483648 @@ -1945,10 +1939,7 @@ ; ((X u< 0x8000000) & ((X & 0x7FFFFFFF) != 0x7FFFFFFF)) -> X u< 0x7FFFFFFF define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_2147483647(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 2147483647 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 2147483647 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 2147483647 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 2147483648 @@ -1960,10 +1951,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_2147483647(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 2147483647 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 2147483647 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 2147483647 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 2147483648 @@ -1976,10 +1964,7 @@ ; ((X u< 0x4000000) & ((X & 0x30000000) != 0x30000000)) -> X u< 0x30000000 define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_805306368(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_805306368( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 805306368 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 805306368 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 805306368 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 1073741824 @@ -1991,10 +1976,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_805306368(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_805306368( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 805306368 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 805306368 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 805306368 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 1073741824 @@ -2007,10 +1989,7 @@ ; ((X u< 0x40000000) & ((X & 0x3FFFFFFF) != 0x3FFFFFFF)) -> X u< 0x3FFFFFFF define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_1073741824_1073741823(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_1073741824_1073741823( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1073741823 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1073741823 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1073741823 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 1073741824 @@ -2022,10 +2001,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_1073741824_1073741823(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_1073741824_1073741823( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1073741823 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1073741823 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1073741823 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 1073741824 @@ -2038,10 +2014,7 @@ ; ((X u< 8) & ((X & 7) != 7)) -> X u< 7 define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_7(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_7( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 7 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 7 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 7 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 8 @@ -2053,10 +2026,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_7(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_7( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 7 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 7 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 7 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 8 @@ -2069,10 +2039,7 @@ ; ((X u< 8) & ((X & 6) != 6)) -> X u< 6 define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_6(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_6( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 6 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 6 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 6 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 8 @@ -2084,10 +2051,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_6(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_6( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 6 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 6 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 6 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 8 @@ -2317,10 +2281,7 @@ ; Vector of 1 reduction define <1 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_2147483647(<1 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <1 x i32> [[X:%.*]], ; CHECK-NEXT: ret <1 x i1> [[T4]] ; %t1 = icmp ult <1 x i32> %x, @@ -2332,10 +2293,7 @@ define <1 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_2147483647(<1 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <1 x i32> [[X:%.*]], ; CHECK-NEXT: ret <1 x i1> [[T4]] ; %t1 = icmp ult <1 x i32> %x, @@ -2348,10 +2306,7 @@ ; Vector of 2 reduction define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_1610612736_2147483647(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_1610612736_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, @@ -2363,10 +2318,7 @@ define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_1610612736_2147483647(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_1610612736_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, @@ -2379,10 +2331,7 @@ ; Vector of 2 reduction with splat containing poison define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_splat_poison_2147483648_1610612736_2147483647(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_splat_poison_2147483648_1610612736_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, @@ -2394,10 +2343,7 @@ define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_splat_poison_2147483648_1610612736_2147483647(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_splat_poison_2147483648_1610612736_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, @@ -2410,10 +2356,7 @@ ; Vector of 2 reduction with splat containing undef define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_splat_undef_2147483648_1610612736_2147483647(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_splat_undef_2147483648_1610612736_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, @@ -2425,10 +2368,7 @@ define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_splat_undef_2147483648_1610612736_2147483647(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_splat_undef_2147483648_1610612736_2147483647( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, @@ -2441,10 +2381,7 @@ ; Vector of 7 reduction define <7 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_128_others(<7 x i8> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_128_others( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <7 x i8> [[X:%.*]], ; CHECK-NEXT: ret <7 x i1> [[T4]] ; %t1 = icmp ult <7 x i8> %x, @@ -2456,10 +2393,7 @@ define <7 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_128_others(<7 x i8> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_128_others( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <7 x i8> [[X:%.*]], ; CHECK-NEXT: ret <7 x i1> [[T4]] ; %t1 = icmp ult <7 x i8> %x, @@ -2472,10 +2406,7 @@ ; Vector of 6 reduction define <6 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_64_others(<6 x i8> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_64_others( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <6 x i8> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <6 x i8> [[X:%.*]], ; CHECK-NEXT: ret <6 x i1> [[T4]] ; %t1 = icmp ult <6 x i8> %x, @@ -2487,10 +2418,7 @@ define <6 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_64_others(<6 x i8> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_64_others( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <6 x i8> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <6 x i8> [[X:%.*]], ; CHECK-NEXT: ret <6 x i1> [[T4]] ; %t1 = icmp ult <6 x i8> %x,