diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -445,6 +445,14 @@ return cst_pred_ty(); } +struct is_shifted_mask { + bool isValue(const APInt &C) { return C.isShiftedMask(); } +}; + +inline cst_pred_ty m_ShiftedMask() { + return cst_pred_ty(); +} + struct is_all_ones { bool isValue(const APInt &C) { return C.isAllOnes(); } }; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -481,6 +481,86 @@ return ConstantInt::get(LHS->getType(), !IsAnd); } +/// Try to fold (icmp(A & B) != 0) & (icmp(A & D) == E), where B is a contiguous +/// set of ones starting from the most significant bit (negative power of 2), D +/// and E are equal, and D is a contiguous set of ones starting at the most +/// significant zero bit in B. +static Value *foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous( + bool IsAnd, Value *A, Value *B, Value *C, Value *D, Value *E, + ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, + InstCombiner::BuilderTy &Builder) { + assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) && + "Expected equality predicates for masked type of icmps."); + if (!IsAnd || PredL != ICmpInst::ICMP_EQ || PredR != ICmpInst::ICMP_NE) + return nullptr; + + if (!match(B, m_NegatedPower2()) || !match(D, m_ShiftedMask()) || + !match(E, m_ShiftedMask())) + return nullptr; + + const APInt *BCst, *DCst, *ECst; + if (match(B, m_APInt(BCst)) && match(D, m_APInt(DCst)) && + match(E, m_APInt(ECst)) && *DCst == *ECst && + (BCst->countLeadingOnes() - DCst->countLeadingZeros() == 0u)) { + return Builder.CreateICmp(ICmpInst::ICMP_ULT, A, D); + } + + if (const auto *BVTy = dyn_cast(B->getType())) { + const auto *BFVTy = dyn_cast(BVTy); + const auto *BConst = dyn_cast(B); + const auto *DConst = dyn_cast(D); + const auto *EConst = dyn_cast(E); + + if (!BFVTy || !BConst || !DConst || !EConst) + return nullptr; + + const auto NumElts = BFVTy->getNumElements(); + + for (unsigned i = 0; i != NumElts; ++i) { + const auto *BElt = BConst->getAggregateElement(i); + const auto *DElt = DConst->getAggregateElement(i); + const auto *EElt = EConst->getAggregateElement(i); + + if (!BElt || !DElt || !EElt) + return nullptr; + + if (match(BElt, m_APIntAllowUndef(BCst)) && match(DElt, m_APInt(DCst)) && + match(EElt, m_APInt(ECst)) && *DCst == *ECst && + (isa(BElt) || + (BCst->countLeadingOnes() - DCst->countLeadingZeros() == 0u))) { + continue; + } + return nullptr; + } + return Builder.CreateICmp(ICmpInst::ICMP_ULT, A, D); + } + return nullptr; +} + +/// Try to fold (icmp(A & B) != C) & (icmp(A & D) == E) where C is zero and the +/// BMask is not equal to either a mixed or all ones value. +static Value *foldLogOpOfMaskedICmpsAsymmetricOrOther( + bool IsAnd, Value *A, Value *B, Value *C, Value *D, Value *E, + ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, unsigned LHSMask, + unsigned RHSMask, InstCombiner::BuilderTy &Builder) { + assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) && + "Expected equality predicates for masked type of icmps."); + + const auto compareBMask = BMask_NotMixed | BMask_NotAllOnes; + if ((LHSMask & Mask_AllZeros) && (RHSMask == compareBMask)) { + if (Value *V = foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous( + IsAnd, A, B, C, D, E, PredL, PredR, Builder)) { + return V; + } + } else if ((LHSMask == compareBMask) && (RHSMask & Mask_AllZeros)) { + if (Value *V = foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous( + IsAnd, A, D, E, B, C, PredR, PredL, Builder)) { + return V; + } + } + return nullptr; +} + /// Try to fold (icmp(A & B) ==/!= 0) &/| (icmp(A & D) ==/!= E) into a single /// (icmp(A & X) ==/!= Y), where the left-hand side and the right hand side /// aren't of the common mask pattern type. @@ -517,7 +597,7 @@ } /// Try to fold (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E) -/// into a single (icmp(A & X) ==/!= Y). +/// into a single (icmp(A & X) ==/!= Y) or (icmp A u< Y). static Value *foldLogOpOfMaskedICmps(ICmpInst *LHS, ICmpInst *RHS, bool IsAnd, bool IsLogical, InstCombiner::BuilderTy &Builder) { @@ -532,6 +612,7 @@ unsigned LHSMask = MaskPair->first; unsigned RHSMask = MaskPair->second; unsigned Mask = LHSMask & RHSMask; + if (Mask == 0) { // Even if the two sides don't share a common pattern, check if folding can // still happen. @@ -539,6 +620,9 @@ LHS, RHS, IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask, Builder)) return V; + if (Value *V = foldLogOpOfMaskedICmpsAsymmetricOrOther( + IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask, Builder)) + return V; return nullptr; } @@ -592,6 +676,9 @@ Value *NewAnd2 = Builder.CreateAnd(A, NewAnd1); return Builder.CreateICmp(NewCC, NewAnd2, A); } + if (Value *V = foldLogOpOfMaskedICmpsAsymmetricOrOther( + IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask, Builder)) + return V; // Remaining cases assume at least that B and D are constant, and depend on // their actual values. This isn't strictly necessary, just a "handle the diff --git a/llvm/test/Transforms/InstCombine/icmp-logical.ll b/llvm/test/Transforms/InstCombine/icmp-logical.ll --- a/llvm/test/Transforms/InstCombine/icmp-logical.ll +++ b/llvm/test/Transforms/InstCombine/icmp-logical.ll @@ -1774,10 +1774,7 @@ ; ((X u< 0x8000000) & ((X & 0x60000000) != 0x60000000)) -> X u< 0x60000000 define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_1(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_1( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1610612736 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1610612736 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1610612736 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 2147483648 @@ -1789,10 +1786,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_1(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_1( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1610612736 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1610612736 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1610612736 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 2147483648 @@ -1805,10 +1799,7 @@ ; ((X u< 0x8000000) & ((X & 0x7FFFFFFF) != 0x7FFFFFFF)) -> X u< 0x7FFFFFFF define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 2147483647 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 2147483647 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 2147483647 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 2147483648 @@ -1820,10 +1811,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 2147483647 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 2147483647 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 2147483647 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 2147483648 @@ -1836,10 +1824,7 @@ ; ((X u< 0x4000000) & ((X & 0x30000000) != 0x30000000)) -> X u< 0x30000000 define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_3(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_3( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 805306368 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 805306368 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 805306368 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 1073741824 @@ -1851,10 +1836,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_3(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_3( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 805306368 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 805306368 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 805306368 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 1073741824 @@ -1867,10 +1849,7 @@ ; ((X u< 0x40000000) & ((X & 0x3FFFFFFF) != 0x3FFFFFFF)) -> X u< 0x3FFFFFFF define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_4(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_4( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1073741823 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1073741823 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1073741823 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 1073741824 @@ -1882,10 +1861,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_4(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_4( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1073741823 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1073741823 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1073741823 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 1073741824 @@ -1898,10 +1874,7 @@ ; ((X u< 8) & ((X & 7) != 7)) -> X u< 7 define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_5(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_5( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 7 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 7 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 7 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 8 @@ -1913,10 +1886,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_5(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_5( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 7 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 7 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 7 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 8 @@ -1929,10 +1899,7 @@ ; ((X u< 8) & ((X & 6) != 6)) -> X u< 6 define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_6(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_6( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 6 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 6 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 6 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 8 @@ -1944,10 +1911,7 @@ define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_6(i32 %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_6( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8 -; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 6 -; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 6 -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 6 ; CHECK-NEXT: ret i1 [[T4]] ; %t1 = icmp ult i32 %x, 8 @@ -2177,10 +2141,7 @@ ; Vector of 1 reduction define <1 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_14(<1 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_14( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <1 x i32> [[X:%.*]], ; CHECK-NEXT: ret <1 x i1> [[T4]] ; %t1 = icmp ult <1 x i32> %x, @@ -2192,10 +2153,7 @@ define <1 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_14(<1 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_14( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <1 x i32> [[X:%.*]], ; CHECK-NEXT: ret <1 x i1> [[T4]] ; %t1 = icmp ult <1 x i32> %x, @@ -2208,10 +2166,7 @@ ; Vector of 2 reduction define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_15(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_15( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, @@ -2223,10 +2178,7 @@ define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_15(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_15( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, @@ -2239,10 +2191,7 @@ ; Vector of 2 reduction with splat containing poison define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_16(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_16( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, @@ -2255,10 +2204,7 @@ ; Vector of 7 reduction define <7 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_17(<7 x i8> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_17( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <7 x i8> [[X:%.*]], ; CHECK-NEXT: ret <7 x i1> [[T4]] ; %t1 = icmp ult <7 x i8> %x, @@ -2270,10 +2216,7 @@ define <7 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_17(<7 x i8> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_17( -; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T3]], [[T1]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <7 x i8> [[X:%.*]], ; CHECK-NEXT: ret <7 x i1> [[T4]] ; %t1 = icmp ult <7 x i8> %x, @@ -2286,10 +2229,7 @@ ; Vector of 6 reduction define <6 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_18(<6 x i8> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_18( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <6 x i8> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <6 x i8> [[X:%.*]], ; CHECK-NEXT: ret <6 x i1> [[T4]] ; %t1 = icmp ult <6 x i8> %x, @@ -2301,10 +2241,7 @@ define <6 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_18(<6 x i8> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_18( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <6 x i8> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], -; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]] +; CHECK-NEXT: [[T4:%.*]] = icmp ult <6 x i8> [[X:%.*]], ; CHECK-NEXT: ret <6 x i1> [[T4]] ; %t1 = icmp ult <6 x i8> %x, @@ -2349,14 +2286,14 @@ define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_20(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_20( ; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], +; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], +; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], ; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]] ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, - %t2 = and <2 x i32> %x, - %t3 = icmp ne <2 x i32> %t2, + %t2 = and <2 x i32> %x, + %t3 = icmp ne <2 x i32> %t2, %t4 = and <2 x i1> %t1, %t3 ret <2 x i1> %t4 } @@ -2364,14 +2301,14 @@ define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_20(<2 x i32> %x) { ; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_20( ; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], -; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], +; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], +; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], ; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]] ; CHECK-NEXT: ret <2 x i1> [[T4]] ; %t1 = icmp ult <2 x i32> %x, - %t2 = and <2 x i32> %x, - %t3 = icmp ne <2 x i32> %t2, + %t2 = and <2 x i32> %x, + %t3 = icmp ne <2 x i32> %t2, %t4 = and <2 x i1> %t3, %t1 ret <2 x i1> %t4 }