diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp
--- a/bolt/lib/Core/BinaryFunction.cpp
+++ b/bolt/lib/Core/BinaryFunction.cpp
@@ -688,6 +688,7 @@
   assert((Opcode == dwarf::DW_CFA_expression ||
           Opcode == dwarf::DW_CFA_val_expression) &&
          "invalid DWARF expression CFI");
+  (void)Opcode;
   const uint8_t *const Start =
       reinterpret_cast<const uint8_t *>(ExprBytes.drop_front(1).data());
   const uint8_t *const End =
@@ -1097,7 +1098,6 @@
   auto handleExternalReference = [&](MCInst &Instruction, uint64_t Size,
                                      uint64_t Offset, uint64_t TargetAddress,
                                      bool &IsCall) -> MCSymbol * {
-    const bool IsCondBranch = MIB->isConditionalBranch(Instruction);
     const uint64_t AbsoluteInstrAddr = getAddress() + Offset;
     MCSymbol *TargetSymbol = nullptr;
     InterproceduralReferences.insert(TargetAddress);
@@ -1115,7 +1115,8 @@
     // treated as calls.
     if (!IsCall) {
       if (!MIB->convertJmpToTailCall(Instruction)) {
-        assert(IsCondBranch && "unknown tail call instruction");
+        assert(MIB->isConditionalBranch(Instruction) &&
+               "unknown tail call instruction");
         if (opts::Verbosity >= 2) {
           errs() << "BOLT-WARNING: conditional tail call detected in "
                  << "function " << *this << " at 0x"
diff --git a/bolt/lib/Core/DebugData.cpp b/bolt/lib/Core/DebugData.cpp
--- a/bolt/lib/Core/DebugData.cpp
+++ b/bolt/lib/Core/DebugData.cpp
@@ -598,6 +598,7 @@
 
     assert(Patch.Index == DebugLoclistWriter::InvalidIndex ||
            Patch.Index == Index++ && "Gap in LocList Index Array.");
+    (void)Index;
 
     std::vector<uint64_t> OffsetsArray;
     for (const DebugLocationEntry &Entry : Patch.LocList) {
diff --git a/bolt/lib/Passes/RegReAssign.cpp b/bolt/lib/Passes/RegReAssign.cpp
--- a/bolt/lib/Passes/RegReAssign.cpp
+++ b/bolt/lib/Passes/RegReAssign.cpp
@@ -349,6 +349,7 @@
 
   LLVM_DEBUG(dbgs() << "\n ** Swapping " << BC.MRI->getName(RBX) << " with "
                     << BC.MRI->getName(Candidate) << "\n\n");
+  (void)BC;
   swap(Function, RBX, Candidate);
   FuncsChanged.insert(&Function);
   return true;
diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -763,6 +763,7 @@
     assert(Adrp->getOperand(1).isImm() && "Unexpected adrp operand");
     bool Ret = evaluateMemOperandTarget(*Adrp, Base, AdrpPC, InstSize);
     assert(Ret && "Failed to evaluate adrp");
+    (void)Ret;
 
     return Base + Offset;
   }
diff --git a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
--- a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -1744,9 +1744,8 @@
 
   bool convertCallToIndirectCall(MCInst &Inst, const MCSymbol *TargetLocation,
                                  MCContext *Ctx) override {
-    bool IsTailCall = isTailCall(Inst);
     assert((Inst.getOpcode() == X86::CALL64pcrel32 ||
-            (Inst.getOpcode() == X86::JMP_4 && IsTailCall)) &&
+            (Inst.getOpcode() == X86::JMP_4 && isTailCall(Inst))) &&
            "64-bit direct (tail) call instruction expected");
     const auto NewOpcode =
         (Inst.getOpcode() == X86::CALL64pcrel32) ? X86::CALL64m : X86::JMP32m;