diff --git a/llvm/test/CodeGen/SPIRV/TruncToBool.ll b/llvm/test/CodeGen/SPIRV/TruncToBool.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/TruncToBool.ll
@@ -0,0 +1,15 @@
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+
+; CHECK-SPIRV:      OpBitwiseAnd
+; CHECK-SPIRV-NEXT: OpINotEqual
+
+; Function Attrs: nounwind
+define spir_kernel void @test(i32 %op1, i32 %op2, i8 %op3) {
+entry:
+  %0 = trunc i8 %op3 to i1
+  %call = call spir_func i32 @_Z14__spirv_Selectbii(i1 zeroext %0, i32 %op1, i32 %op2)
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare spir_func i32 @_Z14__spirv_Selectbii(i1 zeroext, i32, i32)
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll
@@ -0,0 +1,46 @@
+; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s
+
+; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]]
+; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]]
+; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]]
+; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]]
+; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]]
+
+@g1 = addrspace(1) global i8 undef, align 4
+@g2 = addrspace(1) global i16 undef, align 4
+@g3 = addrspace(1) global i32 undef, align 4
+@g4 = addrspace(1) global i64 undef, align 8
+@g5 = addrspace(1) global <2 x i32> undef, align 4
+
+
+; Function Attrs: norecurse nounwind readnone
+define dso_local spir_kernel void @test(i8 %x8, i16 %x16, i32 %x32, i64 %x64, <2 x i32> %x2i32) local_unnamed_addr {
+entry:
+  %0 = tail call i8 @llvm.ctpop.i8(i8 %x8)
+  store i8 %0, i8 addrspace(1)* @g1, align 4
+  %1 = tail call i16 @llvm.ctpop.i16(i16 %x16)
+  store i16 %1, i16 addrspace(1)* @g2, align 4
+  %2 = tail call i32 @llvm.ctpop.i32(i32 %x32)
+  store i32 %2, i32 addrspace(1)* @g3, align 4
+  %3 = tail call i64 @llvm.ctpop.i64(i64 %x64)
+  store i64 %3, i64 addrspace(1)* @g4, align 8
+  %4 = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %x2i32)
+  store <2 x i32> %4, <2 x i32> addrspace(1)* @g5, align 4
+
+  ret void
+}
+
+; Function Attrs: inaccessiblememonly nounwind willreturn
+declare i8 @llvm.ctpop.i8(i8)
+
+; Function Attrs: inaccessiblememonly nounwind willreturn
+declare i16 @llvm.ctpop.i16(i16)
+
+; Function Attrs: inaccessiblememonly nounwind willreturn
+declare i32 @llvm.ctpop.i32(i32)
+
+; Function Attrs: inaccessiblememonly nounwind willreturn
+declare i64 @llvm.ctpop.i64(i64)
+
+; Function Attrs: inaccessiblememonly nounwind willreturn
+declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>)
diff --git a/llvm/test/CodeGen/SPIRV/optnone.ll b/llvm/test/CodeGen/SPIRV/optnone.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/optnone.ll
@@ -0,0 +1,14 @@
+;; Check that optnone is correctly ignored when extension is not enabled
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+
+;; Per SPIR-V spec:
+;; FunctionControlDontInlineMask = 0x2 (2)
+; CHECK-SPIRV: %[[#]] = OpFunction %[[#]] DontInline
+
+; Function Attrs: nounwind optnone noinline
+define spir_func void @_Z3foov() #0 {
+entry:
+  ret void
+}
+
+attributes #0 = { nounwind optnone noinline }
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/DecorationMaxByteOffset.ll b/llvm/test/CodeGen/SPIRV/transcoding/DecorationMaxByteOffset.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/transcoding/DecorationMaxByteOffset.ll
@@ -0,0 +1,24 @@
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+
+; CHECK-SPIRV:     OpName %[[#PTR_ID:]] "ptr"
+; CHECK-SPIRV:     OpName %[[#PTR2_ID:]] "ptr2"
+; CHECK-SPIRV-DAG: OpDecorate %[[#PTR_ID]] MaxByteOffset 12
+; CHECK-SPIRV-DAG: OpDecorate %[[#PTR2_ID]] MaxByteOffset 123
+; CHECK-SPIRV:     %[[#CHAR_T:]] = OpTypeInt 8 0
+; CHECK-SPIRV:     %[[#CHAR_PTR_T:]] = OpTypePointer Workgroup %[[#CHAR_T]]
+; CHECK-SPIRV:     %[[#PTR_ID]] = OpFunctionParameter %[[#CHAR_PTR_T]]
+; CHECK-SPIRV:     %[[#PTR2_ID]] = OpFunctionParameter %[[#CHAR_PTR_T]]
+
+; Function Attrs: nounwind
+define spir_kernel void @worker(i8 addrspace(3)* dereferenceable(12) %ptr) {
+entry:
+  %ptr.addr = alloca i8 addrspace(3)*, align 4
+  store i8 addrspace(3)* %ptr, i8 addrspace(3)** %ptr.addr, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define spir_func void @not_a_kernel(i8 addrspace(3)* dereferenceable(123) %ptr2) {
+entry:
+  ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i32.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i32.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i32.ll
@@ -0,0 +1,14 @@
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+
+; CHECK-SPIRV: %[[#int:]] = OpTypeInt 32
+; CHECK-SPIRV: OpBitReverse %[[#int]]
+
+; Function Attrs: convergent nounwind writeonly
+define spir_kernel void @testBitRev(i32 %a, i32 %b, i32 %c, i32 addrspace(1)* nocapture %res) local_unnamed_addr {
+entry:
+  %call = tail call i32 @llvm.bitreverse.i32(i32 %b)
+  store i32 %call, i32 addrspace(1)* %res, align 4
+  ret void
+}
+
+declare i32 @llvm.bitreverse.i32(i32)
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_v2i16.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_v2i16.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_v2i16.ll
@@ -0,0 +1,15 @@
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+
+; CHECK-SPIRV: %[[#short:]] = OpTypeInt 16
+; CHECK-SPIRV: %[[#short2:]] = OpTypeVector %[[#short]] 2
+; CHECK-SPIRV: OpBitReverse %[[#short2]]
+
+; Function Attrs: convergent nounwind writeonly
+define spir_kernel void @testBitRev(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> addrspace(1)* nocapture %res) local_unnamed_addr {
+entry:
+  %call = tail call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %b)
+  store <2 x i16> %call, <2 x i16> addrspace(1)* %res, align 4
+  ret void
+}
+
+declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>)
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpSwitchEmpty.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpSwitchEmpty.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpSwitchEmpty.ll
@@ -0,0 +1,25 @@
+;; Source:
+;; void kk(int x){
+;;   switch(x) {
+;;     default: return;
+;;   }
+;; }
+
+;; Command:
+;; clang -cc1 -triple spir -emit-llvm -o test/SPIRV/OpSwitchEmpty.ll OpSwitchEmpty.cl -disable-llvm-passes
+
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+
+; CHECK-SPIRV: %[[#X:]] = OpFunctionParameter %[[#]]
+; CHECK-SPIRV: OpSwitch %[[#X]] %[[#DEFAULT:]]{{$}}
+; CHECK-SPIRV: %[[#DEFAULT]] = OpLabel
+
+; Function Attrs: nounwind
+define spir_func void @kk(i32 %x) {
+entry:
+  switch i32 %x, label %sw.default [
+  ]
+
+sw.default:                                       ; preds = %entry
+  ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
@@ -0,0 +1,18 @@
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+
+; CHECK-SPIRV: OpName %[[#vec:]] "vec"
+; CHECK-SPIRV: OpName %[[#index:]] "index"
+; CHECK-SPIRV: OpName %[[#res:]] "res"
+
+; CHECK-SPIRV: %[[#float:]] = OpTypeFloat 32
+; CHECK-SPIRV: %[[#float2:]] = OpTypeVector %[[#float]] 2
+
+; CHECK-SPIRV: %[[#res]] = OpVectorExtractDynamic %[[#float]] %[[#vec]] %[[#index]]
+
+; Function Attrs: nounwind
+define spir_kernel void @test(float addrspace(1)* nocapture %out, <2 x float> %vec, i32 %index) {
+entry:
+  %res = extractelement <2 x float> %vec, i32 %index
+  store float %res, float addrspace(1)* %out, align 4
+  ret void
+}