diff --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll
--- a/llvm/test/CodeGen/RISCV/rv32zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zba.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+zba -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32ZBA
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBA
 
 define signext i16 @sh1add(i64 %0, i16* %1) {
 ; RV32I-LABEL: sh1add:
@@ -271,49 +271,31 @@
 }
 
 define i32 @mul258(i32 %a) {
-; RV32I-LABEL: mul258:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    li a1, 258
-; RV32I-NEXT:    mul a0, a0, a1
-; RV32I-NEXT:    ret
-;
-; RV32ZBA-LABEL: mul258:
-; RV32ZBA:       # %bb.0:
-; RV32ZBA-NEXT:    li a1, 258
-; RV32ZBA-NEXT:    mul a0, a0, a1
-; RV32ZBA-NEXT:    ret
+; CHECK-LABEL: mul258:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 258
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    ret
   %c = mul i32 %a, 258
   ret i32 %c
 }
 
 define i32 @mul260(i32 %a) {
-; RV32I-LABEL: mul260:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    li a1, 260
-; RV32I-NEXT:    mul a0, a0, a1
-; RV32I-NEXT:    ret
-;
-; RV32ZBA-LABEL: mul260:
-; RV32ZBA:       # %bb.0:
-; RV32ZBA-NEXT:    li a1, 260
-; RV32ZBA-NEXT:    mul a0, a0, a1
-; RV32ZBA-NEXT:    ret
+; CHECK-LABEL: mul260:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 260
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    ret
   %c = mul i32 %a, 260
   ret i32 %c
 }
 
 define i32 @mul264(i32 %a) {
-; RV32I-LABEL: mul264:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    li a1, 264
-; RV32I-NEXT:    mul a0, a0, a1
-; RV32I-NEXT:    ret
-;
-; RV32ZBA-LABEL: mul264:
-; RV32ZBA:       # %bb.0:
-; RV32ZBA-NEXT:    li a1, 264
-; RV32ZBA-NEXT:    mul a0, a0, a1
-; RV32ZBA-NEXT:    ret
+; CHECK-LABEL: mul264:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 264
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    ret
   %c = mul i32 %a, 264
   ret i32 %c
 }
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll
--- a/llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll
@@ -1,12 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32ZBB-ZBP-ZBKB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBP-ZBKB
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32ZBB-ZBP-ZBKB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBP-ZBKB
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV32ZBB-ZBP-ZBKB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBP-ZBKB
 
 define i32 @andn_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: andn_i32:
@@ -138,55 +138,30 @@
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define i64 @rol_i64(i64 %a, i64 %b) nounwind {
-; RV32I-LABEL: rol_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a3, a2, 26
-; RV32I-NEXT:    srli a3, a3, 31
-; RV32I-NEXT:    mv a4, a1
-; RV32I-NEXT:    bnez a3, .LBB7_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a4, a0
-; RV32I-NEXT:  .LBB7_2:
-; RV32I-NEXT:    sll a5, a4, a2
-; RV32I-NEXT:    bnez a3, .LBB7_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:  .LBB7_4:
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    not a6, a2
-; RV32I-NEXT:    srl a1, a1, a6
-; RV32I-NEXT:    or a3, a5, a1
-; RV32I-NEXT:    sll a0, a0, a2
-; RV32I-NEXT:    srli a1, a4, 1
-; RV32I-NEXT:    srl a1, a1, a6
-; RV32I-NEXT:    or a1, a0, a1
-; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-ZBP-ZBKB-LABEL: rol_i64:
-; RV32ZBB-ZBP-ZBKB:       # %bb.0:
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a3, a2, 26
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a3, a3, 31
-; RV32ZBB-ZBP-ZBKB-NEXT:    mv a4, a1
-; RV32ZBB-ZBP-ZBKB-NEXT:    bnez a3, .LBB7_2
-; RV32ZBB-ZBP-ZBKB-NEXT:  # %bb.1:
-; RV32ZBB-ZBP-ZBKB-NEXT:    mv a4, a0
-; RV32ZBB-ZBP-ZBKB-NEXT:  .LBB7_2:
-; RV32ZBB-ZBP-ZBKB-NEXT:    sll a5, a4, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    bnez a3, .LBB7_4
-; RV32ZBB-ZBP-ZBKB-NEXT:  # %bb.3:
-; RV32ZBB-ZBP-ZBKB-NEXT:    mv a0, a1
-; RV32ZBB-ZBP-ZBKB-NEXT:  .LBB7_4:
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a1, a0, 1
-; RV32ZBB-ZBP-ZBKB-NEXT:    not a6, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    srl a1, a1, a6
-; RV32ZBB-ZBP-ZBKB-NEXT:    or a3, a5, a1
-; RV32ZBB-ZBP-ZBKB-NEXT:    sll a0, a0, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a1, a4, 1
-; RV32ZBB-ZBP-ZBKB-NEXT:    srl a1, a1, a6
-; RV32ZBB-ZBP-ZBKB-NEXT:    or a1, a0, a1
-; RV32ZBB-ZBP-ZBKB-NEXT:    mv a0, a3
-; RV32ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: rol_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a3, a2, 26
+; CHECK-NEXT:    srli a3, a3, 31
+; CHECK-NEXT:    mv a4, a1
+; CHECK-NEXT:    bnez a3, .LBB7_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    mv a4, a0
+; CHECK-NEXT:  .LBB7_2:
+; CHECK-NEXT:    sll a5, a4, a2
+; CHECK-NEXT:    bnez a3, .LBB7_4
+; CHECK-NEXT:  # %bb.3:
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:  .LBB7_4:
+; CHECK-NEXT:    srli a1, a0, 1
+; CHECK-NEXT:    not a6, a2
+; CHECK-NEXT:    srl a1, a1, a6
+; CHECK-NEXT:    or a3, a5, a1
+; CHECK-NEXT:    sll a0, a0, a2
+; CHECK-NEXT:    srli a1, a4, 1
+; CHECK-NEXT:    srl a1, a1, a6
+; CHECK-NEXT:    or a1, a0, a1
+; CHECK-NEXT:    mv a0, a3
+; CHECK-NEXT:    ret
   %or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
   ret i64 %or
 }
@@ -216,51 +191,28 @@
 declare i64 @llvm.fshr.i64(i64, i64, i64)
 
 define i64 @ror_i64(i64 %a, i64 %b) nounwind {
-; RV32I-LABEL: ror_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a4, a2, 32
-; RV32I-NEXT:    mv a3, a0
-; RV32I-NEXT:    beqz a4, .LBB9_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a3, a1
-; RV32I-NEXT:  .LBB9_2:
-; RV32I-NEXT:    srl a5, a3, a2
-; RV32I-NEXT:    beqz a4, .LBB9_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:  .LBB9_4:
-; RV32I-NEXT:    slli a0, a1, 1
-; RV32I-NEXT:    not a4, a2
-; RV32I-NEXT:    sll a0, a0, a4
-; RV32I-NEXT:    or a0, a0, a5
-; RV32I-NEXT:    srl a1, a1, a2
-; RV32I-NEXT:    slli a2, a3, 1
-; RV32I-NEXT:    sll a2, a2, a4
-; RV32I-NEXT:    or a1, a2, a1
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-ZBP-ZBKB-LABEL: ror_i64:
-; RV32ZBB-ZBP-ZBKB:       # %bb.0:
-; RV32ZBB-ZBP-ZBKB-NEXT:    andi a4, a2, 32
-; RV32ZBB-ZBP-ZBKB-NEXT:    mv a3, a0
-; RV32ZBB-ZBP-ZBKB-NEXT:    beqz a4, .LBB9_2
-; RV32ZBB-ZBP-ZBKB-NEXT:  # %bb.1:
-; RV32ZBB-ZBP-ZBKB-NEXT:    mv a3, a1
-; RV32ZBB-ZBP-ZBKB-NEXT:  .LBB9_2:
-; RV32ZBB-ZBP-ZBKB-NEXT:    srl a5, a3, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    beqz a4, .LBB9_4
-; RV32ZBB-ZBP-ZBKB-NEXT:  # %bb.3:
-; RV32ZBB-ZBP-ZBKB-NEXT:    mv a1, a0
-; RV32ZBB-ZBP-ZBKB-NEXT:  .LBB9_4:
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a0, a1, 1
-; RV32ZBB-ZBP-ZBKB-NEXT:    not a4, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    sll a0, a0, a4
-; RV32ZBB-ZBP-ZBKB-NEXT:    or a0, a0, a5
-; RV32ZBB-ZBP-ZBKB-NEXT:    srl a1, a1, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a2, a3, 1
-; RV32ZBB-ZBP-ZBKB-NEXT:    sll a2, a2, a4
-; RV32ZBB-ZBP-ZBKB-NEXT:    or a1, a2, a1
-; RV32ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: ror_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a4, a2, 32
+; CHECK-NEXT:    mv a3, a0
+; CHECK-NEXT:    beqz a4, .LBB9_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    mv a3, a1
+; CHECK-NEXT:  .LBB9_2:
+; CHECK-NEXT:    srl a5, a3, a2
+; CHECK-NEXT:    beqz a4, .LBB9_4
+; CHECK-NEXT:  # %bb.3:
+; CHECK-NEXT:    mv a1, a0
+; CHECK-NEXT:  .LBB9_4:
+; CHECK-NEXT:    slli a0, a1, 1
+; CHECK-NEXT:    not a4, a2
+; CHECK-NEXT:    sll a0, a0, a4
+; CHECK-NEXT:    or a0, a0, a5
+; CHECK-NEXT:    srl a1, a1, a2
+; CHECK-NEXT:    slli a2, a3, 1
+; CHECK-NEXT:    sll a2, a2, a4
+; CHECK-NEXT:    or a1, a2, a1
+; CHECK-NEXT:    ret
   %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
   ret i64 %or
 }
@@ -298,53 +250,31 @@
 }
 
 define i64 @rori_i64(i64 %a) nounwind {
-; RV32I-LABEL: rori_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    slli a3, a1, 31
-; RV32I-NEXT:    or a2, a3, a2
-; RV32I-NEXT:    srli a1, a1, 1
-; RV32I-NEXT:    slli a0, a0, 31
-; RV32I-NEXT:    or a1, a0, a1
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-ZBP-ZBKB-LABEL: rori_i64:
-; RV32ZBB-ZBP-ZBKB:       # %bb.0:
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a2, a0, 1
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a3, a1, 31
-; RV32ZBB-ZBP-ZBKB-NEXT:    or a2, a3, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a1, a1, 1
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a0, a0, 31
-; RV32ZBB-ZBP-ZBKB-NEXT:    or a1, a0, a1
-; RV32ZBB-ZBP-ZBKB-NEXT:    mv a0, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: rori_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srli a2, a0, 1
+; CHECK-NEXT:    slli a3, a1, 31
+; CHECK-NEXT:    or a2, a3, a2
+; CHECK-NEXT:    srli a1, a1, 1
+; CHECK-NEXT:    slli a0, a0, 31
+; CHECK-NEXT:    or a1, a0, a1
+; CHECK-NEXT:    mv a0, a2
+; CHECK-NEXT:    ret
   %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 63)
   ret i64 %1
 }
 
 define i64 @rori_i64_fshr(i64 %a) nounwind {
-; RV32I-LABEL: rori_i64_fshr:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a2, a1, 31
-; RV32I-NEXT:    slli a3, a0, 1
-; RV32I-NEXT:    or a2, a3, a2
-; RV32I-NEXT:    srli a0, a0, 31
-; RV32I-NEXT:    slli a1, a1, 1
-; RV32I-NEXT:    or a1, a1, a0
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-ZBP-ZBKB-LABEL: rori_i64_fshr:
-; RV32ZBB-ZBP-ZBKB:       # %bb.0:
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a2, a1, 31
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a3, a0, 1
-; RV32ZBB-ZBP-ZBKB-NEXT:    or a2, a3, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a0, a0, 31
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a1, a1, 1
-; RV32ZBB-ZBP-ZBKB-NEXT:    or a1, a1, a0
-; RV32ZBB-ZBP-ZBKB-NEXT:    mv a0, a2
-; RV32ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: rori_i64_fshr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srli a2, a1, 31
+; CHECK-NEXT:    slli a3, a0, 1
+; CHECK-NEXT:    or a2, a3, a2
+; CHECK-NEXT:    srli a0, a0, 31
+; CHECK-NEXT:    slli a1, a1, 1
+; CHECK-NEXT:    or a1, a1, a0
+; CHECK-NEXT:    mv a0, a2
+; CHECK-NEXT:    ret
   %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
   ret i64 %1
 }
@@ -403,17 +333,11 @@
 }
 
 define i8 @srli_i8(i8 %a) nounwind {
-; RV32I-LABEL: srli_i8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    srli a0, a0, 30
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-ZBP-ZBKB-LABEL: srli_i8:
-; RV32ZBB-ZBP-ZBKB:       # %bb.0:
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a0, a0, 24
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a0, a0, 30
-; RV32ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: srli_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 24
+; CHECK-NEXT:    srli a0, a0, 30
+; CHECK-NEXT:    ret
   %1 = lshr i8 %a, 6
   ret i8 %1
 }
@@ -421,17 +345,11 @@
 ; We could use sext.b+srai, but slli+srai offers more opportunities for
 ; comppressed instructions.
 define i8 @srai_i8(i8 %a) nounwind {
-; RV32I-LABEL: srai_i8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    srai a0, a0, 29
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-ZBP-ZBKB-LABEL: srai_i8:
-; RV32ZBB-ZBP-ZBKB:       # %bb.0:
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a0, a0, 24
-; RV32ZBB-ZBP-ZBKB-NEXT:    srai a0, a0, 29
-; RV32ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: srai_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 24
+; CHECK-NEXT:    srai a0, a0, 29
+; CHECK-NEXT:    ret
   %1 = ashr i8 %a, 5
   ret i8 %1
 }
@@ -439,17 +357,11 @@
 ; We could use zext.h+srli, but slli+srli offers more opportunities for
 ; comppressed instructions.
 define i16 @srli_i16(i16 %a) nounwind {
-; RV32I-LABEL: srli_i16:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a0, a0, 16
-; RV32I-NEXT:    srli a0, a0, 22
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-ZBP-ZBKB-LABEL: srli_i16:
-; RV32ZBB-ZBP-ZBKB:       # %bb.0:
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a0, a0, 16
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a0, a0, 22
-; RV32ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: srli_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 16
+; CHECK-NEXT:    srli a0, a0, 22
+; CHECK-NEXT:    ret
   %1 = lshr i16 %a, 6
   ret i16 %1
 }
@@ -457,17 +369,11 @@
 ; We could use sext.h+srai, but slli+srai offers more opportunities for
 ; comppressed instructions.
 define i16 @srai_i16(i16 %a) nounwind {
-; RV32I-LABEL: srai_i16:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a0, a0, 16
-; RV32I-NEXT:    srai a0, a0, 25
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-ZBP-ZBKB-LABEL: srai_i16:
-; RV32ZBB-ZBP-ZBKB:       # %bb.0:
-; RV32ZBB-ZBP-ZBKB-NEXT:    slli a0, a0, 16
-; RV32ZBB-ZBP-ZBKB-NEXT:    srai a0, a0, 25
-; RV32ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: srai_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 16
+; CHECK-NEXT:    srai a0, a0, 25
+; CHECK-NEXT:    ret
   %1 = ashr i16 %a, 9
   ret i16 %1
 }
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll
--- a/llvm/test/CodeGen/RISCV/rv32zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32ZBB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBB
 
 declare i32 @llvm.ctlz.i32(i32, i1)
 
@@ -750,27 +750,16 @@
 declare i64 @llvm.abs.i64(i64, i1 immarg)
 
 define i64 @abs_i64(i64 %x) {
-; RV32I-LABEL: abs_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    bgez a1, .LBB19_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    snez a2, a0
-; RV32I-NEXT:    neg a0, a0
-; RV32I-NEXT:    add a1, a1, a2
-; RV32I-NEXT:    neg a1, a1
-; RV32I-NEXT:  .LBB19_2:
-; RV32I-NEXT:    ret
-;
-; RV32ZBB-LABEL: abs_i64:
-; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    bgez a1, .LBB19_2
-; RV32ZBB-NEXT:  # %bb.1:
-; RV32ZBB-NEXT:    snez a2, a0
-; RV32ZBB-NEXT:    neg a0, a0
-; RV32ZBB-NEXT:    add a1, a1, a2
-; RV32ZBB-NEXT:    neg a1, a1
-; RV32ZBB-NEXT:  .LBB19_2:
-; RV32ZBB-NEXT:    ret
+; CHECK-LABEL: abs_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    bgez a1, .LBB19_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    snez a2, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    add a1, a1, a2
+; CHECK-NEXT:    neg a1, a1
+; CHECK-NEXT:  .LBB19_2:
+; CHECK-NEXT:    ret
   %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
   ret i64 %abs
 }
diff --git a/llvm/test/CodeGen/RISCV/rv32zbp-zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbp-zbkb.ll
--- a/llvm/test/CodeGen/RISCV/rv32zbp-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbp-zbkb.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32ZBP-ZBKB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBP-ZBKB
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32ZBP-ZBKB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBP-ZBKB
 
 define i32 @pack_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: pack_i32:
@@ -31,15 +31,10 @@
 ; extensions introduce instructions suitable for this pattern.
 
 define i64 @pack_i64(i64 %a, i64 %b) nounwind {
-; RV32I-LABEL: pack_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a1, a2
-; RV32I-NEXT:    ret
-;
-; RV32ZBP-ZBKB-LABEL: pack_i64:
-; RV32ZBP-ZBKB:       # %bb.0:
-; RV32ZBP-ZBKB-NEXT:    mv a1, a2
-; RV32ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: pack_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mv a1, a2
+; CHECK-NEXT:    ret
   %shl = and i64 %a, 4294967295
   %shl1 = shl i64 %b, 32
   %or = or i64 %shl1, %shl
@@ -52,17 +47,11 @@
 ; extensions introduce instructions suitable for this pattern.
 
 define i64 @packu_i64(i64 %a, i64 %b) nounwind {
-; RV32I-LABEL: packu_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:    mv a1, a3
-; RV32I-NEXT:    ret
-;
-; RV32ZBP-ZBKB-LABEL: packu_i64:
-; RV32ZBP-ZBKB:       # %bb.0:
-; RV32ZBP-ZBKB-NEXT:    mv a0, a1
-; RV32ZBP-ZBKB-NEXT:    mv a1, a3
-; RV32ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: packu_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    mv a1, a3
+; CHECK-NEXT:    ret
   %shr = lshr i64 %a, 32
   %shr1 = and i64 %b, -4294967296
   %or = or i64 %shr1, %shr
diff --git a/llvm/test/CodeGen/RISCV/rv32zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbp.ll
--- a/llvm/test/CodeGen/RISCV/rv32zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbp.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32ZBP
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBP
 
 define i32 @gorc1_i32(i32 %a) nounwind {
 ; RV32I-LABEL: gorc1_i32:
@@ -3159,27 +3159,16 @@
 }
 
 define i32 @or_shl_fshl(i32 %x, i32 %y, i32 %s) {
-; RV32I-LABEL: or_shl_fshl:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    sll a3, a1, a2
-; RV32I-NEXT:    sll a0, a0, a2
-; RV32I-NEXT:    not a2, a2
-; RV32I-NEXT:    srli a1, a1, 1
-; RV32I-NEXT:    srl a1, a1, a2
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    or a0, a0, a3
-; RV32I-NEXT:    ret
-;
-; RV32ZBP-LABEL: or_shl_fshl:
-; RV32ZBP:       # %bb.0:
-; RV32ZBP-NEXT:    sll a3, a1, a2
-; RV32ZBP-NEXT:    sll a0, a0, a2
-; RV32ZBP-NEXT:    not a2, a2
-; RV32ZBP-NEXT:    srli a1, a1, 1
-; RV32ZBP-NEXT:    srl a1, a1, a2
-; RV32ZBP-NEXT:    or a0, a0, a1
-; RV32ZBP-NEXT:    or a0, a0, a3
-; RV32ZBP-NEXT:    ret
+; CHECK-LABEL: or_shl_fshl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll a3, a1, a2
+; CHECK-NEXT:    sll a0, a0, a2
+; CHECK-NEXT:    not a2, a2
+; CHECK-NEXT:    srli a1, a1, 1
+; CHECK-NEXT:    srl a1, a1, a2
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    or a0, a0, a3
+; CHECK-NEXT:    ret
   %shy = shl i32 %y, %s
   %fun = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %s)
   %or = or i32 %fun, %shy
@@ -3210,27 +3199,16 @@
 }
 
 define i32 @or_shl_fshl_commute(i32 %x, i32 %y, i32 %s) {
-; RV32I-LABEL: or_shl_fshl_commute:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    sll a3, a1, a2
-; RV32I-NEXT:    sll a0, a0, a2
-; RV32I-NEXT:    not a2, a2
-; RV32I-NEXT:    srli a1, a1, 1
-; RV32I-NEXT:    srl a1, a1, a2
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    or a0, a3, a0
-; RV32I-NEXT:    ret
-;
-; RV32ZBP-LABEL: or_shl_fshl_commute:
-; RV32ZBP:       # %bb.0:
-; RV32ZBP-NEXT:    sll a3, a1, a2
-; RV32ZBP-NEXT:    sll a0, a0, a2
-; RV32ZBP-NEXT:    not a2, a2
-; RV32ZBP-NEXT:    srli a1, a1, 1
-; RV32ZBP-NEXT:    srl a1, a1, a2
-; RV32ZBP-NEXT:    or a0, a0, a1
-; RV32ZBP-NEXT:    or a0, a3, a0
-; RV32ZBP-NEXT:    ret
+; CHECK-LABEL: or_shl_fshl_commute:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll a3, a1, a2
+; CHECK-NEXT:    sll a0, a0, a2
+; CHECK-NEXT:    not a2, a2
+; CHECK-NEXT:    srli a1, a1, 1
+; CHECK-NEXT:    srl a1, a1, a2
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    or a0, a3, a0
+; CHECK-NEXT:    ret
   %shy = shl i32 %y, %s
   %fun = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %s)
   %or = or i32 %shy, %fun
@@ -3261,27 +3239,16 @@
 }
 
 define i32 @or_lshr_fshr(i32 %x, i32 %y, i32 %s) {
-; RV32I-LABEL: or_lshr_fshr:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srl a3, a1, a2
-; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    not a2, a2
-; RV32I-NEXT:    slli a1, a1, 1
-; RV32I-NEXT:    sll a1, a1, a2
-; RV32I-NEXT:    or a0, a1, a0
-; RV32I-NEXT:    or a0, a0, a3
-; RV32I-NEXT:    ret
-;
-; RV32ZBP-LABEL: or_lshr_fshr:
-; RV32ZBP:       # %bb.0:
-; RV32ZBP-NEXT:    srl a3, a1, a2
-; RV32ZBP-NEXT:    srl a0, a0, a2
-; RV32ZBP-NEXT:    not a2, a2
-; RV32ZBP-NEXT:    slli a1, a1, 1
-; RV32ZBP-NEXT:    sll a1, a1, a2
-; RV32ZBP-NEXT:    or a0, a1, a0
-; RV32ZBP-NEXT:    or a0, a0, a3
-; RV32ZBP-NEXT:    ret
+; CHECK-LABEL: or_lshr_fshr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl a3, a1, a2
+; CHECK-NEXT:    srl a0, a0, a2
+; CHECK-NEXT:    not a2, a2
+; CHECK-NEXT:    slli a1, a1, 1
+; CHECK-NEXT:    sll a1, a1, a2
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    or a0, a0, a3
+; CHECK-NEXT:    ret
   %shy = lshr i32 %y, %s
   %fun = call i32 @llvm.fshr.i32(i32 %y, i32 %x, i32 %s)
   %or = or i32 %fun, %shy
@@ -3312,27 +3279,16 @@
 }
 
 define i32 @or_lshr_fshr_commute(i32 %x, i32 %y, i32 %s) {
-; RV32I-LABEL: or_lshr_fshr_commute:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srl a3, a1, a2
-; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    not a2, a2
-; RV32I-NEXT:    slli a1, a1, 1
-; RV32I-NEXT:    sll a1, a1, a2
-; RV32I-NEXT:    or a0, a1, a0
-; RV32I-NEXT:    or a0, a3, a0
-; RV32I-NEXT:    ret
-;
-; RV32ZBP-LABEL: or_lshr_fshr_commute:
-; RV32ZBP:       # %bb.0:
-; RV32ZBP-NEXT:    srl a3, a1, a2
-; RV32ZBP-NEXT:    srl a0, a0, a2
-; RV32ZBP-NEXT:    not a2, a2
-; RV32ZBP-NEXT:    slli a1, a1, 1
-; RV32ZBP-NEXT:    sll a1, a1, a2
-; RV32ZBP-NEXT:    or a0, a1, a0
-; RV32ZBP-NEXT:    or a0, a3, a0
-; RV32ZBP-NEXT:    ret
+; CHECK-LABEL: or_lshr_fshr_commute:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl a3, a1, a2
+; CHECK-NEXT:    srl a0, a0, a2
+; CHECK-NEXT:    not a2, a2
+; CHECK-NEXT:    slli a1, a1, 1
+; CHECK-NEXT:    sll a1, a1, a2
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    or a0, a3, a0
+; CHECK-NEXT:    ret
   %shy = lshr i32 %y, %s
   %fun = call i32 @llvm.fshr.i32(i32 %y, i32 %x, i32 %s)
   %or = or i32 %shy, %fun
@@ -3363,23 +3319,14 @@
 }
 
 define i32 @or_shl_fshl_simplify(i32 %x, i32 %y, i32 %s) {
-; RV32I-LABEL: or_shl_fshl_simplify:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    sll a1, a1, a2
-; RV32I-NEXT:    not a2, a2
-; RV32I-NEXT:    srli a0, a0, 1
-; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    or a0, a1, a0
-; RV32I-NEXT:    ret
-;
-; RV32ZBP-LABEL: or_shl_fshl_simplify:
-; RV32ZBP:       # %bb.0:
-; RV32ZBP-NEXT:    sll a1, a1, a2
-; RV32ZBP-NEXT:    not a2, a2
-; RV32ZBP-NEXT:    srli a0, a0, 1
-; RV32ZBP-NEXT:    srl a0, a0, a2
-; RV32ZBP-NEXT:    or a0, a1, a0
-; RV32ZBP-NEXT:    ret
+; CHECK-LABEL: or_shl_fshl_simplify:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll a1, a1, a2
+; CHECK-NEXT:    not a2, a2
+; CHECK-NEXT:    srli a0, a0, 1
+; CHECK-NEXT:    srl a0, a0, a2
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
   %shy = shl i32 %y, %s
   %fun = call i32 @llvm.fshl.i32(i32 %y, i32 %x, i32 %s)
   %or = or i32 %fun, %shy
@@ -3387,23 +3334,14 @@
 }
 
 define i32 @or_lshr_fshr_simplify(i32 %x, i32 %y, i32 %s) {
-; RV32I-LABEL: or_lshr_fshr_simplify:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srl a1, a1, a2
-; RV32I-NEXT:    not a2, a2
-; RV32I-NEXT:    slli a0, a0, 1
-; RV32I-NEXT:    sll a0, a0, a2
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    ret
-;
-; RV32ZBP-LABEL: or_lshr_fshr_simplify:
-; RV32ZBP:       # %bb.0:
-; RV32ZBP-NEXT:    srl a1, a1, a2
-; RV32ZBP-NEXT:    not a2, a2
-; RV32ZBP-NEXT:    slli a0, a0, 1
-; RV32ZBP-NEXT:    sll a0, a0, a2
-; RV32ZBP-NEXT:    or a0, a0, a1
-; RV32ZBP-NEXT:    ret
+; CHECK-LABEL: or_lshr_fshr_simplify:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl a1, a1, a2
+; CHECK-NEXT:    not a2, a2
+; CHECK-NEXT:    slli a0, a0, 1
+; CHECK-NEXT:    sll a0, a0, a2
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    ret
   %shy = lshr i32 %y, %s
   %fun = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %s)
   %or = or i32 %shy, %fun
diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll
--- a/llvm/test/CodeGen/RISCV/rv32zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32ZBS
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBS
 
 define i32 @bclr_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: bclr_i32:
@@ -278,43 +278,24 @@
 ; extensions introduce instructions suitable for this pattern.
 
 define i64 @bext_i64(i64 %a, i64 %b) nounwind {
-; RV32I-LABEL: bext_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a3, a2, 63
-; RV32I-NEXT:    addi a4, a3, -32
-; RV32I-NEXT:    bltz a4, .LBB12_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    srl a0, a1, a4
-; RV32I-NEXT:    j .LBB12_3
-; RV32I-NEXT:  .LBB12_2:
-; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    slli a1, a1, 1
-; RV32I-NEXT:    xori a2, a3, 31
-; RV32I-NEXT:    sll a1, a1, a2
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:  .LBB12_3:
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    ret
-;
-; RV32ZBS-LABEL: bext_i64:
-; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    andi a3, a2, 63
-; RV32ZBS-NEXT:    addi a4, a3, -32
-; RV32ZBS-NEXT:    bltz a4, .LBB12_2
-; RV32ZBS-NEXT:  # %bb.1:
-; RV32ZBS-NEXT:    srl a0, a1, a4
-; RV32ZBS-NEXT:    j .LBB12_3
-; RV32ZBS-NEXT:  .LBB12_2:
-; RV32ZBS-NEXT:    srl a0, a0, a2
-; RV32ZBS-NEXT:    slli a1, a1, 1
-; RV32ZBS-NEXT:    xori a2, a3, 31
-; RV32ZBS-NEXT:    sll a1, a1, a2
-; RV32ZBS-NEXT:    or a0, a0, a1
-; RV32ZBS-NEXT:  .LBB12_3:
-; RV32ZBS-NEXT:    andi a0, a0, 1
-; RV32ZBS-NEXT:    li a1, 0
-; RV32ZBS-NEXT:    ret
+; CHECK-LABEL: bext_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a3, a2, 63
+; CHECK-NEXT:    addi a4, a3, -32
+; CHECK-NEXT:    bltz a4, .LBB12_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    srl a0, a1, a4
+; CHECK-NEXT:    j .LBB12_3
+; CHECK-NEXT:  .LBB12_2:
+; CHECK-NEXT:    srl a0, a0, a2
+; CHECK-NEXT:    slli a1, a1, 1
+; CHECK-NEXT:    xori a2, a3, 31
+; CHECK-NEXT:    sll a1, a1, a2
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:  .LBB12_3:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    li a1, 0
+; CHECK-NEXT:    ret
   %conv = and i64 %b, 63
   %shr = lshr i64 %a, %conv
   %and1 = and i64 %shr, 1
@@ -356,15 +337,10 @@
 }
 
 define i32 @bclri_i32_10(i32 %a) nounwind {
-; RV32I-LABEL: bclri_i32_10:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, -1025
-; RV32I-NEXT:    ret
-;
-; RV32ZBS-LABEL: bclri_i32_10:
-; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    andi a0, a0, -1025
-; RV32ZBS-NEXT:    ret
+; CHECK-LABEL: bclri_i32_10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, -1025
+; CHECK-NEXT:    ret
   %and = and i32 %a, -1025
   ret i32 %and
 }
@@ -485,15 +461,10 @@
 }
 
 define i32 @bseti_i32_10(i32 %a) nounwind {
-; RV32I-LABEL: bseti_i32_10:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    ori a0, a0, 1024
-; RV32I-NEXT:    ret
-;
-; RV32ZBS-LABEL: bseti_i32_10:
-; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    ori a0, a0, 1024
-; RV32ZBS-NEXT:    ret
+; CHECK-LABEL: bseti_i32_10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ori a0, a0, 1024
+; CHECK-NEXT:    ret
   %or = or i32 %a, 1024
   ret i32 %or
 }
@@ -545,15 +516,10 @@
 }
 
 define i32 @binvi_i32_10(i32 %a) nounwind {
-; RV32I-LABEL: binvi_i32_10:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    xori a0, a0, 1024
-; RV32I-NEXT:    ret
-;
-; RV32ZBS-LABEL: binvi_i32_10:
-; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    xori a0, a0, 1024
-; RV32ZBS-NEXT:    ret
+; CHECK-LABEL: binvi_i32_10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xori a0, a0, 1024
+; CHECK-NEXT:    ret
   %xor = xor i32 %a, 1024
   ret i32 %xor
 }
@@ -639,15 +605,10 @@
 }
 
 define i32 @xor_i32_96(i32 %a) nounwind {
-; RV32I-LABEL: xor_i32_96:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    xori a0, a0, 96
-; RV32I-NEXT:    ret
-;
-; RV32ZBS-LABEL: xor_i32_96:
-; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    xori a0, a0, 96
-; RV32ZBS-NEXT:    ret
+; CHECK-LABEL: xor_i32_96:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xori a0, a0, 96
+; CHECK-NEXT:    ret
   %xor = xor i32 %a, 96
   ret i32 %xor
 }
@@ -704,15 +665,10 @@
 }
 
 define i32 @or_i32_96(i32 %a) nounwind {
-; RV32I-LABEL: or_i32_96:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    ori a0, a0, 96
-; RV32I-NEXT:    ret
-;
-; RV32ZBS-LABEL: or_i32_96:
-; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    ori a0, a0, 96
-; RV32ZBS-NEXT:    ret
+; CHECK-LABEL: or_i32_96:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ori a0, a0, 96
+; CHECK-NEXT:    ret
   %or = or i32 %a, 96
   ret i32 %or
 }
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV64ZBA,RV64ZBANOZBB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBA,RV64ZBANOZBB
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zba,+zbb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV64ZBA,RV64ZBAZBB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBA,RV64ZBAZBB
 
 define i64 @slliuw(i64 %a) nounwind {
 ; RV64I-LABEL: slliuw:
@@ -528,51 +528,33 @@
 }
 
 define i64 @sh1add_imm(i64 %0) {
-; RV64I-LABEL: sh1add_imm:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 1
-; RV64I-NEXT:    addi a0, a0, 5
-; RV64I-NEXT:    ret
-;
-; RV64ZBA-LABEL: sh1add_imm:
-; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    slli a0, a0, 1
-; RV64ZBA-NEXT:    addi a0, a0, 5
-; RV64ZBA-NEXT:    ret
+; CHECK-LABEL: sh1add_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 1
+; CHECK-NEXT:    addi a0, a0, 5
+; CHECK-NEXT:    ret
   %a = shl i64 %0, 1
   %b = add i64 %a, 5
   ret i64 %b
 }
 
 define i64 @sh2add_imm(i64 %0) {
-; RV64I-LABEL: sh2add_imm:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 2
-; RV64I-NEXT:    addi a0, a0, -6
-; RV64I-NEXT:    ret
-;
-; RV64ZBA-LABEL: sh2add_imm:
-; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    slli a0, a0, 2
-; RV64ZBA-NEXT:    addi a0, a0, -6
-; RV64ZBA-NEXT:    ret
+; CHECK-LABEL: sh2add_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 2
+; CHECK-NEXT:    addi a0, a0, -6
+; CHECK-NEXT:    ret
   %a = shl i64 %0, 2
   %b = add i64 %a, -6
   ret i64 %b
 }
 
 define i64 @sh3add_imm(i64 %0) {
-; RV64I-LABEL: sh3add_imm:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 3
-; RV64I-NEXT:    ori a0, a0, 7
-; RV64I-NEXT:    ret
-;
-; RV64ZBA-LABEL: sh3add_imm:
-; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    slli a0, a0, 3
-; RV64ZBA-NEXT:    ori a0, a0, 7
-; RV64ZBA-NEXT:    ret
+; CHECK-LABEL: sh3add_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    ori a0, a0, 7
+; CHECK-NEXT:    ret
   %a = shl i64 %0, 3
   %b = add i64 %a, 7
   ret i64 %b
@@ -654,49 +636,31 @@
 }
 
 define i64 @mul258(i64 %a) {
-; RV64I-LABEL: mul258:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 258
-; RV64I-NEXT:    mul a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64ZBA-LABEL: mul258:
-; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    li a1, 258
-; RV64ZBA-NEXT:    mul a0, a0, a1
-; RV64ZBA-NEXT:    ret
+; CHECK-LABEL: mul258:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 258
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    ret
   %c = mul i64 %a, 258
   ret i64 %c
 }
 
 define i64 @mul260(i64 %a) {
-; RV64I-LABEL: mul260:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 260
-; RV64I-NEXT:    mul a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64ZBA-LABEL: mul260:
-; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    li a1, 260
-; RV64ZBA-NEXT:    mul a0, a0, a1
-; RV64ZBA-NEXT:    ret
+; CHECK-LABEL: mul260:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 260
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    ret
   %c = mul i64 %a, 260
   ret i64 %c
 }
 
 define i64 @mul264(i64 %a) {
-; RV64I-LABEL: mul264:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 264
-; RV64I-NEXT:    mul a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64ZBA-LABEL: mul264:
-; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    li a1, 264
-; RV64ZBA-NEXT:    mul a0, a0, a1
-; RV64ZBA-NEXT:    ret
+; CHECK-LABEL: mul264:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 264
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    ret
   %c = mul i64 %a, 264
   ret i64 %c
 }
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbp-zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbp-zbkb.ll
--- a/llvm/test/CodeGen/RISCV/rv64zbb-zbp-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbp-zbkb.ll
@@ -1,12 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV64I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV64ZBB-ZBP-ZBKB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBB-ZBP-ZBKB
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV64ZBB-ZBP-ZBKB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBB-ZBP-ZBKB
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=RV64ZBB-ZBP-ZBKB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBB-ZBP-ZBKB
 
 define signext i32 @andn_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: andn_i32:
@@ -336,19 +336,12 @@
 ; instead of having the same input to both shifts it has different inputs. Make
 ; sure we don't match it as a roriw.
 define signext i32 @not_rori_i32(i32 signext %x, i32 signext %y) nounwind {
-; RV64I-LABEL: not_rori_i32:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slliw a0, a0, 31
-; RV64I-NEXT:    srliw a1, a1, 1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64ZBB-ZBP-ZBKB-LABEL: not_rori_i32:
-; RV64ZBB-ZBP-ZBKB:       # %bb.0:
-; RV64ZBB-ZBP-ZBKB-NEXT:    slliw a0, a0, 31
-; RV64ZBB-ZBP-ZBKB-NEXT:    srliw a1, a1, 1
-; RV64ZBB-ZBP-ZBKB-NEXT:    or a0, a0, a1
-; RV64ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: not_rori_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slliw a0, a0, 31
+; CHECK-NEXT:    srliw a1, a1, 1
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    ret
   %a = shl i32 %x, 31
   %b = lshr i32 %y, 1
   %c = or i32 %a, %b
@@ -359,25 +352,15 @@
 ; than 32 bits so the lshr doesn't shift zeroes into the lower 32 bits. Make
 ; sure we don't match it to roriw.
 define i64 @roriw_bug(i64 %x) nounwind {
-; RV64I-LABEL: roriw_bug:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 31
-; RV64I-NEXT:    andi a0, a0, -2
-; RV64I-NEXT:    srli a2, a0, 1
-; RV64I-NEXT:    or a1, a1, a2
-; RV64I-NEXT:    sext.w a1, a1
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64ZBB-ZBP-ZBKB-LABEL: roriw_bug:
-; RV64ZBB-ZBP-ZBKB:       # %bb.0:
-; RV64ZBB-ZBP-ZBKB-NEXT:    slli a1, a0, 31
-; RV64ZBB-ZBP-ZBKB-NEXT:    andi a0, a0, -2
-; RV64ZBB-ZBP-ZBKB-NEXT:    srli a2, a0, 1
-; RV64ZBB-ZBP-ZBKB-NEXT:    or a1, a1, a2
-; RV64ZBB-ZBP-ZBKB-NEXT:    sext.w a1, a1
-; RV64ZBB-ZBP-ZBKB-NEXT:    xor a0, a0, a1
-; RV64ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: roriw_bug:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a1, a0, 31
+; CHECK-NEXT:    andi a0, a0, -2
+; CHECK-NEXT:    srli a2, a0, 1
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    sext.w a1, a1
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    ret
   %a = shl i64 %x, 31
   %b = and i64 %x, 18446744073709551614
   %c = lshr i64 %b, 1
@@ -457,17 +440,11 @@
 }
 
 define i8 @srli_i8(i8 %a) nounwind {
-; RV64I-LABEL: srli_i8:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 56
-; RV64I-NEXT:    srli a0, a0, 62
-; RV64I-NEXT:    ret
-;
-; RV64ZBB-ZBP-ZBKB-LABEL: srli_i8:
-; RV64ZBB-ZBP-ZBKB:       # %bb.0:
-; RV64ZBB-ZBP-ZBKB-NEXT:    slli a0, a0, 56
-; RV64ZBB-ZBP-ZBKB-NEXT:    srli a0, a0, 62
-; RV64ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: srli_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 56
+; CHECK-NEXT:    srli a0, a0, 62
+; CHECK-NEXT:    ret
   %1 = lshr i8 %a, 6
   ret i8 %1
 }
@@ -475,17 +452,11 @@
 ; We could use sext.b+srai, but slli+srai offers more opportunities for
 ; comppressed instructions.
 define i8 @srai_i8(i8 %a) nounwind {
-; RV64I-LABEL: srai_i8:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 56
-; RV64I-NEXT:    srai a0, a0, 61
-; RV64I-NEXT:    ret
-;
-; RV64ZBB-ZBP-ZBKB-LABEL: srai_i8:
-; RV64ZBB-ZBP-ZBKB:       # %bb.0:
-; RV64ZBB-ZBP-ZBKB-NEXT:    slli a0, a0, 56
-; RV64ZBB-ZBP-ZBKB-NEXT:    srai a0, a0, 61
-; RV64ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: srai_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 56
+; CHECK-NEXT:    srai a0, a0, 61
+; CHECK-NEXT:    ret
   %1 = ashr i8 %a, 5
   ret i8 %1
 }
@@ -493,17 +464,11 @@
 ; We could use zext.h+srli, but slli+srli offers more opportunities for
 ; comppressed instructions.
 define i16 @srli_i16(i16 %a) nounwind {
-; RV64I-LABEL: srli_i16:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 48
-; RV64I-NEXT:    srli a0, a0, 54
-; RV64I-NEXT:    ret
-;
-; RV64ZBB-ZBP-ZBKB-LABEL: srli_i16:
-; RV64ZBB-ZBP-ZBKB:       # %bb.0:
-; RV64ZBB-ZBP-ZBKB-NEXT:    slli a0, a0, 48
-; RV64ZBB-ZBP-ZBKB-NEXT:    srli a0, a0, 54
-; RV64ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: srli_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 48
+; CHECK-NEXT:    srli a0, a0, 54
+; CHECK-NEXT:    ret
   %1 = lshr i16 %a, 6
   ret i16 %1
 }
@@ -511,17 +476,11 @@
 ; We could use sext.h+srai, but slli+srai offers more opportunities for
 ; comppressed instructions.
 define i16 @srai_i16(i16 %a) nounwind {
-; RV64I-LABEL: srai_i16:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 48
-; RV64I-NEXT:    srai a0, a0, 57
-; RV64I-NEXT:    ret
-;
-; RV64ZBB-ZBP-ZBKB-LABEL: srai_i16:
-; RV64ZBB-ZBP-ZBKB:       # %bb.0:
-; RV64ZBB-ZBP-ZBKB-NEXT:    slli a0, a0, 48
-; RV64ZBB-ZBP-ZBKB-NEXT:    srai a0, a0, 57
-; RV64ZBB-ZBP-ZBKB-NEXT:    ret
+; CHECK-LABEL: srai_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 48
+; CHECK-NEXT:    srai a0, a0, 57
+; CHECK-NEXT:    ret
   %1 = ashr i16 %a, 9
   ret i16 %1
 }
diff --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64zbs.ll
--- a/llvm/test/CodeGen/RISCV/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV64ZBS
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBS
 
 define signext i32 @bclr_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: bclr_i32:
@@ -429,15 +429,10 @@
 }
 
 define signext i32 @bclri_i32_10(i32 signext %a) nounwind {
-; RV64I-LABEL: bclri_i32_10:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, -1025
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: bclri_i32_10:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    andi a0, a0, -1025
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: bclri_i32_10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, -1025
+; CHECK-NEXT:    ret
   %and = and i32 %a, -1025
   ret i32 %and
 }
@@ -475,31 +470,20 @@
 }
 
 define signext i32 @bclri_i32_31(i32 signext %a) nounwind {
-; RV64I-LABEL: bclri_i32_31:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 33
-; RV64I-NEXT:    srli a0, a0, 33
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: bclri_i32_31:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    slli a0, a0, 33
-; RV64ZBS-NEXT:    srli a0, a0, 33
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: bclri_i32_31:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 33
+; CHECK-NEXT:    srli a0, a0, 33
+; CHECK-NEXT:    ret
   %and = and i32 %a, -2147483649
   ret i32 %and
 }
 
 define i64 @bclri_i64_10(i64 %a) nounwind {
-; RV64I-LABEL: bclri_i64_10:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, -1025
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: bclri_i64_10:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    andi a0, a0, -1025
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: bclri_i64_10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, -1025
+; CHECK-NEXT:    ret
   %and = and i64 %a, -1025
   ret i64 %and
 }
@@ -619,15 +603,10 @@
 }
 
 define signext i32 @bseti_i32_10(i32 signext %a) nounwind {
-; RV64I-LABEL: bseti_i32_10:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    ori a0, a0, 1024
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: bseti_i32_10:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    ori a0, a0, 1024
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: bseti_i32_10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ori a0, a0, 1024
+; CHECK-NEXT:    ret
   %or = or i32 %a, 1024
   ret i32 %or
 }
@@ -664,31 +643,20 @@
 }
 
 define signext i32 @bseti_i32_31(i32 signext %a) nounwind {
-; RV64I-LABEL: bseti_i32_31:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 524288
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: bseti_i32_31:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    lui a1, 524288
-; RV64ZBS-NEXT:    or a0, a0, a1
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: bseti_i32_31:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a1, 524288
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    ret
   %or = or i32 %a, 2147483648
   ret i32 %or
 }
 
 define i64 @bseti_i64_10(i64 %a) nounwind {
-; RV64I-LABEL: bseti_i64_10:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    ori a0, a0, 1024
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: bseti_i64_10:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    ori a0, a0, 1024
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: bseti_i64_10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ori a0, a0, 1024
+; CHECK-NEXT:    ret
   %or = or i64 %a, 1024
   ret i64 %or
 }
@@ -773,15 +741,10 @@
 }
 
 define signext i32 @binvi_i32_10(i32 signext %a) nounwind {
-; RV64I-LABEL: binvi_i32_10:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    xori a0, a0, 1024
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: binvi_i32_10:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    xori a0, a0, 1024
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: binvi_i32_10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xori a0, a0, 1024
+; CHECK-NEXT:    ret
   %xor = xor i32 %a, 1024
   ret i32 %xor
 }
@@ -818,31 +781,20 @@
 }
 
 define signext i32 @binvi_i32_31(i32 signext %a) nounwind {
-; RV64I-LABEL: binvi_i32_31:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 524288
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: binvi_i32_31:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    lui a1, 524288
-; RV64ZBS-NEXT:    xor a0, a0, a1
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: binvi_i32_31:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a1, 524288
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    ret
   %xor = xor i32 %a, 2147483648
   ret i32 %xor
 }
 
 define i64 @binvi_i64_10(i64 %a) nounwind {
-; RV64I-LABEL: binvi_i64_10:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    xori a0, a0, 1024
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: binvi_i64_10:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    xori a0, a0, 1024
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: binvi_i64_10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xori a0, a0, 1024
+; CHECK-NEXT:    ret
   %xor = xor i64 %a, 1024
   ret i64 %xor
 }
@@ -962,15 +914,10 @@
 }
 
 define i64 @xor_i64_96(i64 %a) nounwind {
-; RV64I-LABEL: xor_i64_96:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    xori a0, a0, 96
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: xor_i64_96:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    xori a0, a0, 96
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: xor_i64_96:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xori a0, a0, 96
+; CHECK-NEXT:    ret
   %xor = xor i64 %a, 96
   ret i64 %xor
 }
@@ -1028,15 +975,10 @@
 }
 
 define i64 @or_i64_96(i64 %a) nounwind {
-; RV64I-LABEL: or_i64_96:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    ori a0, a0, 96
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: or_i64_96:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    ori a0, a0, 96
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: or_i64_96:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ori a0, a0, 96
+; CHECK-NEXT:    ret
   %or = or i64 %a, 96
   ret i64 %or
 }